CN102879963B - Array substrate and preparation method thereof, liquid crystal display panel and liquid crystal display device - Google Patents
Array substrate and preparation method thereof, liquid crystal display panel and liquid crystal display device Download PDFInfo
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- CN102879963B CN102879963B CN201210374367.0A CN201210374367A CN102879963B CN 102879963 B CN102879963 B CN 102879963B CN 201210374367 A CN201210374367 A CN 201210374367A CN 102879963 B CN102879963 B CN 102879963B
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Abstract
The invention relates to the technical field of storage and discloses an array substrate which comprises a thin-film transistor and a flash memory structure. The flash memory structure comprises a gate, a gate insulating layer, a floating gate, a floating gate insulating layer, an active layer, a source and a drain, and the gate, the gate insulating layer, the floating gate, the floating gate insulating layer, the active layer, the source and the drain form a floating gate structure based nonvolatile flash memory structure to enable the flash memory structure to be integrated in the array substrate. Therefore, the floating gate structure based flash memory structure is integrated in the array substrate. The invention further provides a liquid crystal display panel with the array substrate, a liquid crystal display device with the liquid crystal display panel and a preparation method of the array substrate.
Description
Technical field
The present invention relates to technical field of memory, particularly a kind of array base palte and preparation method thereof, liquid crystal panel, liquid crystal indicator.
Background technology
Flash memory is a kind of long-life nonvolatile memory, and it is not that block size is generally 256KB to 20MB in units of single byte but in units of fixing block that data are deleted.Flash memory is the mutation of Electrical Erasable ROM (read-only memory) (EEPROM), faster than the renewal speed of Electrical Erasable ROM (read-only memory).Still can preserve data due to during its power-off, flash memory is usually used to the configuration information of preserving various electronic display unit, in preservation data etc. in the basic input/output routine of computer, personal digital assistant, digital camera.
Along with the development of lcd technology, the Suresh Kumar display demand of liquid crystal panel is got more and more, in the procedure for displaying of liquid crystal panel, the set information of liquid crystal panel is got more and more, in prior art, the set information of liquid crystal panel is stored in independent flash chip.
Therefore, how above-mentioned flash memory structure to be integrated in liquid crystal panel the problem becoming those skilled in the art and need to study.
Summary of the invention
The invention provides a kind of array base palte, form a flash memory structure in each pixel cell of this array base palte, flash memory structure can be integrated in array base palte.
In addition, present invention also offers a kind of there is above-mentioned array base palte liquid crystal panel and a kind of there is the liquid crystal indicator of above-mentioned liquid crystal panel and the preparation method of above-mentioned array base palte.
For achieving the above object, the invention provides following technical scheme:
A kind of array base palte, comprise thin film transistor (TFT), also comprise flash memory structure, described flash memory structure comprises grid, gate insulation layer, active layer, source-drain electrode, floating boom and floating boom insulation course.
Preferably, described floating boom and described grid and the just right position of described source-drain electrode have pectination.
Preferably, described floating boom extends into described grid and described source-drain electrode just to outside region.
Preferably, described grid is positioned at and described source-drain electrode just has platy structure to extra-regional position.
Preferably, described floating boom is prepared from by metal material.
Preferably, described floating boom is prepared from by transparent conductive material.
Preferably, described grid, gate insulation layer, floating boom, floating boom insulation course, active layer and source-drain electrode are positioned on described substrate successively.
Preferably, described source-drain electrode, active layer, floating boom insulation course, floating boom, gate insulation layer, grid are positioned on described substrate successively.
Present invention also offers a kind of liquid crystal panel, comprise any one array base palte mentioned in technique scheme.
Present invention also offers a kind of liquid crystal indicator, comprise the liquid crystal panel mentioned in technique scheme.
Present invention also offers a kind of preparation method of bottom gate type array base palte, comprising:
Substrate forms gate metal layer, and passes through the figure of a patterning processes formation thin-film transistor gate and flash memory structure grid;
Gate metal layer forms gate insulation layer;
Gate insulation layer is formed floating-gate metal layer, and passes through the figure of a patterning processes formation flash memory structure floating boom;
Floating-gate metal layer is formed floating boom insulation course;
Floating boom insulation course is formed with active layer, and passes through the figure of a patterning processes formation thin film transistor active layer and flash memory structure active layer;
Active layer is formed source-drain electrode metal level, and passes through the figure of a patterning processes formation thin film transistor (TFT) source-drain electrode and flash memory structure source-drain electrode.
Present invention also offers a kind of preparation method of top gate type array base palte, comprising:
Substrate is formed source-drain electrode metal level, and passes through the figure of a patterning processes formation thin film transistor (TFT) source-drain electrode and flash memory structure source-drain electrode;
Source-drain electrode metal level is formed with active layer, and passes through the figure of a patterning processes formation thin film transistor active layer and flash memory structure active layer;
Active layer by layer on form floating boom insulation course;
Floating boom insulation course is formed floating-gate metal layer, and passes through the figure of a patterning processes formation flash memory structure floating boom;
Floating-gate metal layer forms gate insulation layer;
Gate insulation layer forms gate metal layer, and passes through the figure of a patterning processes formation thin-film transistor gate and flash memory structure grid.
The array base palte with flash memory structure provided by the invention, comprises thin film transistor (TFT), also comprises flash memory structure, and described flash memory structure comprises grid, gate insulation layer, active layer, source-drain electrode, floating boom and floating boom insulation course.
Grid in above-mentioned array base palte, gate insulation layer, floating boom, floating boom insulation course, active layer and source-drain electrode, define a kind of non-volatile flash memory structure based on floating gate structure, thus be integrated in array base palte by flash memory structure.
So, be integrated with the flash memory structure based on floating gate structure in array base palte provided by the invention.
In further technical scheme, liquid crystal panel provided by the invention, comprises any one array base palte provided in technique scheme.Owing to there is integrated flash memory structure in above-mentioned array base palte, therefore, in this liquid crystal panel, also there is integrated flash memory structure.
In further technical scheme, the invention provides a kind of liquid crystal indicator, comprise the liquid crystal panel in technique scheme, in this liquid crystal indicator, there is integrated flash memory structure.
In addition, present invention also offers a kind of preparation method of bottom gate type array base palte, comprising:
Substrate forms gate metal layer, and passes through the figure of a patterning processes formation thin-film transistor gate and flash memory structure grid;
Gate metal layer forms gate insulation layer;
Gate insulation layer is formed floating-gate metal layer, and passes through the figure of a patterning processes formation flash memory structure floating boom;
Floating-gate metal layer is formed floating boom insulation course;
Floating boom insulation course is formed with active layer, and passes through the figure of a patterning processes formation thin film transistor active layer and flash memory structure active layer;
Active layer is formed source-drain electrode metal level, and passes through the figure of a patterning processes formation thin film transistor (TFT) source-drain electrode and flash memory structure source-drain electrode.
In the preparation method of the bottom gate type array base palte that the technical program provides, the preparation technology of flash memory structure can be combined with the preparation technology of thin film transistor (TFT), is convenient to the integrated of flash memory structure.
Meanwhile, present invention also offers a kind of preparation method of top gate type array base palte, comprising:
Substrate is formed source-drain electrode metal level, and passes through the figure of a patterning processes formation thin film transistor (TFT) source-drain electrode and flash memory structure source-drain electrode;
Source-drain electrode metal level is formed with active layer, and passes through the figure of a patterning processes formation thin film transistor active layer and flash memory structure active layer;
Active layer by layer on form floating boom insulation course;
Floating boom insulation course is formed floating-gate metal layer, and passes through the figure of a patterning processes formation flash memory structure floating boom;
Floating-gate metal layer forms gate insulation layer;
Gate insulation layer forms gate metal layer, and passes through the figure of a patterning processes formation thin-film transistor gate and flash memory structure grid.
In the preparation method of the top gate type array base palte that the technical program provides, the preparation technology of flash memory structure can be combined with the preparation technology of thin film transistor (TFT), is convenient to the integrated of flash memory structure.
Accompanying drawing explanation
Fig. 1 is the structural representation of array base palte provided by the invention;
Fig. 2 is for the A of array base palte shown in Fig. 1 is to schematic diagram;
Fig. 3 is preparation method's process flow diagram of bottom gate type array base palte provided by the invention;
Fig. 4 is preparation method's process flow diagram of top gate type array base palte provided by the invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
Embodiment one
As shown in Figure 1, the array base palte of what the present embodiment provided have flash memory structure, comprise thin film transistor (TFT), also comprise flash memory structure, described flash memory structure comprises grid 01, gate insulation layer 02, floating boom 03, floating boom insulation course 04, active layer 05 and source-drain electrode 06.
As shown in Figure 1, grid 01 in above-mentioned array base palte, gate insulation layer 02, floating boom 03, floating boom insulation course 04, active layer 05 and source-drain electrode 06 are adjacent successively, as shown in Figure 2, raceway groove between source electrode 062 and drain electrode 061 defines the channel region of flash memory structure, when grid 01 and source electrode 062 and drain electrode 061 apply operating voltage, above-mentioned flash memory structure just can realize the function of storing digital information.
Above-mentioned grid 01, gate insulation layer 02, floating boom 03, floating boom insulation course 04, active layer 05 and source-drain electrode 06 define a kind of non-volatile flash memory structure based on floating gate structure, thus are integrated in array base palte by flash memory structure.
So, be integrated with the flash memory structure based on floating gate structure in array base palte provided by the invention.
Preferably, in order to not affect the aperture opening ratio of viewing area in liquid crystal panel, preferably, the flash memory structure in above-mentioned array base palte is positioned at the array base palte position relative with the non-display area of liquid crystal panel.
Preferably, as shown in Figure 2, the above-mentioned floating boom 03 mentioned in technique scheme and above-mentioned grid 01 and the just right position of source-drain electrode 06 have pectination.Comb in pectination is uniformly distributed, and grid 01 can provide level signal by the gap between two of an arbitrary neighborhood comb to active layer 05, and the comb of pectination is uniformly distributed, and improves the homogeneity that grid 01 pair of active layer 05 controls; And electric charge is when injecting floating boom 03, and the comb side of pectination also can iunjected charge, and therefore, pectination changes the charge injection point of floating boom 03, improves the efficiency of charge injection floating boom 03.
As shown in Figure 2, further, on the basis of technique scheme, in order to improve the memory space of floating boom 03 storage inside electric charge, improve the hold facility of floating boom 03 electric charge, preferably, above-mentioned floating boom 03 extends into grid 01 with source-drain electrode 06 just to outside region simultaneously.
More preferably, as shown in Figure 2, above-mentioned floating boom 03 is positioned at grid 01 and just has platy structure to extra-regional position with source-drain electrode 06.
The preparing material and can have multiple choices of above-mentioned floating boom 03:
Mode one, above-mentioned floating boom 03 can be prepared from by metal material.As, can be the metal materials such as nickel, silver, copper.
Mode two, above-mentioned floating boom 03 can also be prepared from by transparent conductive material.As tin indium oxide.
Further, in above-mentioned array base palte, grid 01, gate insulation layer 02, floating boom 03, floating boom insulation course 04, active layer 05 and source-drain electrode 06 are positioned at substrate successively.That is, above-mentioned array base palte has bottom-gate type configuration.
Certainly, above-mentioned array base palte can also be top-gate type structure, and above-mentioned source-drain electrode 06, active layer 05, floating boom insulation course 04, floating boom 03, gate insulation layer 02 and grid 01 are positioned at substrate successively.
Embodiment two
Present embodiments provide a kind of liquid crystal panel, any one array base palte provided in embodiment one and preferred implementation thereof is provided.Owing to there is integrated flash memory structure in above-mentioned array base palte, therefore, in this liquid crystal panel, also there is integrated flash memory structure.
Embodiment three
Present embodiments provide a kind of liquid crystal indicator comprising the liquid crystal panel that embodiment two provides, in this liquid crystal indicator, there is integrated flash memory structure.
Embodiment four
As shown in Figure 3, present embodiments provide a kind of preparation method of bottom gate type array base palte, comprising:
Step S301: form gate metal layer on substrate, and the figure passing through a patterning processes formation thin-film transistor gate and flash memory structure grid 01;
Step S302: form gate insulation layer 02 in gate metal layer;
Step S303: form floating-gate metal layer on gate insulation layer, and the figure passing through a patterning processes formation flash memory structure floating boom 03;
Step S304: form floating boom insulation course 04 on floating-gate metal layer;
Step S305: be formed with active layer on floating boom insulation course 04, and the figure passing through a patterning processes formation thin film transistor active layer and flash memory structure active layer 05;
Step S306: form source-drain electrode metal level on active layer, and the figure passing through a patterning processes formation thin film transistor (TFT) source-drain electrode and flash memory structure source-drain electrode 06.
In the preparation method of the bottom gate type array base palte that the technical program provides, the preparation technology of flash memory structure can be combined with the preparation technology of thin film transistor (TFT), as:
In step S301, the grid 01 of flash memory structure is synchronous with the grid of thin film transistor (TFT) and prepare with layer;
In step S302, gate insulation layer 02 covers the grid 01 of flash memory structure and the grid of thin film transistor (TFT) simultaneously;
In step S305, the active layer 05 of flash memory structure and the active layer of thin film transistor (TFT) are synchronous and prepare with layer;
In step S306, the source-drain electrode 06 of flash memory structure and the source-drain electrode of thin film transistor (TFT) are synchronous and prepare with layer.
Therefore, the preparation method of above-mentioned bottom gate type array base palte is convenient to the integrated of flash memory structure.
Embodiment five
With above-described embodiment four in like manner, as shown in Figure 4, present embodiments provide a kind of preparation method of top gate type array base palte, comprising:
Step S401: form source-drain electrode metal level on substrate, and the figure passing through a patterning processes formation thin film transistor (TFT) source-drain electrode and flash memory structure source-drain electrode;
Step S402: be formed with active layer on source-drain electrode metal level, and the figure passing through a patterning processes formation thin film transistor active layer and flash memory structure active layer;
Step S403: active layer by layer on form floating boom insulation course;
Step S404: form floating-gate metal layer on floating boom insulation course, and the figure passing through a patterning processes formation flash memory structure floating boom;
Step S405: form gate insulation layer on floating-gate metal layer;
Step S406: form gate metal layer on gate insulation layer, and the figure passing through a patterning processes formation thin-film transistor gate and flash memory structure grid.
In the preparation method of the top gate type array base palte that the technical program provides, the preparation technology of flash memory structure can be combined with the preparation technology of thin film transistor (TFT), is convenient to the integrated of flash memory structure.
Obviously, those skilled in the art can carry out various change and modification to the embodiment of the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (11)
1. an array base palte, comprises thin film transistor (TFT), it is characterized in that, also comprises flash memory structure, and described flash memory structure comprises grid, gate insulation layer, active layer, source-drain electrode, floating boom and floating boom insulation course; Described floating boom and described grid and the just right position of described source-drain electrode have pectination.
2. array base palte according to claim 1, is characterized in that, described floating boom extends into described grid and described source-drain electrode just to outside region.
3. array base palte according to claim 2, is characterized in that, is positioned at described grid and described source-drain electrode just has platy structure to extra-regional position.
4. the array base palte according to any one of claims 1 to 3, is characterized in that, described floating boom is prepared from by metal material.
5. the array base palte according to any one of claims 1 to 3, is characterized in that, described floating boom is prepared from by transparent conductive material.
6. the array base palte according to any one of claims 1 to 3, is characterized in that, described grid, gate insulation layer, floating boom, floating boom insulation course, active layer and source-drain electrode are positioned on substrate successively.
7. the array base palte according to any one of claims 1 to 3, is characterized in that, described source-drain electrode, active layer, floating boom insulation course, floating boom, gate insulation layer, grid are positioned on substrate successively.
8. a liquid crystal panel, is characterized in that, comprises the array base palte as described in any one of claim 1 ~ 7.
9. a liquid crystal indicator, is characterized in that, comprises liquid crystal panel as claimed in claim 8.
10. a preparation method for bottom gate type array base palte, is characterized in that, comprising:
Substrate forms gate metal layer, and passes through the figure of a patterning processes formation thin-film transistor gate and flash memory structure grid;
Gate metal layer forms gate insulation layer;
Gate insulation layer is formed floating-gate metal layer, and passes through the figure of a patterning processes formation flash memory structure floating boom;
Floating-gate metal layer is formed floating boom insulation course;
Floating boom insulation course is formed with active layer, and passes through the figure of a patterning processes formation thin film transistor active layer and flash memory structure active layer;
Active layer is formed source-drain electrode metal level, and passes through the figure of a patterning processes formation thin film transistor (TFT) source-drain electrode and flash memory structure source-drain electrode.
The preparation method of 11. 1 kinds of top gate type array base paltes, is characterized in that, comprising:
Substrate is formed source-drain electrode metal level, and passes through the figure of a patterning processes formation thin film transistor (TFT) source-drain electrode and flash memory structure source-drain electrode;
Source-drain electrode metal level is formed with active layer, and passes through the figure of a patterning processes formation thin film transistor active layer and flash memory structure active layer;
Active layer by layer on form floating boom insulation course;
Floating boom insulation course is formed floating-gate metal layer, and passes through the figure of a patterning processes formation flash memory structure floating boom;
Floating-gate metal layer forms gate insulation layer;
Gate insulation layer forms gate metal layer, and passes through the figure of a patterning processes formation thin-film transistor gate and flash memory structure grid.
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| CN102879963B true CN102879963B (en) | 2015-02-04 |
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| KR20150044324A (en) * | 2013-10-16 | 2015-04-24 | 삼성디스플레이 주식회사 | Thin film transistor array substrate and method thereof |
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| CN1696772A (en) * | 2005-06-15 | 2005-11-16 | 友达光电股份有限公司 | Basal plate of active element array |
| JP2006165123A (en) * | 2004-12-03 | 2006-06-22 | Canon Inc | Organic transistor device |
| CN101179108A (en) * | 2007-12-12 | 2008-05-14 | 中国科学院长春应用化学研究所 | Non-volatile organic thin-film transistor memory based on floating gate structure and manufacturing method therefor |
| CN101728395A (en) * | 2008-10-10 | 2010-06-09 | 华映视讯（吴江）有限公司 | Array substrate of thin film transistor and liquid crystal display panel |
| CN102282651A (en) * | 2009-01-29 | 2011-12-14 | 国际商业机器公司 | Memory transistor with a non-planar floating gate and manufacturing method thereof |
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| JP2006165123A (en) * | 2004-12-03 | 2006-06-22 | Canon Inc | Organic transistor device |
| CN1696772A (en) * | 2005-06-15 | 2005-11-16 | 友达光电股份有限公司 | Basal plate of active element array |
| CN101179108A (en) * | 2007-12-12 | 2008-05-14 | 中国科学院长春应用化学研究所 | Non-volatile organic thin-film transistor memory based on floating gate structure and manufacturing method therefor |
| CN101728395A (en) * | 2008-10-10 | 2010-06-09 | 华映视讯（吴江）有限公司 | Array substrate of thin film transistor and liquid crystal display panel |
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