CN102879963A - Array substrate and preparation method thereof, liquid crystal display panel and liquid crystal display device - Google Patents
Array substrate and preparation method thereof, liquid crystal display panel and liquid crystal display device Download PDFInfo
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- CN102879963A CN102879963A CN2012103743670A CN201210374367A CN102879963A CN 102879963 A CN102879963 A CN 102879963A CN 2012103743670 A CN2012103743670 A CN 2012103743670A CN 201210374367 A CN201210374367 A CN 201210374367A CN 102879963 A CN102879963 A CN 102879963A
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- floating boom
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Abstract
The invention relates to the technical field of storage and discloses an array substrate which comprises a thin-film transistor and a flash memory structure. The flash memory structure comprises a gate, a gate insulating layer, a floating gate, a floating gate insulating layer, an active layer, a source and a drain, and the gate, the gate insulating layer, the floating gate, the floating gate insulating layer, the active layer, the source and the drain form a floating gate structure based nonvolatile flash memory structure to enable the flash memory structure to be integrated in the array substrate. Therefore, the floating gate structure based flash memory structure is integrated in the array substrate. The invention further provides a liquid crystal display panel with the array substrate, a liquid crystal display device with the liquid crystal display panel and a preparation method of the array substrate.
Description
Technical field
The present invention relates to technical field of memory, particularly a kind of array base palte and preparation method thereof, liquid crystal panel, liquid crystal indicator.
Background technology
Flash memory is a kind of long-life nonvolatile memory, and the data deletion is not take single byte as unit but take fixing block as unit, the block size is generally 256KB to 20MB.Flash memory is the mutation of electronics erasable read-only memory (EEPROM), and is faster than the renewal speed of electronics erasable read-only memory.Because its when outage still can save data, flash memory is usually used to preserve the configuration information of various electronic display units, such as aspects such as preservation data in the basic input/output routine of computer, personal digital assistant, digital camera.
Development along with lcd technology, Suresh Kumar demonstration demand to liquid crystal panel is more and more, and is in the procedure for displaying of liquid crystal panel, more and more to the set information of liquid crystal panel, in the prior art, the set information of liquid crystal panel is stored in the independent flash chip.
Therefore, how above-mentioned flash memory structure is integrated in and becomes the problem that those skilled in the art need to study in the liquid crystal panel.
Summary of the invention
The invention provides a kind of array base palte, form a flash memory structure in each pixel cell of this array base palte, flash memory structure can be integrated in the array base palte.
In addition, the present invention also provides a kind of liquid crystal panel and a kind of preparation method with liquid crystal indicator and above-mentioned array base palte of above-mentioned liquid crystal panel with above-mentioned array base palte.
For achieving the above object, the invention provides following technical scheme:
A kind of array base palte comprises thin film transistor (TFT), also comprises flash memory structure, and described flash memory structure comprises grid, gate insulation layer, active layer, source-drain electrode, floating boom and floating boom insulation course.
Preferably, described floating boom and described grid and described source-drain electrode over against the position have pectination.
Preferably, described floating boom extends into described grid and described source-drain electrode outside the zone.
Preferably, be positioned at described grid and described source-drain electrode has platy structure over against extra-regional position.
Preferably, described floating boom is prepared from by metal material.
Preferably, described floating boom is prepared from by transparent conductive material.
Preferably, described grid, gate insulation layer, floating boom, floating boom insulation course, active layer and source-drain electrode are positioned on the described substrate successively.
Preferably, described source-drain electrode, active layer, floating boom insulation course, floating boom, gate insulation layer, grid are positioned on the described substrate successively.
The present invention also provides a kind of liquid crystal panel, comprises any array base palte of mentioning in the technique scheme.
The present invention also provides a kind of liquid crystal indicator, comprises the liquid crystal panel of mentioning in the technique scheme.
The present invention also provides a kind of preparation method of bottom gate type array base palte, comprising:
Form gate metal layer at substrate, and form the figure of film crystal tube grid and flash memory structure grid by composition technique;
Form gate insulation layer in gate metal layer;
Form the floating boom metal level at gate insulation layer, and pass through the figure of a composition technique formation flash memory structure floating boom;
Form the floating boom insulation course at the floating boom metal level;
Form active layer at the floating boom insulation course, and form the figure of thin film transistor active layer and flash memory structure active layer by composition technique;
Form the source-drain electrode metal level at active layer, and form the figure of thin film transistor (TFT) source-drain electrode and flash memory structure source-drain electrode by composition technique.
The present invention also provides a kind of preparation method of top gate type array base palte, comprising:
Form the source-drain electrode metal level at substrate, and form the figure of thin film transistor (TFT) source-drain electrode and flash memory structure source-drain electrode by composition technique;
Form active layer at the source-drain electrode metal level, and form the figure of thin film transistor active layer and flash memory structure active layer by composition technique;
At the active floating boom insulation course that forms layer by layer;
Form the floating boom metal level at the floating boom insulation course, and pass through the figure of a composition technique formation flash memory structure floating boom;
Form gate insulation layer at the floating boom metal level;
Form gate metal layer at gate insulation layer, and form the figure of film crystal tube grid and flash memory structure grid by composition technique.
Array base palte with flash memory structure provided by the invention comprises thin film transistor (TFT), also comprises flash memory structure, and described flash memory structure comprises grid, gate insulation layer, active layer, source-drain electrode, floating boom and floating boom insulation course.
Grid in the above-mentioned array base palte, gate insulation layer, floating boom, floating boom insulation course, active layer and source-drain electrode have formed a kind of non-volatile flash memory structure based on floating gate structure, thereby flash memory structure have been integrated in the array base palte.
So, integrated flash memory structure based on floating gate structure in the array base palte provided by the invention.
In further technical scheme, any array base palte that provides in the technique scheme is provided liquid crystal panel provided by the invention.Owing to have integrated flash memory structure in the above-mentioned array base palte, therefore, also have integrated flash memory structure in this liquid crystal panel.
In further technical scheme, the invention provides a kind of liquid crystal indicator, comprise the liquid crystal panel in the technique scheme, have integrated flash memory structure in this liquid crystal indicator.
In addition, the present invention also provides a kind of preparation method of bottom gate type array base palte, comprising:
Form gate metal layer at substrate, and form the figure of film crystal tube grid and flash memory structure grid by composition technique;
Form gate insulation layer in gate metal layer;
Form the floating boom metal level at gate insulation layer, and pass through the figure of a composition technique formation flash memory structure floating boom;
Form the floating boom insulation course at the floating boom metal level;
Form active layer at the floating boom insulation course, and form the figure of thin film transistor active layer and flash memory structure active layer by composition technique;
Form the source-drain electrode metal level at active layer, and form the figure of thin film transistor (TFT) source-drain electrode and flash memory structure source-drain electrode by composition technique.
Among the preparation method of the bottom gate type array base palte that the technical program provides, the preparation technology of flash memory structure can be combined with the preparation technology of thin film transistor (TFT), is convenient to the integrated of flash memory structure.
Simultaneously, the present invention also provides a kind of preparation method of top gate type array base palte, comprising:
Form the source-drain electrode metal level at substrate, and form the figure of thin film transistor (TFT) source-drain electrode and flash memory structure source-drain electrode by composition technique;
Form active layer at the source-drain electrode metal level, and form the figure of thin film transistor active layer and flash memory structure active layer by composition technique;
At the active floating boom insulation course that forms layer by layer;
Form the floating boom metal level at the floating boom insulation course, and pass through the figure of a composition technique formation flash memory structure floating boom;
Form gate insulation layer at the floating boom metal level;
Form gate metal layer at gate insulation layer, and form the figure of film crystal tube grid and flash memory structure grid by composition technique.
Among the preparation method of the top gate type array base palte that the technical program provides, the preparation technology of flash memory structure can be combined with the preparation technology of thin film transistor (TFT), is convenient to the integrated of flash memory structure.
Description of drawings
Fig. 1 is the structural representation of array base palte provided by the invention;
Fig. 2 is that the A of array base palte shown in Figure 1 is to synoptic diagram;
Fig. 3 is preparation method's process flow diagram of bottom gate type array base palte provided by the invention;
Fig. 4 is preparation method's process flow diagram of top gate type array base palte provided by the invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
Embodiment one
As shown in Figure 1, the array base palte with flash memory structure that present embodiment provides comprises thin film transistor (TFT), also comprises flash memory structure, and described flash memory structure comprises grid 01, gate insulation layer 02, floating boom 03, floating boom insulation course 04, active layer 05 and source-drain electrode 06.
As shown in Figure 1, grid 01 in the above-mentioned array base palte, gate insulation layer 02, floating boom 03, floating boom insulation course 04, active layer 05 and source-drain electrode 06 are adjacent successively, as shown in Figure 2, source electrode 062 and the raceway groove between 061 of draining have formed the channel region of flash memory structure, when grid 01 and source electrode 062 and drain 061 when applying operating voltage, above-mentioned flash memory structure just can be realized the function of storing digital information.
Above-mentioned grid 01, gate insulation layer 02, floating boom 03, floating boom insulation course 04, active layer 05 and source-drain electrode 06 have formed a kind of non-volatile flash memory structure based on floating gate structure, thereby flash memory structure is integrated in the array base palte.
So, integrated flash memory structure based on floating gate structure in the array base palte provided by the invention.
Preferably, in order not affect the aperture opening ratio of viewing area in the liquid crystal panel, preferably, the flash memory structure in the above-mentioned array base palte is positioned at the array base palte position relative with the non-display area of liquid crystal panel.
Preferably, as shown in Figure 2, the above-mentioned floating boom mentioned in the technique scheme 03 and above-mentioned grid 01 and source-drain electrode 06 over against the position have pectination.Broach in the pectination evenly distributes, and grid 01 can provide level signal to active layer 05 by the gap between two broach of arbitrary neighborhood, and the broach of pectination evenly distributes, and has improved the homogeneity of 01 pair of active layer of grid, 05 control; And electric charge is when injecting floating boom 03, and the broach side of pectination also can iunjected charge, and therefore, pectination has changed the charge injection point of floating boom 03, improves the efficient of charge injection floating boom 03.
As shown in Figure 2, further, on the basis of technique scheme, in order to improve the memory space of floating boom 03 storage inside electric charge, improve simultaneously the hold facility of floating boom 03 electric charge, preferably, above-mentioned floating boom 03 extends into grid 01 and source-drain electrode 06 outside the zone.
More preferably, as shown in Figure 2, above-mentioned floating boom 03 is positioned at grid 01 and has platy structure with source-drain electrode 06 over against extra-regional position.
The preparation material of above-mentioned floating boom 03 can have multiple choices:
Mode one, above-mentioned floating boom 03 can be prepared from by metal material.As, can be the metal materials such as nickel, silver, copper.
Mode two, above-mentioned floating boom 03 can also be prepared from by transparent conductive material.Such as tin indium oxide.
Further, in the above-mentioned array base palte, grid 01, gate insulation layer 02, floating boom 03, floating boom insulation course 04, active layer 05 and source-drain electrode 06 are positioned on the substrate successively.That is, above-mentioned array base palte has the bottom gate type structure.
Certainly, above-mentioned array base palte can also be the top gate type structure, and above-mentioned source-drain electrode 06, active layer 05, floating boom insulation course 04, floating boom 03, gate insulation layer 02 and grid 01 are positioned on the substrate successively.
Embodiment two
Present embodiment provides a kind of liquid crystal panel, and any array base palte that provides in embodiment one and the preferred implementation thereof is provided.Owing to have integrated flash memory structure in the above-mentioned array base palte, therefore, also have integrated flash memory structure in this liquid crystal panel.
Embodiment three
Present embodiment provides the liquid crystal indicator of the liquid crystal panel that a kind of embodiment of comprising two provides, and has integrated flash memory structure in this liquid crystal indicator.
Embodiment four
As shown in Figure 3, present embodiment provides a kind of preparation method of bottom gate type array base palte, comprising:
Step S301: form gate metal layer at substrate, and form the figure of film crystal tube grid and flash memory structure grid 01 by composition technique;
Step S302: form gate insulation layer 02 in gate metal layer;
Step S303: form the floating boom metal level at gate insulation layer, and pass through the figure of a composition technique formation flash memory structure floating boom 03;
Step S304: form floating boom insulation course 04 at the floating boom metal level;
Step S305: form active layer at floating boom insulation course 04, and form the figure of thin film transistor active layer and flash memory structure active layer 05 by composition technique;
Step S306: form the source-drain electrode metal level at active layer, and form the figure of thin film transistor (TFT) source-drain electrode and flash memory structure source-drain electrode 06 by composition technique.
Among the preparation method of the bottom gate type array base palte that the technical program provides, the preparation technology of flash memory structure can be combined with the preparation technology of thin film transistor (TFT), as:
Among the step S301, the grid 01 of flash memory structure prepares synchronously and with layer with the grid of thin film transistor (TFT);
Among the step S302, gate insulation layer 02 covers the grid 01 of flash memory structure and the grid of thin film transistor (TFT) simultaneously;
Among the step S305, the active layer 05 of flash memory structure and the active layer of thin film transistor (TFT) prepare synchronously and with layer;
Among the step S306, the source-drain electrode 06 of flash memory structure and the source-drain electrode of thin film transistor (TFT) prepare synchronously and with layer.
Therefore, the preparation method of above-mentioned bottom gate type array base palte is convenient to the integrated of flash memory structure.
Embodiment five
With above-described embodiment four in like manner, as shown in Figure 4, present embodiment provides a kind of preparation method of top gate type array base palte, comprising:
Step S401: form the source-drain electrode metal level at substrate, and form the figure of thin film transistor (TFT) source-drain electrode and flash memory structure source-drain electrode by composition technique;
Step S402: form active layer at the source-drain electrode metal level, and form the figure of thin film transistor active layer and flash memory structure active layer by composition technique;
Step S403: at the active floating boom insulation course that forms layer by layer;
Step S404: form the floating boom metal level at the floating boom insulation course, and pass through the figure of a composition technique formation flash memory structure floating boom;
Step S405: form gate insulation layer at the floating boom metal level;
Step S406: form gate metal layer at gate insulation layer, and form the figure of film crystal tube grid and flash memory structure grid by composition technique.
Among the preparation method of the top gate type array base palte that the technical program provides, the preparation technology of flash memory structure can be combined with the preparation technology of thin film transistor (TFT), is convenient to the integrated of flash memory structure.
Obviously, those skilled in the art can carry out various changes and modification to the embodiment of the invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (12)
1. an array base palte comprises thin film transistor (TFT), it is characterized in that, also comprises flash memory structure, and described flash memory structure comprises grid, gate insulation layer, active layer, source-drain electrode, floating boom and floating boom insulation course.
2. array base palte according to claim 1 is characterized in that, described floating boom and described grid and described source-drain electrode over against the position have pectination.
3. array base palte according to claim 2 is characterized in that, described floating boom extends into described grid and described source-drain electrode outside the zone.
4. array base palte according to claim 3 is characterized in that, is positioned at described grid and described source-drain electrode has platy structure over against extra-regional position.
5. each described array base palte is characterized in that according to claim 1 ~ 4, and described floating boom is prepared from by metal material.
6. each described array base palte is characterized in that according to claim 1 ~ 4, and described floating boom is prepared from by transparent conductive material.
7. each described array base palte is characterized in that according to claim 1 ~ 4, and described grid, gate insulation layer, floating boom, floating boom insulation course, active layer and source-drain electrode are positioned on the described substrate successively.
8. each described array base palte is characterized in that according to claim 1 ~ 4, and described source-drain electrode, active layer, floating boom insulation course, floating boom, gate insulation layer, grid are positioned on the described substrate successively.
9. a liquid crystal panel is characterized in that, comprises such as each described array base palte of claim 1 ~ 8.
10. a liquid crystal indicator is characterized in that, comprises liquid crystal panel as claimed in claim 9.
11. the preparation method of a bottom gate type array base palte is characterized in that, comprising:
Form gate metal layer at substrate, and form the figure of film crystal tube grid and flash memory structure grid by composition technique;
Form gate insulation layer in gate metal layer;
Form the floating boom metal level at gate insulation layer, and pass through the figure of a composition technique formation flash memory structure floating boom;
Form the floating boom insulation course at the floating boom metal level;
Form active layer at the floating boom insulation course, and form the figure of thin film transistor active layer and flash memory structure active layer by composition technique;
Form the source-drain electrode metal level at active layer, and form the figure of thin film transistor (TFT) source-drain electrode and flash memory structure source-drain electrode by composition technique.
12. the preparation method of a top gate type array base palte is characterized in that, comprising:
Form the source-drain electrode metal level at substrate, and form the figure of thin film transistor (TFT) source-drain electrode and flash memory structure source-drain electrode by composition technique;
Form active layer at the source-drain electrode metal level, and form the figure of thin film transistor active layer and flash memory structure active layer by composition technique;
At the active floating boom insulation course that forms layer by layer;
Form the floating boom metal level at the floating boom insulation course, and pass through the figure of a composition technique formation flash memory structure floating boom;
Form gate insulation layer at the floating boom metal level;
Form gate metal layer at gate insulation layer, and form the figure of film crystal tube grid and flash memory structure grid by composition technique.
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| CN104576653A (en) * | 2013-10-16 | 2015-04-29 | 三星显示有限公司 | Thin film transistor array substrate and manufacturing method thereof |
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