CN107305897B - A kind of ferroelectric type InGaZnO nonvolatile memory of double-gate structure - Google Patents
A kind of ferroelectric type InGaZnO nonvolatile memory of double-gate structure Download PDFInfo
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- CN107305897B CN107305897B CN201610236723.0A CN201610236723A CN107305897B CN 107305897 B CN107305897 B CN 107305897B CN 201610236723 A CN201610236723 A CN 201610236723A CN 107305897 B CN107305897 B CN 107305897B
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- 230000015654 memory Effects 0.000 title claims abstract description 40
- 239000000758 substrate Substances 0.000 claims description 8
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims 2
- 229910052742 iron Inorganic materials 0.000 claims 1
- 238000000926 separation method Methods 0.000 abstract description 3
- 239000000463 material Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000002708 enhancing effect Effects 0.000 description 2
- 230000005621 ferroelectricity Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/78391—Field effect transistors with field effect produced by an insulated gate the gate comprising a layer which is used for its ferroelectric properties
Abstract
The invention discloses a kind of ferroelectric type InGaZnO nonvolatile memories of double-gate structure, from top to bottom are as follows: top-gated/ferroelectric layer/channel layer/bottom gate oxide layer/bottom gate.The separation that the nonvolatile memory is operated by carrying out " program/erase " and " reading " in structure, improves the memory window and unfailing performance of memory.
Description
Technical field
The present invention relates to semiconductor non-volatile memory field more particularly to a kind of ferroelectric types with double-gate structure
InGaZnO nonvolatile memory.
Background technique
FPD is used widely in each electronic product such as TV, computer and smart phone, is greatly changed
It has been apt to people's lives.As people have low-power consumption and high-resolution portable electronic device, large scale 3D display etc.
The product demand of higher quality increases sharply, and researcher proposes " panel system (System on Panel, SoP) " technology,
The module of different function (such as pixel circuit, peripheral drive circuit and information store module) is integrated on panel.SoP skill
Art has been obviously improved the stability and operating rate of product while reducing product cost and power consumption, therefore is to develop high-quality
The Advantageous approach of FPD.Thin film transistor (TFT) (Thin Film Transistor, TFT) and nonvolatile memory
(Non-Volatile Memory, NVM)) it is two kinds of critical devices for constituting SoP, wherein and NVM plays pixel in SoP and deposits
The effect of storage, various display parameters and control signal storage.
An important branch of the ferroelectric type NVM as NVM has structure (including channel layer/ferroelectric layer/grid) and makes
The features such as simple process, fast operating rate, therefore have a extensive future.
Either TFT or NVM, device performance are all closely related with the material of channel layer.It is (such as non-with traditional Si base
Brilliant Si, polycrystalline Si etc.) channel material compares, and InGaZnO has that light transmittance is high, mobility is high, uniformity is good and preparation process is simple
The advantages that single (can be formed a film using conventional sputter technique), be ideal channel material.Therefore, make ditch using InGaZnO
Road developing material high performance TFT and NVM, for realizing that SoP is of great significance.
Initial InGaZnO TFT is single grid structure, in recent years, has developed the InGaZnO TFT of double-gate structure (from upper
Include: top-gated/top-gated oxide layer/channel layer/bottom gate oxide layer/bottom gate under and), to realize TFT threshold voltage VthAdjusting with
And enhancing grid is to the control ability of channel and the driving capability of TFT.Compared to InGaZnO TFT, the development of InGaZnO NVM
It then relatively lags behind, particularly, the performance indicators such as the memory window of memory and reliability remain to be further improved.Pass through increase
" program/erase (Program/Erase, P/E) " voltage can increase the memory window of memory；On the other hand, big " volume
Stress caused by journey/erasing " voltage can deteriorate the unfailing performance of memory and will increase the power consumption of device.In addition, for
Existing ferroelectric type NVM, " program/erase " (realizing information storage) and " reading " (realizing that information is read) operation is usually using same
Grid carries out, and therefore, in progress " reading " operation, ferroelectricity can be deteriorated by being applied to stress caused by " reading " operation voltage of grid
The performance of layer, thereby reduces the reliability of memory.
Summary of the invention
Goal of the invention: for overcome the deficiencies in the prior art, the InGaZnO ferroelectric type for providing a kind of double-gate structure is non-volatile
Property memory, can effectively improve the memory window and unfailing performance of memory.
Technical solution: to achieve the above object, the technical solution adopted by the present invention is that:
A kind of ferroelectric type InGaZnO nonvolatile memory of double-gate structure including substrate, sets bottom gate on substrate,
If on substrate and covering the bottom gate oxide layer of bottom gate, the InGaZnO channel layer being located in bottom gate oxide layer is located at
The source electrode of opposite sides, drain electrode, are located at the ferroelectricity on InGaZnO channel layer and on source electrode, drain electrode on InGaZnO channel layer
Layer, is arranged in the top-gated on ferroelectric layer, the top-gated is located at the surface of bottom gate；The equivalent oxide thickness of the bottom gate oxide layer
Spend TBOX, InGaZnO channel layer equivalent oxide thickness TIGZOAnd the equivalent oxide thickness T of ferroelectric layerTOXMeet: 3 >
TBOX/(TTOX+TIGZO)>1；Voltage is applied to the top-gated to realize " program/erase " operation of nonvolatile memory, to institute
It states bottom gate and applies voltage to realize " reading " operation of nonvolatile memory.
The utility model has the advantages that compared with prior art, the invention has the following advantages that
1), the ferroelectric type InGaZnO nonvolatile memory of double-gate structure proposed by the present invention, by utilizing bottom gate TFT
Carrying out " reading " operation can be achieved to amplify the memory window of top-gated memory, therefore, enhance the storage performance of device, and can solve
Certainly existing ferroelectric type memory must realize big memory window by increasing program/erase voltage and operating time and its draw
The power consumption and integrity problem risen.
2), " program/erase " and " reading " operation of existing ferroelectric type NVM is usually carried out using identical grid, in " reading "
When operation, the reliability of ferroelectric layer and device can be deteriorated by being applied to stress caused by " reading " operation voltage of grid；The present invention
In " program/erase " and " reading " operation separation, eliminate " readings " and operate to the stress effect of ferroelectric layer, therefore improve device
Unfailing performance.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram of the ferroelectric type InGaZnO nonvolatile memory of double-gate structure.
Specific embodiment
As shown in Figure 1, a kind of ferroelectric type InGaZnO nonvolatile memory of double-gate structure, including substrate 10, it is located at lining
Bottom gate 11 on bottom 10 is located on substrate 10 and covers the bottom gate oxide layer 12 of bottom gate 11, is located in bottom gate oxide layer 12
InGaZnO channel layer 13 is located at source electrode 14 and the drain electrode 15 of opposite sides on InGaZnO channel layer 13, is located at InGaZnO channel
Ferroelectric layer 16 on layer 13 and on source electrode 14, drain electrode 15, is arranged in the top-gated 17 on ferroelectric layer 16, top-gated 17 is located at bottom gate 11
Surface.The equivalent oxide thickness T of bottom gate oxide layer 12BOX, InGaZnO channel layer 13 equivalent oxide thickness TIGZO
And the equivalent oxide thickness T of ferroelectric layer 16TOXMeet: 3 > TBOX/(TTOX+TIGZO)>1。
In above structure, top-gated 17, ferroelectric layer 16, channel layer 13, source electrode 14 and drain electrode 15 constitute top-gated memory；Ditch
Channel layer 13, source electrode 14, drain electrode 15, bottom gate oxide layer 12 and bottom gate 11 constitute bottom gate TFT.Double grid ferroelectric type InGaZnO
NVM carried out in structure " program/erase " and " reading " operation separation: " program/erase " operation by top-gated memory into
Row applies voltage to top-gated 17 to realize；And " reading " operation is then carried out by bottom gate TFT, i.e., applies voltage to bottom gate 11
It realizes.Since InGaZnO has the inherent characteristics for being difficult to transoid, the double grid ferroelectric type InGaZnO nonvolatile memory is right
When top-gated memory carries out " program/erase ", the V of caused top-gated memorythAmplitude of variation Δ Vth T(i.e. memory window) and
The V of caused bottom gate TFT under this conditionthAmplitude of variation Δ Vth BApproximation meets following coupled relation:
Formula (1) shows: if selection suitable material and thickness make TBOX/(TTOX+TIGZO) > 1, Δ Vth BIt is inclined to top-gated
Δ V caused by settingth TWith enhancing and amplification effect.According to formula (1), due to TBOX/(TTOX+TIGZO) > 1, using bottom gate TFT into
Row " reading " operation can be achieved to amplify the memory window of top-gated memory.But if TBOX/(TTOX+TIGZO) > 3, then it can be the bottom of due to
Gate oxide is blocked up, and the grid of bottom gate TFT is caused to die down the control ability of channel layer, results in operating voltage and power consumption increases
Add, and/or since ferroelectric layer is excessively thin, top-gated memory is caused to be easy to happen charge leakage, causes device reliability energy
It is deteriorated.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications are also answered
It is considered as protection scope of the present invention.
Claims (1)
1. a kind of ferroelectric type InGaZnO nonvolatile memory of double-gate structure, it is characterised in that: including substrate, be located at substrate
On bottom gate, if on substrate and covering the bottom gate oxide layer of bottom gate, the InGaZnO channel layer being located in bottom gate oxide layer,
It is located at the source electrode of opposite sides on InGaZnO channel layer, drain electrode, is located at the iron on InGaZnO channel layer and on source electrode, drain electrode
Electric layer, is arranged in the top-gated on ferroelectric layer, and the top-gated is located at the surface of bottom gate；The equivalent oxide of the bottom gate oxide layer
Thickness TBOX, InGaZnO channel layer equivalent oxide thickness TIGZOAnd the equivalent oxide thickness T of ferroelectric layerTOXMeet: 3 >
TBOX/(TTOX+TIGZO)>1；Voltage is applied to the top-gated to realize " program/erase " operation of nonvolatile memory, to institute
It states bottom gate and applies voltage to realize " reading " operation of nonvolatile memory.
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| CN201610236723.0A CN107305897B (en) | 2016-04-15 | 2016-04-15 | A kind of ferroelectric type InGaZnO nonvolatile memory of double-gate structure |
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| CN107305897B true CN107305897B (en) | 2019-11-08 |
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Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107301879B (en) * | 2016-04-15 | 2020-06-02 | 东南大学 | Application of thin film transistor with adjustable threshold voltage as nonvolatile memory |
| CN108155191B (en) * | 2017-12-01 | 2020-06-30 | 东南大学 | Multi-value resistance variable nonvolatile memory and operation method thereof |
| CN108091656B (en) * | 2017-12-01 | 2020-11-20 | 东南大学 | Resistive nonvolatile memory and operation method thereof |
| CN109860304A (en) * | 2019-03-29 | 2019-06-07 | 中国科学院微电子研究所 | The preparation method and control method of a kind of ferroelectric memory, ferroelectric memory |
| CN116711084A (en) * | 2021-03-09 | 2023-09-05 | 华为技术有限公司 | Ferroelectric transistor, memory array, memory and preparation method |
| TWI792545B (en) | 2021-09-09 | 2023-02-11 | 力晶積成電子製造股份有限公司 | Oxide semiconductor-based fram |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102265392A (en) * | 2009-02-24 | 2011-11-30 | 松下电器产业株式会社 | Semiconductor memory cells and manufacturing method therefor as well as semiconductor memory devices |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102265392A (en) * | 2009-02-24 | 2011-11-30 | 松下电器产业株式会社 | Semiconductor memory cells and manufacturing method therefor as well as semiconductor memory devices |
Non-Patent Citations (1)
| Title |
|---|
| 基于In-Ga-Zn-O沟道薄膜晶体管存储器的研究;崔兴美;《中国优秀硕士学位论文全文数据库》;20160315;第1-2页 * |
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