CN107301879B - Application of thin film transistor with adjustable threshold voltage as nonvolatile memory - Google Patents
Application of thin film transistor with adjustable threshold voltage as nonvolatile memory Download PDFInfo
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- CN107301879B CN107301879B CN201610235084.6A CN201610235084A CN107301879B CN 107301879 B CN107301879 B CN 107301879B CN 201610235084 A CN201610235084 A CN 201610235084A CN 107301879 B CN107301879 B CN 107301879B
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- 230000015654 memory Effects 0.000 title claims abstract description 34
- 239000010409 thin film Substances 0.000 title claims abstract description 23
- 230000005641 tunneling Effects 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims description 9
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 8
- 230000000903 blocking effect Effects 0.000 claims description 6
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052733 gallium Inorganic materials 0.000 claims description 4
- 229910052738 indium Inorganic materials 0.000 claims description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical group [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 4
- 239000011787 zinc oxide Substances 0.000 claims description 4
- 238000000034 method Methods 0.000 claims description 2
- 230000004888 barrier function Effects 0.000 abstract description 4
- 238000000926 separation method Methods 0.000 abstract description 2
- 239000000463 material Substances 0.000 description 4
- 239000000969 carrier Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 230000001965 increasing effect Effects 0.000 description 3
- 230000003321 amplification Effects 0.000 description 2
- 238000005034 decoration Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 230000007334 memory performance Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Abstract
The invention discloses a use of a thin film transistor with adjustable threshold voltage as a nonvolatile memory, wherein a top gate, a barrier layer, a storage layer, a tunneling layer and a channel layer of the thin film transistor form a top gate type memory; the channel layer, the bottom gate oxide layer and the bottom gate of the thin film transistor constitute a bottom gate type TFT. The "program/erase" operation of the nonvolatile memory is realized by operating the top gate type memory, and the "read" operation of the nonvolatile memory is realized by operating the bottom gate type TFT. The separation of the Program/Erase (P/E) and read operations improves the performance of the memory such as the storage window, reliability and working speed.
Description
Technical Field
The invention relates to the field of semiconductor nonvolatile memories, in particular to application of a thin film transistor as a nonvolatile memory.
Background
The flat panel display is widely applied to various electronic products such as televisions, computers, smart phones and the like, and the life of people is greatly improved. As people have rapidly increased demands for portable electronic devices with low power consumption and high resolution, large-sized 3D displays, and other products with higher quality, researchers have proposed a "System on Panel (SoP)" technology, i.e., modules with different functions (such as pixel circuits, peripheral driving circuits, and information storage modules) are integrated on a Panel. The SoP technology significantly improves the stability and the operating speed of the product while reducing the cost and the power consumption of the product, and thus is a beneficial technical approach for developing high-quality flat panel displays. Thin Film Transistors (TFTs) and Non-Volatile memories (NVMs) are two key devices that constitute the SoP, where the NVM plays a role in storing pixels, various display parameters, and control signals. The charge type NVM is an important branch of the NVM, has the characteristics of simple structure (including a channel layer/a tunneling layer/a storage layer/a blocking layer/a grid electrode), high reliability and compatibility with a TFT (thin film transistor) technology, and has wide development prospect.
The device performance of either TFT or NVM is closely related to the material of the channel layer. Compared with the traditional Si-based (such as amorphous Si and polycrystalline silicon) channel material, the InGaZnO oxide has the advantages of high light transmittance, high mobility, good uniformity, simple preparation process (a film can be formed by using a conventional sputtering process) and the like, so the InGaZnO oxide is the preferred channel material for developing the SoP. In addition, the InGaZnO has the characteristic of difficult inversion (namely, no hole appears on the surface of the InGaZnO under the negative bias), so that the TFT has extremely low electric leakage and the power consumption of the TFT is reduced; on the other hand, the problems of low erasing efficiency and small memory window of the charge-type NVM also result, which becomes a bottleneck restricting the development of the NVM. In addition, for the charge-type NVM, charges trapped in the storage layer can also cause scattering of carriers on the surface of the channel layer, which reduces the mobility of the device and thus affects the operating speed of the device.
The initial InGaZnO TFT was a single gate structure, and in recent years, an InGaZnO TFT of a double gate structure was developed to realize a threshold voltage V of the TFTthAnd enhance the gate control capability of the channel and the driving capability of the TFT. The Chinese patent application: 201410442648.4 discloses a thin film transistor with adjustable threshold voltage, which, as shown in fig. 1, includes a substrate 10, a bottom gate 11 disposed on the substrate 10, a bottom gate oxide layer 12 disposed on the substrate 10 and covering the bottom gate 11, a channel layer 13 disposed on the bottom gate oxide layer 12, a source electrode 14 and a drain electrode 15 disposed on opposite sides of the channel layer 13, a tunneling layer 21 disposed on the channel layer 13 and on the source electrode 14 and the drain electrode 15, a storage layer 22 disposed on the tunneling layer 21, a blocking layer 23 disposed on the storage layer 22, and a top gate 17 disposed on the blocking layer 23, wherein the top gate 17 is located right above the bottom gate 11. The channel layer 13 is indium gallium zinc oxide InGaZnO.
Because InGaZnO has the characteristic of difficult inversion, the double-gate InGaZnO TFT carries out V by applying negative bias to one of the gate electrodes (such as a top gate)thV of top gate TFT (top gate/top gate oxide layer/channel layer) during modulationthAmplitude of variation Δ Vth TAnd V of bottom gate TFT (channel layer/bottom gate oxide layer/bottom gate) caused under the conditionthAmplitude of variation Δ Vth BThe following coupling relationships are approximately satisfied:
wherein, TBOX、TTOXAnd TIGZORespectively representing the equivalent oxide thicknesses of the bottom gate oxide layer, the top gate oxide layer and the channel layer. Formula (1) indicates that: if the appropriate gate oxide material and thickness are chosen such that T isBOX/(TTOX+TIGZO)>1，ΔVth BΔ V induced by bias to top gateth THas the enhancement and amplification effects. Compared to InGaZnO TFTs, charged InGaZnO NVM is typically a single gate structure.
Disclosure of Invention
The purpose of the invention is as follows: the invention provides an application of a thin film transistor with adjustable threshold voltage as a nonvolatile memory.
The technical scheme is as follows: the application of a thin film transistor with adjustable threshold voltage as a nonvolatile memory comprises applying voltage to the top gate of the thin film transistor with adjustable threshold voltage to realize the programming/erasing operation of the nonvolatile memory, applying voltage to the bottom gate of the thin film transistor with adjustable threshold voltage to realize the reading operation of the nonvolatile memory, and forming an equivalent oxide layer thickness T of the bottom gate oxide layerBOXEquivalent oxide thickness T of channel layerIGZOAnd equivalent oxide thickness T of top gate oxideTOXThe conditions are satisfied: 3>TBOX/(TTOX+TIGZO)>1, the channel layer is indium gallium zinc oxide.
Has the advantages that: compared with the prior art, the invention has the following advantages:
1. in the invention, a top gate, a blocking layer, a storage layer, a tunneling layer and a channel layer of the thin film transistor form a top gate type memory; the channel layer, the bottom gate oxide layer and the bottom gate of the thin film transistor constitute a bottom gate type TFT. Due to TBOX/(TTOX+TIGZO)>1, according to the formula (1), the memory window of the top gate type memory can be enlarged by using the bottom gate type TFT for the reading operation, thereby enhancing the memory performance of the device and solving the problem that the existing charge type memory has to realize a large memory window by increasing the programming/erasing voltage (especially the erasing voltage) and the operation timeAnd the power consumption and reliability problems that it causes.
2. The programming/erasing (P/E) and reading operations of the conventional NVM are performed by using the same gate, and during the reading operation, the stress generated by the reading operation voltage applied to the gate may cause the leakage of the charge in the storage layer, thereby reducing the reliability of the device; the separation of the programming/erasing and reading operations in the invention eliminates the interference of the reading operation on the charges in the storage layer, thereby improving the reliability of the device.
3. The programming/erasing operation and the reading operation of the conventional NVM are carried out through the same side surface of the channel layer, and during the reading operation, charges trapped in the storage layer generate coulomb scattering on current carriers on the surface of the channel layer, so that the mobility of the current carriers is reduced, and the working speed of a device is further reduced; in the invention, "programming/erasing" and "reading" operations are separated, and the "programming/erasing" and "reading" operations are respectively performed through the upper surface and the lower surface of the channel layer, so that the charge in the storage layer is inhibited from generating coulomb scattering on the current carrier on the lower surface of the channel layer, and the mobility of the current carrier and the working speed of the device are improved.
Drawings
Fig. 1 is a schematic structural diagram of a thin film transistor with adjustable threshold voltage.
DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION
A thin film transistor with adjustable threshold voltage is used as a nonvolatile memory and comprises a substrate 10, a bottom gate 11 arranged on the substrate 10, a bottom gate oxide layer 12 arranged on the substrate 10 and covering the bottom gate 11, a channel layer 13 arranged on the bottom gate oxide layer 12, a source electrode 14 and a drain electrode 15 arranged on two opposite sides of the channel layer 13, a tunneling layer 21 arranged on the channel layer 13 and on the source electrode 14 and the drain electrode 15, a storage layer 22 arranged on the tunneling layer 21, a barrier layer 23 arranged on the storage layer 22, and a top gate 17 arranged on the barrier layer 23, wherein the top gate 17 is positioned right above the bottom gate 11. Wherein the channel layer 13 is indium gallium zinc oxide, and the equivalent oxide thickness T of the bottom gate oxide layerBOXEquivalent oxide thickness T of channel layerIGZOAnd equivalent oxide thickness T of top gate oxideTOXThe conditions are satisfied: 3>TBOX/(TTOX+TIGZO)>1。
When the thin film transistor with the adjustable threshold voltage is used as a nonvolatile memory, the top gate 17, the barrier layer 23, the storage layer 22, the tunneling layer 21 and the channel layer 13 form a top gate type memory; the channel layer 13, the bottom gate oxide layer 12, and the bottom gate 11 constitute a bottom gate type TFT. The programming/erasing of the nonvolatile memory is realized by operating the top gate type memory, and the information storage function of the nonvolatile memory is completed; the reading of the nonvolatile memory is realized by operating the bottom gate type TFT, and the information reading function of the nonvolatile memory is completed, namely the thin film transistor with adjustable threshold voltage is realized to serve as the double-gate a-IGZO CT-NVM.
To accomplish this, the bottom gate oxide layer T is formedBOXA channel layer TIGZOAnd a top gate oxide layer TTOXHas an equivalent oxide thickness of 3>TBOX/(TTOX+TIGZO)>1。TBOX/(TTOX+TIGZO)>1, ensuring the amplification of a storage window of a top gate type memory by a bottom gate TFT during reading operation; but if TBOX/(TTOX+TIGZO) If the thickness of the bottom gate oxide layer is more than 3, the control capability of the gate of the bottom gate type TFT on the channel layer is weakened, so that the working voltage and the power consumption are increased, and/or the charge of the top gate memory is easy to leak due to the fact that the thickness of the top gate oxide layer is too thin, so that the reliability of the device is deteriorated.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (1)
1. A method for using a thin film transistor with adjustable threshold voltage as a nonvolatile memory applies voltage to the top gate of the thin film transistor with adjustable threshold voltage to realize nonvolatile memoryThe programming/erasing operation of the nonvolatile memory is realized by applying voltage to the bottom gate of the thin film transistor with adjustable threshold voltage to realize the reading operation of the nonvolatile memory, and the equivalent oxide thickness T of the bottom gate oxide layerBOXEquivalent oxide thickness T of channel layerIGZOAnd equivalent oxide thickness T of top gate oxideTOXThe conditions are satisfied: 3>TBOX/(TTOX+TIGZO)>1, the channel layer is indium gallium zinc oxide;
the thin film transistor with the adjustable threshold voltage comprises a substrate (10), a bottom gate (11) arranged on the substrate (10), a bottom gate oxide layer (12) arranged on the substrate (10) and covering the bottom gate (11), a channel layer (13) arranged on the bottom gate oxide layer (12), source electrodes (14) arranged on two opposite sides of the channel layer (13), a drain electrode (15), a tunneling layer (21) arranged on the channel layer (13) and the source electrodes (14), a storage layer (22) arranged on the tunneling layer (21), a blocking layer (23) arranged on the storage layer (22), and a top gate (17) arranged on the blocking layer (23), wherein the top gate (17) is positioned right above the bottom gate (11).
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| CN108155191B (en) * | 2017-12-01 | 2020-06-30 | 东南大学 | Multi-value resistance variable nonvolatile memory and operation method thereof |
| CN108831931B (en) * | 2018-05-07 | 2021-09-14 | 中国科学院物理研究所 | Nonvolatile memory and preparation method thereof |
| CN111403485B (en) * | 2020-03-29 | 2021-07-27 | 华中科技大学 | Novel ferroelectric transistor and preparation method thereof |
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