CN102866970B - Compact flash (CF) card reading-writing control intellectual property (IP) core special for digital signal processor (DSP) - Google Patents
Compact flash (CF) card reading-writing control intellectual property (IP) core special for digital signal processor (DSP) Download PDFInfo
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Abstract
The invention provides a compact flash (CF) card reading-writing control intellectual property (IP) core special for a digital signal processor (DSP), relates to the technical field of nonvolatile high-capacity data memory in power down and aims at solving the problem that the practical application of a commonly-used embedded controller is limited greatly due to the fact that the embedded controller is lack of a CF card. The CF card reading-writing control IP comprises a DSP connecting port, a CF card connecting port, an external memory interface (EMIF) interface, an address decoder, a control data bus, a global control register, a CF card reading module, a CF card reading module and a bus arbitration unit. The data exchange end of the DSP connecting port is communicated with one data exchange end of the EMIF interface, the other data exchange end of the CF card reading module is communicated with the data wiring exchange end of the bus arbitration unit, and the CF card data exchange end of the bus arbitration unit is communicated with the data exchange end of the CF card connecting port. The CF card reading-writing control IP is suitable for the field of nonvolatile high-capacity data memory in power down.
Description
Technical field
The present invention relates to power down non-volatile mass data technical field of memory.
Background technology
CF jig has that memory space is large, shock resistance good, easy to carry and be easy to the features such as upgrading, more and more applied in Large Copacity portable data storage.The method of current embedded system control CF card mainly contains following several:
1. utilize flush bonding processor port and accessory logic circuit.Accessory logic circuit can be built by the logic gate of 74 series, also can realize with CPLD or FPGA.This scheme is subject to processing the performance limitations of device port, cannot realize the UDMA protocol transmission of CF card, CF card read or write speed is not high, and the occupancy of data storage procedure to CPU is higher, reduce system works performance, the occasion of high-speed data acquisition record can not be applied to.
2. in FPGA, build flush bonding processor, as NiosII, bamboo product Avalon interface, to the IP kernel of CF interface, utilizes the access of NiosII processor realization to CF card.The program can reduce the occupation rate to outside master cpu, but realizes more complicated.
3. flush bonding processor carries CF card controller.As the pxa255 processor of Intel Company and the AT91RM9200 of Atmel company.This kind of processor provides CF card interface, can facilitate realize the control of CF card.
Such as, but in the conventional embedded controller of major part, integrated CF card controller is also little, arm processor, TMS320C6000 series DSP etc.Conventional embedded controller owing to lacking CF card interface, and produces the problem that practical application is extremely restricted.
Summary of the invention
The object of the invention is to solve existing conventional embedded controller owing to lacking CF card interface, and produce the problem that practical application is extremely restricted, a kind of DSP special CF card Read-write Catrol IP kernel is provided.
DSP special CF card Read-write Catrol IP kernel, it comprises DSP connectivity port, CF card connectivity port, EMIF interface, address decoder, control data bus, overall situation control register, CF card read through model, CF card writing module and bus arbiter unit, the exchanges data end of DSP connectivity port is communicated with a data exchange end of EMIF interface, the output terminal of the address signal of DSP connectivity port is communicated with the input end of the address signal of EMIF interface, the output terminal of the control signal of DSP connectivity port is communicated with the input end of the control signal of EMIF interface, the output terminal of an address signal of EMIF interface is communicated with the input end of the address signal of address decoder, the output terminal of another address signal of EMIF interface is communicated with the input end of the address signal of bus arbiter unit, another exchanges data end of EMIF interface is communicated with control data bus, the output terminal of the chip selection signal of address decoder simultaneously with the input end of the chip selection signal of overall control register, the input end of the chip selection signal of CF card read through model is communicated with the input end of the chip selection signal of CF card writing module, the exchanges data end of overall situation control register, a data exchange end of CF card read through model, a data exchange end of CF card writing module is communicated with control data bus with the bus data exchange end of bus arbiter unit simultaneously, the output terminal of the agreement signalization of overall situation control register is communicated with the input end of the agreement signalization of CF card read through model, the output terminal that the pattern of overall situation control register is arranged is communicated with the input end of the mode setting signal of CF card writing module, another exchanges data end of CF card read through model is communicated with the read data exchange end of bus arbiter unit, another exchanges data end of CF card writing module is communicated with the exchanges data end of writing of bus arbiter unit, the output terminal of control signal of CF card read through model is communicated with the input end of the read control signal of bus arbiter unit, and the output terminal reading enable control signal of CF card read through model is communicated with the input end reading enable control signal of bus arbiter unit, another exchanges data end of CF card writing module is communicated with the exchanges data end of writing of bus arbiter unit, the output terminal of control signal of CF card writing module is communicated with the input end of the write control signal of bus arbiter unit, the output terminal writing enable control signal of CF card writing module is communicated with the input end writing enable control signal of bus arbiter unit, the CF card exchanges data end of bus arbiter unit is communicated with the exchanges data end of CF card connectivity port, the output terminal of the CF card address signal of bus arbiter unit is communicated with the input end of the address signal of CF card connectivity port, the output terminal of the control signal of bus arbiter unit is communicated with the input end of the control signal of CF card connectivity port.
Advantage of the present invention comprises: (I) completes all processes of CF card configuration automatically, simplifies CPU operation steps, decreases taking CPU, improve the operational efficiency of entire system.(II) the super direct memory access UDMA achieved under CF card ide IDE pattern transmits, and improves message transmission rate, is more suitable for the storage of high speed big data quantity.(III) speed supported along with CF card itself improves constantly, and just goes for the fastest up-to-date CF card by the work clock adjusting IP kernel.(IV) general external memory storage EMIF interface, improves the portability of IP kernel, makes it can be applied to fast in the system of DSP master control.
Accompanying drawing explanation
Fig. 1 is composition structural representation of the present invention, Fig. 2 is the composition structural representation of the read through model of embodiment three, Fig. 3 is the composition structural representation of the writing module of embodiment four, Fig. 4 is the principle of work schematic diagram reading to control state machine of embodiment five, and Fig. 5 is the principle of work schematic diagram writing control state machine of embodiment six.
Embodiment
Embodiment one: composition graphs 1 illustrates present embodiment, the special CF card of DSP described in present embodiment Read-write Catrol IP kernel, it comprises DSP connectivity port 1, CF card connectivity port 2, EMIF interface 3, address decoder 4, control data bus 5, overall situation control register 6, CF card read through model 7, CF card writing module 8 and bus arbiter unit 9, the exchanges data end of DSP connectivity port 1 is communicated with a data exchange end of EMIF interface 3, the output terminal of the address signal of DSP connectivity port 1 is communicated with the input end of the address signal of EMIF interface 3, the output terminal of the control signal of DSP connectivity port 1 is communicated with the input end of the control signal of EMIF interface 3, the output terminal of an address signal of EMIF interface 3 is communicated with the input end of the address signal of address decoder 4, the output terminal of another address signal of EMIF interface 3 is communicated with the input end of the address signal of bus arbiter unit 9, another exchanges data end of EMIF interface 3 is communicated with control data bus 5, the output terminal of the chip selection signal of address decoder 4 simultaneously with the input end of the chip selection signal of overall control register 6, the input end of the chip selection signal of CF card read through model 7 is communicated with the input end of the chip selection signal of CF card writing module 8, the exchanges data end of overall situation control register 6, a data exchange end of CF card read through model 7, a data exchange end of CF card writing module 8 is communicated with control data bus 5 with the bus data exchange end of bus arbiter unit 9 simultaneously, the output terminal of the agreement signalization of overall situation control register 6 is communicated with the input end of the agreement signalization of CF card read through model 7, the output terminal that the pattern of overall situation control register 6 is arranged is communicated with the input end of the mode setting signal of CF card writing module 8, another exchanges data end of CF card read through model 7 is communicated with the read data exchange end of bus arbiter unit 9, another exchanges data end of CF card writing module 8 is communicated with the exchanges data end of writing of bus arbiter unit 9, the output terminal of the control signal of CF card read through model 7 is communicated with the input end of the read control signal of bus arbiter unit 9, and the output terminal reading enable control signal of CF card read through model 7 is communicated with the input end reading enable control signal of bus arbiter unit 9, another exchanges data end of CF card writing module 8 is communicated with the exchanges data end of writing of bus arbiter unit 9, the output terminal of the control signal of CF card writing module 8 is communicated with the input end of the write control signal of bus arbiter unit 9, the output terminal writing enable control signal of CF card writing module 8 is communicated with the input end writing enable control signal of bus arbiter unit 9, the CF card exchanges data end of bus arbiter unit 9 is communicated with the exchanges data end of CF card connectivity port 2, the output terminal of the CF card address signal of bus arbiter unit 9 is communicated with the input end of the address signal of CF card connectivity port 2, the output terminal of the control signal of bus arbiter unit 9 is communicated with the input end of the control signal of CF card connectivity port 2.
Advantage of the present invention comprises: (I) completes all processes of CF card configuration automatically, simplifies CPU operation steps, decreases taking CPU, improve the operational efficiency of entire system.(II) the super direct memory access UDMA achieved under CF card ide IDE pattern transmits, and improves message transmission rate, is more suitable for the storage of high speed big data quantity.(III) speed supported along with CF card itself improves constantly, and just goes for the fastest up-to-date CF card by the work clock adjusting IP kernel.(IV) general external memory storage EMIF interface, improves the portability of IP kernel, makes it can be applied to fast in the system of TMS320C6000 series DSP master control.
The modular design of EMIF Interference fit of standard, makes this IP kernel can conveniently be transplanted in the system of TMS320C6000 series DSP+FPGA, realizes the application demand of mass data storage fast.
EMIF Interface Matching module comprises the bus bar framework between the inner each module of IP kernel, and completes the address decoding of DSP address signal, produces the gating signal of each module, realizes the access of CPU to disparate modules.
Overall situation control register, for arranging the Data Transport Protocol under CF card IDE pattern, can be configured to UDMA host-host protocol or PIO host-host protocol.In addition, overall control register is autostore pattern or manual memory module for configuring IP kernel mode of operation.Under autostore pattern, DSP only need send startup command, namely writes the initial configuration of 1, CF card toward read/write command register and various preliminary work just can complete automatically.Under WriteMode, there are the data being greater than two sectors just can automatically write in CF card in FIFO memory and go, cease and desist order until DSP sends.Under reading mode, there is the space that is greater than two sectors in FIFO memory and the data taking-up in CF card just can be write in FIFO by data automatically that do not run through in addition in CF card.Under manual mode, each configuration effort and condition adjudgement are realized by dsp software completely.
The transmission of writing that CF card writing module realizes CF card controls, by access CF card internal register, the data that buffering DSP writes toward CF card, initiation UDMA writes transmission or PIO (performing the data exchange mode that I/O port command carries out the read-write of data by CPU) writes transmission.CF card read through model realizes CF card and reads transmission and control, and by configuration CF card internal register, initiates UDMA and reads transmission or PIO reads transmission, cushions and to read back next data from CF card.Bus arbiter unit, for determining the annexation of writing module bus, read through model bus and EMIF bus three and CF card hardware bus, avoids the conflict that each module common signal line causes.
Embodiment two: present embodiment is the further restriction to DSP special CF card Read-write Catrol IP kernel described in embodiment one, described overall control register 6 also comprises agreement and arranges register 6-1 and pattern arranges register 6-2, the output terminal that agreement arranges register 6-1 is the output terminal of the agreement signalization of overall control register 6, and the output terminal that pattern arranges register 6-2 is the output terminal that the pattern of overall control register 6 is arranged.
Embodiment three: composition graphs 2 illustrates present embodiment, present embodiment is the further restriction to DSP special CF card Read-write Catrol IP kernel described in embodiment one, CF card read through model 7 is by reading to control state machine, FIFO memory, fifo controller, protocol configuration unit, transmission configuration unit, PIO protocol transmission control module and UDMA protocol transmission control module composition, the exchanges data end of overall situation control register 6 is communicated with control data bus 5, the input end of the control signal of overall situation control register 6 is communicated with control data bus 5, the chip selection signal input end of described overall control register 6 is communicated with the chip selection signal input end of fifo controller, and the input end of chip selection signal as CF card read through model 7,
The input end of the control signal of fifo controller is communicated with control data bus 5, the data output end of FIFO memory is communicated with control data bus 5, and the data input pin of FIFO memory is communicated with the data output end of UDMA protocol transmission control module with the data output end of PIO protocol transmission control module simultaneously, the input end reading to control of fifo controller is communicated with the output terminal reading to control of UDMA protocol transmission control module with the output terminal reading to control of PIO protocol transmission control module simultaneously, the status signal exchange end of overall situation control register 6 is communicated with the handshake terminal of transmission configuration unit with the handshake terminal of protocol configuration unit simultaneously, the output terminal of overall situation control register 6 is connected to the input end reading to control state machine, described control state machine of reading is realized by software module, the output terminal of the marking signal of fifo controller is communicated with the input end reading the marking signal controlling state machine, the input end reading the done state signal controlling state machine simultaneously with the output terminal of protocol configuration unit done state signal, the output terminal of transmission configuration unit done state signal, the output terminal of PIO protocol transmission control module done state signal is communicated with the output terminal of UDMA protocol transmission control module done state signal, the output terminal reading the enable control signal controlling state machine is the output terminal of the enable control signal of CF card read through model 7, the output terminal reading the state control signal controlling state machine is communicated with the input end of the state control signal of UDMA protocol transmission control module with protocol configuration unit, transmission configuration unit, PIO protocol transmission control module simultaneously
The exchanges data end of protocol configuration unit is communicated with the protocol configuration exchanges data end of bus arbiter unit 9, the exchanges data end of transmission configuration unit is communicated with the transmission configuration exchanges data end of bus arbiter unit 9, the read data input end of PIO protocol transmission control module is communicated with the PIO agreement read data output terminal of bus arbiter unit 9, and the read data input end of UDMA protocol transmission control module is communicated with the UDMA agreement read data output terminal of bus arbiter unit 9.
Embodiment four: composition graphs 3 illustrates present embodiment, present embodiment is the further restriction to DSP special CF card Read-write Catrol IP kernel described in embodiment one, CF card writing module 8 is by writing control state machine FIFO memory, fifo controller, protocol configuration unit, transmission configuration unit, PIO protocol transmission control module and UDMA protocol transmission control module composition, the exchanges data end of overall situation control register 6 is communicated with control data bus 5, the input end of the control signal of overall situation control register 6 is communicated with control data bus 5, the chip selection signal input end of described overall control register 6 is communicated with the chip selection signal input end of fifo controller, and the input end of chip selection signal as CF card writing module 8,
The input end of the control signal of fifo controller is communicated with control data bus 5, the data output end of FIFO memory is communicated with control data bus 5, and the data output end of FIFO memory is communicated with the data input pin of UDMA protocol transmission control module with the data input pin of PIO protocol transmission control module simultaneously, the input end writing control of fifo controller is communicated with the output terminal writing control of UDMA protocol transmission control module with the output terminal writing control of PIO protocol transmission control module simultaneously, the status signal exchange end of overall situation control register 6 is communicated with the handshake terminal of transmission configuration unit with the handshake terminal of protocol configuration unit simultaneously, the output terminal of overall situation control register 6 is connected to the input end writing control state machine, described control state machine of writing is realized by software module, the output terminal of the marking signal of fifo controller is communicated with the input end writing the marking signal controlling state machine, the input end writing the done state signal of control state machine simultaneously with the output terminal of protocol configuration unit done state signal, the output terminal of transmission configuration unit done state signal, the output terminal of PIO protocol transmission control module done state signal is communicated with the output terminal of UDMA protocol transmission control module done state signal, the output terminal writing the enable control signal of control state machine is the output terminal of the enable control signal of CF card writing module (8), the output terminal writing the state control signal of control state machine simultaneously with protocol configuration unit, transmission configuration unit, PIO protocol transmission control module is communicated with the input end of the state control signal of UDMA protocol transmission control module, the exchanges data end of protocol configuration unit is communicated with the protocol configuration exchanges data end of bus arbiter unit 9, the exchanges data end of transmission configuration unit is communicated with the transmission configuration exchanges data end of bus arbiter unit 9, the data output end of writing of PIO protocol transmission control module is write data input pin with the PIO agreement of bus arbiter unit 9 and is communicated with, the data output end of writing of UDMA protocol transmission control module is write data input pin with the UDMA agreement of bus arbiter unit 9 and is communicated with.
Embodiment five: composition graphs 4 illustrates, present embodiment is the further restriction to DSP special CF card Read-write Catrol IP kernel described in embodiment three, described control state machine of reading comprises five states: be respectively idle condition, init state, configuration status, read data state and change LBA (Logical Block Addressing) state, wherein:
Idle condition is the default state that system starts, for each signal is set to disarmed state; When the rising edge of start up command signals being detected, jump to init state;
Init state, the parameter of initializtion protocol dispensing unit, transmission configuration unit, PIO protocol transmission control module and UDMA protocol transmission control module, and activated protocol dispensing unit, then jump to configuration status;
Configuration status, from overall control register reading protocol configuration information and according to described information configuration host-host protocol; Sector count register, sector number register, low cylinder register and high cylinder register in configuration CF card, after having configured, jump to read data state;
Read data state, the host-host protocol of employing configuration, activates PIO protocol transmission unit or UDMA protocol transmission unit, and initiate the read operation that data transmission realizes CF card, the process of read operation is: the data in reading CF card are in FIFO memory; After reading completes, jump to change logical address state;
Change logical address state, when automatic mode be enabled and CF card non-NULL time, cumulative LBA address, then jumps to configuration status automatically; When sky read by CF card, jump to idle condition, complete the read operation of a CF card.
Embodiment six: composition graphs 5 illustrates, present embodiment is the further restriction to DSP special CF card Read-write Catrol IP kernel described in embodiment four, described control state machine of writing comprises five states: be respectively idle condition, init state, configuration status, write data mode and change LBA (Logical Block Addressing) state, wherein:
Idle condition is the default state that system starts, for each signal is set to disarmed state; When the rising edge of start up command signals being detected, jump to init state;
Init state, the parameter of initializtion protocol dispensing unit, transmission configuration unit, PIO protocol transmission control module and UDMA protocol transmission control module, and activated protocol dispensing unit, then jump to configuration status;
Configuration status, from overall control register reading protocol configuration information and according to described information configuration host-host protocol; Sector count register, sector number register, low cylinder register and high cylinder register in configuration CF card, after having configured, jump to and write data mode;
Write data mode, adopt the host-host protocol of configuration, activate PIO protocol transmission unit or UDMA protocol transmission unit, initiate the write operation that data transmission realizes CF card, the process of write operation is: the data in FIFO memory are written in CF card; After write completes, jump to change logical address state;
Change logical address state, when automatic mode be enabled and the Stop that ceases and desist order is invalid or Stop effectively but FIFO memory non-NULL time, cumulative LBA address, then jumps to configuration status automatically; When the Stop that ceases and desist order is effective and FIFO memory is empty, jumps to idle condition, complete a CF card write operation.
Read transmission at startup CF card or before writing transmission, need to arrange overall control register by EMIF interface, comprise the setting of CF card mode of operation and the setting of CF card host-host protocol.
Under manual mode, DSP is by EMIF interface directly control CF card.
Initiate under automatic mode to write transmission: address decoding sheet selects writing module, bus arbiter module enable write module bus, DSP is by EMIF interface accessing CF card writing module, configure its internal register, comprise startup command, cease and desist order, initial LBA address and read to control state machine or write control state machine DataTrans state time the sector number etc. that transmits, then send and start transmission command.After having configured, writing module judges whether CF card is ready to, and is ready to, and judges whether FIFO memory has data, if having data and data volume is greater than two sectors, then from FIFO, reads data write CF card.When read control state machine or write control state machine complete the transmission of once regulation sector number time, read control state machine or write control state machine to judge whether register of ceasing and desisting order is 1, be 1 and close CF card transmission channel.
Transmission of reading under automatic transmission mode has two kinds of operational modes: a kind of be according to arrange read initial LBA address and read to terminate LBA address complete all digital independent between CF card this sector address interior; Another whether reads sky, until all for CF card valid data are read out according to the frame head of valid data in CF card and postamble automatic decision CF card.When transmission is read in initiation, address decoding sheet selects module to read, and DSP, by EMIF interface accessing CF card read through model, configures its internal register, comprises the frame head of reference position and the postamble of end position or the initial LBA address of valid data in CF card and terminates LBA address.When DSP writes 1 toward the startup command register of read through model, bus arbiter module enable read module bus, read through model starts the configuration effort that CF card is read to transmit, constantly read valid data write FIFO memory from CF card, when FIFO memory data capacity residue is less than two sectors, suspend and read transmission, recover again after waiting DSP to read away data to read transmission.When carrying out reading transmission according to frame head postamble, read through model constantly judges valid data frame head and postamble, until when judging that CF card valid data read sky, just stops sector data to be passed to write in FIFO memory, regulation sector number reportedly complete rear stopping read through model.When carrying out reading transmission according to LBA at whole story address, carried out after single specifies the transmission of sector number (being no more than 256), LBA adds up address automatically, enters and transmits next time, until LBA address is added to and terminates LBA address and then stop read through model.
Read to control state machine or write the work controlled state machine and serve as CPU, its realization is the key greatly reduced in CF card storing process master cpu resource occupation.Read control state machine or write the control state machine control whole storage of CF card or reading process, controlling each unit and complete the operations such as order transmission, condition adjudgement, data transmission.
Claims (6)
1.DSP special CF card Read-write Catrol IP kernel, it is characterized in that, it comprises DSP connectivity port (1), CF card connectivity port (2), EMIF interface (3), address decoder (4), control data bus (5), overall situation control register (6), CF card read through model (7), CF card writing module (8) and bus arbiter unit (9), the exchanges data end of DSP connectivity port (1) is communicated with a data exchange end of EMIF interface (3), the output terminal of the address signal of DSP connectivity port (1) is communicated with the input end of the address signal of EMIF interface (3), the output terminal of the control signal of DSP connectivity port (1) is communicated with the input end of the control signal of EMIF interface (3), the output terminal of an address signal of EMIF interface (3) is communicated with the input end of the address signal of address decoder (4), the output terminal of another address signal of EMIF interface (3) is communicated with the input end of the address signal of bus arbiter unit (9), another exchanges data end of EMIF interface (3) is communicated with control data bus (5), the output terminal of the chip selection signal of address decoder (4) simultaneously with the input end of the chip selection signal of overall control register (6), the input end of the chip selection signal of CF card read through model (7) is communicated with the input end of the chip selection signal of CF card writing module (8), the exchanges data end of overall situation control register (6), a data exchange end of CF card read through model (7), a data exchange end of CF card writing module (8) is communicated with control data bus (5) with the bus data exchange end of bus arbiter unit (9) simultaneously, the output terminal of the agreement signalization of overall situation control register (6) is communicated with the input end of the agreement signalization of CF card read through model (7), the output terminal that the pattern of overall situation control register (6) is arranged is communicated with the input end of the mode setting signal of CF card writing module (8), another exchanges data end of CF card read through model (7) is communicated with the read data exchange end of bus arbiter unit (9), another exchanges data end of CF card writing module (8) is communicated with the exchanges data end of writing of bus arbiter unit (9), the output terminal of the control signal of CF card read through model (7) is communicated with the input end of the read control signal of bus arbiter unit (9), and the output terminal reading enable control signal of CF card read through model (7) is communicated with the input end reading enable control signal of bus arbiter unit (9), another exchanges data end of CF card writing module (8) is communicated with the exchanges data end of writing of bus arbiter unit (9), the output terminal of the control signal of CF card writing module (8) is communicated with the input end of the write control signal of bus arbiter unit (9), the output terminal writing enable control signal of CF card writing module (8) is communicated with the input end writing enable control signal of bus arbiter unit (9), the CF card exchanges data end of bus arbiter unit (9) is communicated with the exchanges data end of CF card connectivity port (2), the output terminal of the CF card address signal of bus arbiter unit (9) is communicated with the input end of the address signal of CF card connectivity port (2), the output terminal of the control signal of bus arbiter unit (9) is communicated with the input end of the control signal of CF card connectivity port (2).
2. DSP special CF card Read-write Catrol IP kernel according to claim 1, it is characterized in that, described overall control register (6) also comprises agreement and arranges register (6-1) and pattern arranges register (6-2), the output terminal that agreement arranges register (6-1) is the output terminal of the agreement signalization of overall control register (6), and the output terminal that pattern arranges register (6-2) is the output terminal that the pattern of overall control register (6) is arranged.
3. DSP special CF card Read-write Catrol IP kernel according to claim 1, it is characterized in that, CF card read through model (7) is by reading to control state machine, FIFO memory, fifo controller, protocol configuration unit, transmission configuration unit, PIO protocol transmission control module and UDMA protocol transmission control module composition, the exchanges data end of overall situation control register (6) is communicated with control data bus (5), the input end of the control signal of overall situation control register (6) is communicated with control data bus (5), the described chip selection signal input end of overall control register (6) is communicated with the chip selection signal input end of fifo controller, and the input end of chip selection signal as CF card read through model (7), the input end of the control signal of fifo controller is communicated with control data bus (5), the data output end of FIFO memory is communicated with control data bus (5), and the data input pin of FIFO memory is communicated with the data output end of UDMA protocol transmission control module with the data output end of PIO protocol transmission control module simultaneously, the input end reading to control of fifo controller is communicated with the output terminal reading to control of UDMA protocol transmission control module with the output terminal reading to control of PIO protocol transmission control module simultaneously, the status signal exchange end of overall situation control register (6) is communicated with the handshake terminal of transmission configuration unit with the handshake terminal of protocol configuration unit simultaneously, the output terminal of overall situation control register (6) is connected to the input end reading to control state machine, described control state machine of reading is realized by software module, the output terminal of the marking signal of fifo controller is communicated with the input end reading the marking signal controlling state machine, the input end reading the done state signal controlling state machine simultaneously with the output terminal of protocol configuration unit done state signal, the output terminal of transmission configuration unit done state signal, the output terminal of PIO protocol transmission control module done state signal is communicated with the output terminal of UDMA protocol transmission control module done state signal, the output terminal reading the enable control signal controlling state machine is the output terminal of the enable control signal of CF card read through model (7), the output terminal reading the state control signal controlling state machine simultaneously with protocol configuration unit, transmission configuration unit, PIO protocol transmission control module is communicated with the input end of the state control signal of UDMA protocol transmission control module, the exchanges data end of protocol configuration unit is communicated with the protocol configuration exchanges data end of bus arbiter unit (9), the exchanges data end of transmission configuration unit is communicated with the transmission configuration exchanges data end of bus arbiter unit (9), the read data input end of PIO protocol transmission control module is communicated with the PIO agreement read data output terminal of bus arbiter unit (9), the read data input end of UDMA protocol transmission control module is communicated with the UDMA agreement read data output terminal of bus arbiter unit (9).
4. DSP special CF card Read-write Catrol IP kernel according to claim 1, it is characterized in that, CF card writing module (8) is by writing control state machine FIFO memory, fifo controller, protocol configuration unit, transmission configuration unit, PIO protocol transmission control module and UDMA protocol transmission control module composition, the exchanges data end of overall situation control register (6) is communicated with control data bus (5), the input end of the control signal of overall situation control register (6) is communicated with control data bus (5), the described chip selection signal input end of overall control register (6) is communicated with the chip selection signal input end of fifo controller, and the input end of chip selection signal as CF card writing module (8), the input end of the control signal of fifo controller is communicated with control data bus (5), the data output end of FIFO memory is communicated with control data bus (5), and the data output end of FIFO memory is communicated with the data input pin of UDMA protocol transmission control module with the data input pin of PIO protocol transmission control module simultaneously, the input end writing control of fifo controller is communicated with the output terminal writing control of UDMA protocol transmission control module with the output terminal writing control of PIO protocol transmission control module simultaneously, the status signal exchange end of overall situation control register (6) is communicated with the handshake terminal of transmission configuration unit with the handshake terminal of protocol configuration unit simultaneously, the output terminal of overall situation control register (6) is connected to the input end writing control state machine, described control state machine of writing is realized by software module, the output terminal of the marking signal of fifo controller is communicated with the input end writing the marking signal controlling state machine, the input end writing the done state signal of control state machine simultaneously with the output terminal of protocol configuration unit done state signal, the output terminal of transmission configuration unit done state signal, the output terminal of PIO protocol transmission control module done state signal is communicated with the output terminal of UDMA protocol transmission control module done state signal, the output terminal writing the enable control signal of control state machine is the output terminal of the enable control signal of CF card writing module (8), the output terminal writing the state control signal of control state machine simultaneously with protocol configuration unit, transmission configuration unit, PIO protocol transmission control module is communicated with the input end of the state control signal of UDMA protocol transmission control module, the exchanges data end of protocol configuration unit is communicated with the protocol configuration exchanges data end of bus arbiter unit (9), the exchanges data end of transmission configuration unit is communicated with the transmission configuration exchanges data end of bus arbiter unit (9), the data output end of writing of PIO protocol transmission control module is write data input pin with the PIO agreement of bus arbiter unit (9) and is communicated with, the data output end of writing of UDMA protocol transmission control module is write data input pin with the UDMA agreement of bus arbiter unit (9) and is communicated with.
5. DSP special CF card Read-write Catrol IP kernel according to claim 3, is characterized in that, described in read control state machine and comprise five states: be respectively idle condition, init state, configuration status, read data state and change LBA (Logical Block Addressing) state, wherein:
Idle condition is the default state that system starts, for each signal is set to disarmed state; When the rising edge of start up command signals being detected, jump to init state;
Init state, the parameter of initializtion protocol dispensing unit, transmission configuration unit, PIO protocol transmission control module and UDMA protocol transmission control module, and activated protocol dispensing unit, then jump to configuration status;
Configuration status, from overall control register reading protocol configuration information and according to described information configuration host-host protocol; Sector count register, sector number register, low cylinder register and high cylinder register in configuration CF card, after having configured, jump to read data state;
Read data state, the host-host protocol of employing configuration, activates PIO protocol transmission unit or UDMA protocol transmission unit, and initiate the read operation that data transmission realizes CF card, the process of read operation is: the data in reading CF card are in FIFO memory; After reading completes, jump to change logical address state;
Change logical address state, when automatic mode be enabled and CF card non-NULL time, cumulative LBA address, then jumps to configuration status automatically; When sky read by CF card, jump to idle condition, complete the read operation of a CF card.
6. DSP special CF card Read-write Catrol IP kernel according to claim 4, is characterized in that, described in write control state machine and comprise five states: be respectively idle condition, init state, configuration status, write data mode and change LBA (Logical Block Addressing) state, wherein:
Idle condition is the default state that system starts, for each signal is set to disarmed state; When the rising edge of start up command signals being detected, jump to init state;
Init state, the parameter of initializtion protocol dispensing unit, transmission configuration unit, PIO protocol transmission control module and UDMA protocol transmission control module, and activated protocol dispensing unit, then jump to configuration status;
Configuration status, from overall control register reading protocol configuration information and according to described information configuration host-host protocol; Sector count register, sector number register, low cylinder register and high cylinder register in configuration CF card, after having configured, jump to and write data mode;
Write data mode, adopt the host-host protocol of configuration, activate PIO protocol transmission unit or UDMA protocol transmission unit, initiate the write operation that data transmission realizes CF card, the process of write operation is: the data in FIFO memory are written in CF card; After write completes, jump to change logical address state;
Change logical address state, when automatic mode be enabled and the Stop that ceases and desist order is invalid or Stop effectively but FIFO memory non-NULL time, cumulative LBA address, then jumps to configuration status automatically; When the Stop that ceases and desist order is effective and FIFO memory is empty, jumps to idle condition, complete a CF card write operation.
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| CN101464846A (en) * | 2008-12-09 | 2009-06-24 | 北京星网锐捷网络技术有限公司 | Data card read-write method, interface control method and apparatus |
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| US6049842A (en) * | 1997-05-01 | 2000-04-11 | International Business Machines Corporation | Efficient data transfer mechanism for input/output devices |
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