CN102866970A - Compact flash (CF) card reading-writing control intellectual property (IP) core special for digital signal processor (DSP) - Google Patents
Compact flash (CF) card reading-writing control intellectual property (IP) core special for digital signal processor (DSP) Download PDFInfo
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Abstract
The invention provides a compact flash (CF) card reading-writing control intellectual property (IP) core special for a digital signal processor (DSP), relates to the technical field of nonvolatile high-capacity data memory in power down and aims at solving the problem that the practical application of a commonly-used embedded controller is limited greatly due to the fact that the embedded controller is lack of a CF card. The CF card reading-writing control IP comprises a DSP connecting port, a CF card connecting port, an external memory interface (EMIF) interface, an address decoder, a control data bus, a global control register, a CF card reading module, a CF card reading module and a bus arbitration unit. The data exchange end of the DSP connecting port is communicated with one data exchange end of the EMIF interface, the other data exchange end of the CF card reading module is communicated with the data wiring exchange end of the bus arbitration unit, and the CF card data exchange end of the bus arbitration unit is communicated with the data exchange end of the CF card connecting port. The CF card reading-writing control IP is suitable for the field of nonvolatile high-capacity data memory in power down.
Description
Technical field
The present invention relates to the non-volatile mass data storage technical field of power down.
Background technology
The CF jig has that memory space is large, shock resistance good, easy to carry and be easy to the characteristics such as upgrading, in large capacity portable data storage, more and more used.The method of at present embedded system control CF card mainly contains following several:
1. utilize flush bonding processor port and accessory logic circuit.Accessory logic circuit can be built with the logic gate of 74 series, also can realize with CPLD or FPGA.This scheme is subject to processing the performance limitations of device port, can't realize the UDMA protocol transmission of CF card, CF card read or write speed is not high, and data storage procedure is higher to the occupancy of CPU, reduce the system works performance, can not be applied to the occasion of high-speed data acquisition record.
2. in FPGA, make up flush bonding processor, such as NiosII, design again the Avalon interface to the IP kernel of CF interface, utilize the realization of NiosII processor to the access of CF card.This scheme can reduce the occupation rate to outside master cpu, but realizes complicated.
3. flush bonding processor carries the CF card controller.Such as the pxa255 processor of Intel Company and the AT91RM9200 of Atmel company.This class processor provides the CF card interface, can make things convenient for to such an extent that realize the control of CF card.
But in most of commonly used embedded controller integrated CF card controller also seldom, such as arm processor, TMS320C6000 series DSP etc.Commonly use embedded controller owing to lacking the CF card interface, and produce the problem that practical application is extremely restricted.
Summary of the invention
To the objective of the invention is to have embedded controller commonly used now owing to lacking the CF card interface in order solving, and to produce the problem that practical application is extremely restricted, provide the special-purpose CF card of a kind of DSP to read and write the control IP kernel.
The special-purpose CF card read-write of DSP control IP kernel, it comprises the DSP connectivity port, CF links and connects port, the EMIF interface, address decoder, the control data bus, overall situation control register, CF card read through model, CF card writing module and bus arbiter unit, the exchanges data end of DSP connectivity port is communicated with a data exchange end of EMIF interface, the output terminal of the address signal of DSP connectivity port is communicated with the input end of the address signal of EMIF interface, the output terminal of the control signal of DSP connectivity port is communicated with the input end of the control signal of EMIF interface, the output terminal of an address signal of EMIF interface is communicated with the input end of the address signal of address decoder, the output terminal of another address signal of EMIF interface is communicated with the input end of the address signal of bus arbiter unit, another exchanges data end of EMIF interface is communicated with the control data bus, the output terminal while of the chip selection signal of address decoder and the input end of the chip selection signal of overall control register, the input end of the chip selection signal of the input end of the chip selection signal of CF card read through model and CF card writing module is communicated with, the exchanges data end of overall situation control register, a data exchange end of CF card read through model, data exchange end of CF card writing module and the bus data exchange end of bus arbiter unit are communicated with the control data bus simultaneously, the output terminal of the agreement signalization of overall situation control register is communicated with the input end of the agreement signalization of CF card read through model, and the output terminal that the pattern of overall control register arranges is communicated with the input end of the pattern signalization of CF card writing module; Another exchanges data end of CF card read through model is communicated with the read data exchange end of bus arbiter unit, another exchanges data end of CF card writing module is communicated with the exchanges data end of writing of bus arbiter unit, the output terminal of the control signal of CF card read through model is communicated with the input end of the read control signal of bus arbiter unit, and the input end that the reading of the output terminal that the reading of CF card read through model enables control signal and bus arbiter unit enables control signal is communicated with; Another exchanges data end of CF card writing module is communicated with the exchanges data end of writing of bus arbiter unit, the output terminal of the control signal of CF card writing module is communicated with the input end of the write control signal of bus arbiter unit, the output terminal that enables control signal of writing of CF card writing module is communicated with the input end that writing of bus arbiter unit enables control signal, CF card exchanges data end and the CF of bus arbiter unit link the exchanges data end that connects port and are communicated with, the output terminal of the CF card address signal of bus arbiter unit is communicated with the input end that CF links the address signal that connects port, and the output terminal of the control signal of bus arbiter unit is communicated with the input end that CF links the control signal that connects port.
Advantage of the present invention comprises: (I) automatically finish all processes of CF card configuration, simplified the CPU operation steps, reduced the taking of CPU, improved the operational efficiency of entire system.(II) realized that the super direct memory access UDMA under the CF card ide IDE pattern transmits, improved message transmission rate, be more suitable for the storage of high speed big data quantity.(III) speed of supporting along with CF card itself improves constantly, and just goes for the fastest up-to-date CF card by the work clock of adjusting IP kernel.(IV) general external memory storage EMIF interface has improved the portability of IP kernel, makes it and can be applied to fast in the system of DSP master control.
Description of drawings
Fig. 1 is composition structural representation of the present invention, Fig. 2 is the composition structural representation of the read through model of embodiment three, Fig. 3 is the composition structural representation of the writing module of embodiment four, Fig. 4 is the principle of work schematic diagram of reading to control state machine of embodiment five, and Fig. 5 is the principle of work schematic diagram of writing the control state machine of embodiment six.
Embodiment
Embodiment one: present embodiment is described in conjunction with Fig. 1, the special-purpose CF card read-write of the described DSP of present embodiment control IP kernel, it comprises DSP connectivity port 1, CF links and connects port 2, EMIF interface 3, address decoder 4, control data bus 5, overall situation control register 6, CF card read through model 7, CF card writing module 8 and bus arbiter unit 9, the exchanges data end of DSP connectivity port 1 is communicated with a data exchange end of EMIF interface 3, the output terminal of the address signal of DSP connectivity port 1 is communicated with the input end of the address signal of EMIF interface 3, the output terminal of the control signal of DSP connectivity port 1 is communicated with the input end of the control signal of EMIF interface 3, the output terminal of an address signal of EMIF interface 3 is communicated with the input end of the address signal of address decoder 4, the output terminal of another address signal of EMIF interface 3 is communicated with the input end of the address signal of bus arbiter unit 9, another exchanges data end of EMIF interface 3 is communicated with control data bus 5, the output terminal while of the chip selection signal of address decoder 4 and the input end of the chip selection signal of overall control register 6, the input end of the chip selection signal of the input end of the chip selection signal of CF card read through model 7 and CF card writing module 8 is communicated with, the exchanges data end of overall situation control register 6, a data exchange end of CF card read through model 7, data exchange end of CF card writing module 8 and the bus data exchange end of bus arbiter unit 9 are communicated with control data bus 5 simultaneously, the output terminal of the agreement signalization of overall situation control register 6 is communicated with the input end of the agreement signalization of CF card read through model 7, and the output terminal that the pattern of overall control register 6 arranges is communicated with the input end of the pattern signalization of CF card writing module 8; Another exchanges data end of CF card read through model 7 is communicated with the read data exchange end of bus arbiter unit 9, another exchanges data end of CF card writing module 8 is communicated with the exchanges data end of writing of bus arbiter unit 9, the output terminal of the control signal of CF card read through model 7 is communicated with the input end of the read control signal of bus arbiter unit 9, and the input end that the reading of the output terminal that the reading of CF card read through model 7 enables control signal and bus arbiter unit 9 enables control signal is communicated with; Another exchanges data end of CF card writing module 8 is communicated with the exchanges data end of writing of bus arbiter unit 9, the output terminal of the control signal of CF card writing module 8 is communicated with the input end of the write control signal of bus arbiter unit 9, the output terminal that enables control signal of writing of CF card writing module 8 is communicated with the input end that writing of bus arbiter unit 9 enables control signal, CF card exchanges data end and the CF of bus arbiter unit 9 link the exchanges data end that connects port 2 and are communicated with, the output terminal of the CF card address signal of bus arbiter unit 9 is communicated with the input end that CF links the address signal that connects port 2, and the output terminal of the control signal of bus arbiter unit 9 is communicated with the input end that CF links the control signal that connects port 2.
Advantage of the present invention comprises: (I) automatically finish all processes of CF card configuration, simplified the CPU operation steps, reduced the taking of CPU, improved the operational efficiency of entire system.(II) realized that the super direct memory access UDMA under the CF card ide IDE pattern transmits, improved message transmission rate, be more suitable for the storage of high speed big data quantity.(III) speed of supporting along with CF card itself improves constantly, and just goes for the fastest up-to-date CF card by the work clock of adjusting IP kernel.(IV) general external memory storage EMIF interface has improved the portability of IP kernel, makes it and can be applied to fast in the system of TMS320C6000 series DSP master control.
The design of the EMIF interface mating die blocking of standard can conveniently be transplanted in the system of TMS320C6000 series DSP+FPGA this IP kernel, realizes fast the application demand of mass data storage.
EMIF Interface Matching module comprises the interconnected framework of bus between inner each module of IP kernel, and finishes the address decoding of DSP address signal, produces the gating signal of each module, realizes that CPU is to the access of disparate modules.
Overall situation control register is used for arranging the Data Transport Protocol under the CF card IDE pattern, can be configured to UDMA host-host protocol or PIO host-host protocol.In addition, overall control register is autostore pattern or manual memory module for configuration IP kernel mode of operation.Under the autostore pattern, DSP only need send startup command, and initial configuration and the various preliminary work of namely writing 1, CF card toward the read/write command register just can be finished automatically.Under the WriteMode, have in the FIFO storer just can automatically write in the CF card greater than the data of two sectors and go, cease and desist order until DSP sends.Under the reading mode, have in the FIFO storer just can automatically the data in the CF card be taken out greater than the data that do not run through in addition in the space of two sectors and the CF card and write among the FIFO.Under the manual mode, each configuration effort and state judgement are realized by dsp software fully.
The transmission of writing of CF card writing module realization CF card is controlled, by access CF card internal register, the data that buffering DSP writes toward the CF card, initiation UDMA writes transmission or PIO (carrying out the data exchange mode that the I/O port command carries out the read-write of data by CPU) writes transmission.CF card read through model realization CF card is read transmission control, and by configuration CF card internal register, initiation UDMA reads to transmit or PIO reads transmission, the data that buffering is read back and from the CF card.Bus arbiter unit is used for determining the annexation of writing module bus, read through model bus and EMIF bus three and CF card hardware bus, the conflict of avoiding each module common signal line to cause.
Embodiment two: present embodiment is the further restriction to the special-purpose CF card read-write of embodiment one described DSP control IP kernel, described overall control register 6 comprises that also agreement arranges register 6-1 and pattern arranges register 6-2, the output terminal that agreement arranges register 6-1 is the output terminal of the agreement signalization of overall control register 6, and the output terminal that pattern arranges register 6-2 is the output terminal of the pattern setting of overall control register 6.
Embodiment three: present embodiment is described in conjunction with Fig. 2, present embodiment is the further restriction to the special-purpose CF card read-write of embodiment one described DSP control IP kernel, CF card read through model 7 is by reading to control state machine, the FIFO storer, fifo controller, the protocol configuration unit, the transmission configuration unit, PIO protocol transmission control module and UDMA protocol transmission control module form, the exchanges data end of overall situation control register 6 is communicated with control data bus 5, the input end of the control signal of overall situation control register 6 is communicated with control data bus 5, the chip selection signal input end of described overall control register 6 and the chip selection signal input end of fifo controller are communicated with, and as the input end of the chip selection signal of CF card read through model 7;
The input end of the control signal of fifo controller is communicated with control data bus 5, the data input pin of FIFO storer is communicated with control data bus 5, and the data input pin of FIFO storer is communicated with the data output end of PIO protocol transmission control module and the data output end of UDMA protocol transmission control module simultaneously; The input end of reading to control of fifo controller is communicated with the output terminal of reading to control of PIO protocol transmission control module and the output terminal of reading to control of UDMA protocol transmission control module simultaneously; The status signal exchange end of overall situation control register 6 is communicated with the handshake terminal of protocol configuration unit and the handshake terminal of transmission configuration unit simultaneously, the output terminal of overall situation control register 6 is connected to the input end of reading to control state machine, describedly read to control state machine and realized by software module, the output terminal of the marking signal of fifo controller is communicated with the input end of the marking signal of reading to control state machine, read to control state machine the done state signal input end simultaneously with the output terminal of protocol configuration unit done state signal, the output terminal of transmission configuration unit done state signal, the output terminal of the output terminal of PIO protocol transmission control module done state signal and UDMA protocol transmission control module done state signal is communicated with; The output terminal that enables control signal of reading to control state machine is the output terminal that enables control signal of CF card read through model 7, the output terminal of reading to control the state control signal of state machine is communicated with the input end of the state control signal of protocol configuration unit, transmission configuration unit, PIO protocol transmission control module and UDMA protocol transmission control module simultaneously
The exchanges data end of protocol configuration unit is communicated with the protocol configuration exchanges data end of bus arbiter unit 9, the exchanges data end of transmission configuration unit is communicated with the transmission configuration exchanges data end of bus arbiter unit 9, the read data input end of PIO protocol transmission control module is communicated with the PIO agreement read data output terminal of bus arbiter unit 9, and the read data input end of UDMA protocol transmission control module is communicated with the UDMA agreement read data output terminal of bus arbiter unit 9.
Embodiment four: present embodiment is described in conjunction with Fig. 3, present embodiment is the further restriction to the special-purpose CF card read-write of embodiment one described DSP control IP kernel, CF card writing module 8 is by writing control state machine FIFO storer, fifo controller, the protocol configuration unit, the transmission configuration unit, PIO protocol transmission control module and UDMA protocol transmission control module form, the exchanges data end of overall situation control register 6 is communicated with control data bus 5, the input end of the control signal of overall situation control register 6 is communicated with control data bus 5, the chip selection signal input end of described overall control register 6 and the chip selection signal input end of fifo controller are communicated with, and as the input end of the chip selection signal of CF card writing module 8;
The input end of the control signal of fifo controller is communicated with control data bus 5, the data input pin of FIFO storer is communicated with control data bus 5, and the data output end of FIFO storer is communicated with the data input pin of PIO protocol transmission control module and the data input pin of UDMA protocol transmission control module simultaneously; The output terminal of writing control of fifo controller is communicated with the input end of writing control of PIO protocol transmission control module and the input end of writing control of UDMA protocol transmission control module simultaneously; The status signal exchange end of overall situation control register 6 is communicated with the handshake terminal of protocol configuration unit and the handshake terminal of transmission configuration unit simultaneously, the output terminal of overall situation control register 6 is connected to the input end of writing the control state machine, the described control state machine of writing is realized by software module, the output terminal of the marking signal of fifo controller is communicated with the input end of the marking signal of writing the control state machine, writes the input end while of the done state signal of controlling state machine and the output terminal of protocol configuration unit done state signal, the output terminal of transmission configuration unit done state signal, the output terminal of the output terminal of PIO protocol transmission control module done state signal and UDMA protocol transmission control module done state signal is communicated with; The output terminal that enables control signal of writing the control state machine is the output terminal that enables control signal of CF card writing module (8), write the output terminal while and protocol configuration unit of the state control signal of control state machine, the transmission configuration unit, the input end of the state control signal of PIO protocol transmission control module and UDMA protocol transmission control module is communicated with, the exchanges data end of protocol configuration unit is communicated with the protocol configuration exchanges data end of bus arbiter unit 9, the exchanges data end of transmission configuration unit is communicated with the transmission configuration exchanges data end of bus arbiter unit 9, the data output end of writing of PIO protocol transmission control module is write data input pin with the PIO agreement of bus arbiter unit 9 and is communicated with, and the data output end of writing of UDMA protocol transmission control module is write data input pin with the UDMA agreement of bus arbiter unit 9 and is communicated with.
Embodiment five: in conjunction with Fig. 4 explanation, present embodiment is the further restriction to the special-purpose CF card read-write of embodiment three described DSP control IP kernel, describedly read to control state machine and comprise five states: be respectively idle condition, init state, configuration status, read data state and change LBA (Logical Block Addressing) state, wherein:
Idle condition is the acquiescence attitude that system starts, and is used for each signal is set to disarmed state; When detecting the rising edge of start up command signals, jump to init state;
Init state, then the parameter of initializtion protocol dispensing unit, transmission configuration unit, PIO protocol transmission control module and UDMA protocol transmission control module, and activated protocol dispensing unit jump to configuration status;
Configuration status reads protocol configuration information and according to described information configuration host-host protocol from overall control register; Sector count register, sector number register, low cylinder register and high cylinder register in the configuration CF card, configuration jumps to the read data state after finishing;
The read data state adopts the host-host protocol of configuration, activates PIO protocol transmission unit or UDMA protocol transmission unit, initiates the read operation that data transmission realizes the CF card, and the process of read operation is: read data in the CF card in the FIFO storer; Read finish after, jump to change logical address state;
Change logical address state is when automatic mode is enabled and during CF card non-NULL, then cumulative LBA address jumps to configuration status automatically; When the CF card is read sky, jump to idle condition, finish the read operation of a CF card.
Embodiment six: in conjunction with Fig. 5 explanation, present embodiment is the further restriction to the special-purpose CF card read-write of embodiment four described DSP control IP kernel, the described control state machine of writing comprises five states: is respectively idle condition, init state, configuration status, writes data mode and change LBA (Logical Block Addressing) state, wherein:
Idle condition is the acquiescence attitude that system starts, and is used for each signal is set to disarmed state; When detecting the rising edge of start up command signals, jump to init state;
Init state, then the parameter of initializtion protocol dispensing unit, transmission configuration unit, PIO protocol transmission control module and UDMA protocol transmission control module, and activated protocol dispensing unit jump to configuration status;
Configuration status reads protocol configuration information and according to described information configuration host-host protocol from overall control register; Sector count register, sector number register, low cylinder register and high cylinder register in the configuration CF card, configuration jumps to and writes data mode after finishing;
Write data mode, adopt the host-host protocol of configuration, activate PIO protocol transmission unit or UDMA protocol transmission unit, initiate the write operation that data transmission realizes the CF card, the process of write operation is: the data in the FIFO storer are written in the CF card; Write finish after, jump to change logical address state;
Change logical address state is when automatic mode is enabled and ceases and desist order the invalid or Stop of Stop effectively but during FIFO storer non-NULL, then cumulative LBA address jumps to configuration status automatically; When ceasing and desisting order Stop effectively and FIFO storer when empty, jump to idle condition, finish CF card write operation one time.
Before startup CF card is read transmission or is write transmission, need to overall control register be set by the EMIF interface, comprise the setting of CF card mode of operation and the setting of CF card host-host protocol.
Under the manual mode, DSP directly controls the CF card by the EMIF interface.
Initiate under the automatic mode to write transmission: the address decoding sheet selects writing module, bus arbitration module enable write module bus, DSP is by EMIF interface accessing CF card writing module, configure its internal register, comprise startup command, cease and desist order, initial LBA address and the sector number that transmits when reading to control state machine or writing control state machine DataTrans attitude etc., then send and start transmission command.After configuration was finished, writing module judged whether the CF card is ready to, and is ready to then judge whether the FIFO storer has data, if data and data volume are arranged greater than two sectors, then reading out data is write the CF card in the FIFO.When reading to control state machine or write the control state machine when finishing once the transmission of regulation sector number, read to control state machine or write the control state machine and judge whether the register of ceasing and desisting order is 1, is 1 and closes CF card transmission channel.
Reading transmission under the automatic transmission mode has two kinds of operational modes: a kind of is to read initial LBA address and read to finish the LBA address and finish that all data between this sector address read in the CF card according to what arrange; Another is whether to read sky according to the frame head of valid data in the CF card and postamble automatic decision CF card, until all valid data of CF card are read out.When initiation read to transmit, the address decoding sheet was selected module to read, and DSP configures its internal register by EMIF interface accessing CF card read through model, comprised the frame head of the reference position of valid data in the CF card and postamble or initial LBA address and the end LBA address of end position.When DSP writes 1 toward the startup command register of read through model, bus arbitration module enable read module bus, read through model starts the configuration effort that the CF card is read to transmit, constantly read valid data from the CF card and write the FIFO storer, when two sectors of FIFO memory data capacity residue less than, suspend and read transmission, wait DSP to read away to recover again to read transmission after the data.When reading to transmit according to the frame head postamble, read through model is constantly judged valid data frame head and postamble, until judge when CF card valid data are read sky, just stops sector data to be passed and writes in the FIFO storer, stops read through model after the regulation sector number is reportedly complete.When the whole story, the LBA address read to transmit, carried out the transmission of single regulation sector number (being no more than 256) after, the LBA address is automatically cumulative, enters next time transmission, until the LBA address is added to and finishes the LBA address and then stop read through model.
Read to control state machine or write the work that the control state machine serves as CPU, its realization is the key that greatly reduces in the CF card storing process the master cpu resource occupation.Read to control state machine or write and control the state machine control whole storage of CF card or read process, control each unit and finish the operations such as order transmission, state judgement, data transmission.
Claims (6)
1.DSP special-purpose CF card read-write control IP kernel, it is characterized in that, it comprises DSP connectivity port (1), CF links and connects port (2), EMIF interface (3), address decoder (4), control data bus (5), overall situation control register (6), CF card read through model (7), CF card writing module (8) and bus arbiter unit (9), the exchanges data end of DSP connectivity port (1) is communicated with a data exchange end of EMIF interface (3), the output terminal of the address signal of DSP connectivity port (1) is communicated with the input end of the address signal of EMIF interface (3), the output terminal of the control signal of DSP connectivity port (1) is communicated with the input end of the control signal of EMIF interface (3), the output terminal of an address signal of EMIF interface (3) is communicated with the input end of the address signal of address decoder (4), the output terminal of another address signal of EMIF interface (3) is communicated with the input end of the address signal of bus arbiter unit (9), another exchanges data end of EMIF interface (3) is communicated with control data bus (5), the output terminal while of the chip selection signal of address decoder (4) and the input end of the chip selection signal of overall control register (6), the input end of the chip selection signal of the input end of the chip selection signal of CF card read through model (7) and CF card writing module (8) is communicated with, the exchanges data end of overall situation control register (6), a data exchange end of CF card read through model (7), data exchange end of CF card writing module (8) and the bus data exchange end of bus arbiter unit (9) are communicated with control data bus (5) simultaneously, the output terminal of the agreement signalization of overall situation control register (6) is communicated with the input end of the agreement signalization of CF card read through model (7), and the output terminal that the pattern of overall control register (6) arranges is communicated with the input end of the pattern signalization of CF card writing module (8); Another exchanges data end of CF card read through model (7) is communicated with the read data exchange end of bus arbiter unit (9), another exchanges data end of CF card writing module (8) is communicated with the exchanges data end of writing of bus arbiter unit (9), the output terminal of the control signal of CF card read through model (7) is communicated with the input end of the read control signal of bus arbiter unit (9), and the input end that the reading of the output terminal that the reading of CF card read through model (7) enables control signal and bus arbiter unit (9) enables control signal is communicated with; Another exchanges data end of CF card writing module (8) is communicated with the exchanges data end of writing of bus arbiter unit (9), the output terminal of the control signal of CF card writing module (8) is communicated with the input end of the write control signal of bus arbiter unit (9), the output terminal that enables control signal of writing of CF card writing module (8) is communicated with the input end that enables control signal of writing of bus arbiter unit (9), CF card exchanges data end and the CF of bus arbiter unit (9) link the exchanges data end that connects port (2) and are communicated with, the output terminal of the CF card address signal of bus arbiter unit (9) is communicated with the input end that CF links the address signal that connects port (2), and the output terminal of the control signal of bus arbiter unit (9) is communicated with the input end that CF links the control signal that connects port (2).
2. IP kernel is controlled in the special-purpose CF card read-write of described DSP according to claim 1, it is characterized in that, described overall control register (6) comprises that also agreement arranges register (6-1) and pattern arranges register (6-2), the output terminal that agreement arranges register (6-1) is the output terminal of the agreement signalization of overall control register (6), and the output terminal that pattern arranges register (6-2) is the output terminal of the pattern setting of overall control register (6).
3. IP kernel is controlled in the special-purpose CF card read-write of described DSP according to claim 1, it is characterized in that, CF card read through model (7) is by reading to control state machine, the FIFO storer, fifo controller, the protocol configuration unit, the transmission configuration unit, PIO protocol transmission control module and UDMA protocol transmission control module form, the exchanges data end of overall situation control register (6) is communicated with control data bus (5), the input end of the control signal of overall situation control register (6) is communicated with control data bus (5), the chip selection signal input end of described overall control register (6) and the chip selection signal input end of fifo controller are communicated with, and as the input end of the chip selection signal of CF card read through model (7); The input end of the control signal of fifo controller is communicated with control data bus (5), the data input pin of FIFO storer is communicated with control data bus (5), and the data input pin of FIFO storer is communicated with the data output end of PIO protocol transmission control module and the data output end of UDMA protocol transmission control module simultaneously; The input end of reading to control of fifo controller is communicated with the output terminal of reading to control of PIO protocol transmission control module and the output terminal of reading to control of UDMA protocol transmission control module simultaneously; The status signal exchange end of overall situation control register (6) is communicated with the handshake terminal of protocol configuration unit and the handshake terminal of transmission configuration unit simultaneously, the output terminal of overall situation control register (6) is connected to the input end of reading to control state machine, describedly read to control state machine and realized by software module, the output terminal of the marking signal of fifo controller is communicated with the input end of the marking signal of reading to control state machine, read to control state machine the done state signal input end simultaneously with the output terminal of protocol configuration unit done state signal, the output terminal of transmission configuration unit done state signal, the output terminal of the output terminal of PIO protocol transmission control module done state signal and UDMA protocol transmission control module done state signal is communicated with; The output terminal that enables control signal of reading to control state machine is the output terminal that enables control signal of CF card read through model (7), read to control state machine state control signal output terminal simultaneously and the protocol configuration unit, the transmission configuration unit, the input end of the state control signal of PIO protocol transmission control module and UDMA protocol transmission control module is communicated with, the exchanges data end of protocol configuration unit is communicated with the protocol configuration exchanges data end of bus arbiter unit (9), the exchanges data end of transmission configuration unit is communicated with the transmission configuration exchanges data end of bus arbiter unit (9), the read data input end of PIO protocol transmission control module is communicated with the PIO agreement read data output terminal of bus arbiter unit (9), and the read data input end of UDMA protocol transmission control module is communicated with the UDMA agreement read data output terminal of bus arbiter unit (9).
4. IP kernel is controlled in the special-purpose CF card read-write of described DSP according to claim 1, it is characterized in that, CF card writing module (8) is by writing control state machine FIFO storer, fifo controller, the protocol configuration unit, the transmission configuration unit, PIO protocol transmission control module and UDMA protocol transmission control module form, the exchanges data end of overall situation control register (6) is communicated with control data bus (5), the input end of the control signal of overall situation control register (6) is communicated with control data bus (5), the chip selection signal input end of described overall control register (6) and the chip selection signal input end of fifo controller are communicated with, and as the input end of the chip selection signal of CF card writing module (8); The input end of the control signal of fifo controller is communicated with control data bus (5), the data input pin of FIFO storer is communicated with control data bus (5), and the data output end of FIFO storer is communicated with the data input pin of PIO protocol transmission control module and the data input pin of UDMA protocol transmission control module simultaneously; The output terminal of writing control of fifo controller is communicated with the input end of writing control of PIO protocol transmission control module and the input end of writing control of UDMA protocol transmission control module simultaneously; The status signal exchange end of overall situation control register (6) is communicated with the handshake terminal of protocol configuration unit and the handshake terminal of transmission configuration unit simultaneously, the output terminal of overall situation control register (6) is connected to the input end of writing the control state machine, the described control state machine of writing is realized by software module, the output terminal of the marking signal of fifo controller is communicated with the input end of the marking signal of writing the control state machine, writes the input end while of the done state signal of controlling state machine and the output terminal of protocol configuration unit done state signal, the output terminal of transmission configuration unit done state signal, the output terminal of the output terminal of PIO protocol transmission control module done state signal and UDMA protocol transmission control module done state signal is communicated with; The output terminal that enables control signal of writing the control state machine is the output terminal that enables control signal of CF card writing module (8), write the output terminal while and protocol configuration unit of the state control signal of control state machine, the transmission configuration unit, the input end of the state control signal of PIO protocol transmission control module and UDMA protocol transmission control module is communicated with, the exchanges data end of protocol configuration unit is communicated with the protocol configuration exchanges data end of bus arbiter unit (9), the exchanges data end of transmission configuration unit is communicated with the transmission configuration exchanges data end of bus arbiter unit (9), the data output end of writing of PIO protocol transmission control module is write data input pin with the PIO agreement of bus arbiter unit (9) and is communicated with, and the data output end of writing of UDMA protocol transmission control module is write data input pin with the UDMA agreement of bus arbiter unit (9) and is communicated with.
5. the special-purpose CF card read-write of described DSP control IP kernel according to claim 3 is characterized in that, describedly reads to control state machine and comprises five states: be respectively idle condition, init state, configuration status, read data state and change LBA (Logical Block Addressing) state, wherein:
Idle condition is the acquiescence attitude that system starts, and is used for each signal is set to disarmed state; When detecting the rising edge of start up command signals, jump to init state;
Init state, then the parameter of initializtion protocol dispensing unit, transmission configuration unit, PIO protocol transmission control module and UDMA protocol transmission control module, and activated protocol dispensing unit jump to configuration status;
Configuration status reads protocol configuration information and according to described information configuration host-host protocol from overall control register; Sector count register, sector number register, low cylinder register and high cylinder register in the configuration CF card, configuration jumps to the read data state after finishing;
The read data state adopts the host-host protocol of configuration, activates PIO protocol transmission unit or UDMA protocol transmission unit, initiates the read operation that data transmission realizes the CF card, and the process of read operation is: read data in the CF card in the FIFO storer; Read finish after, jump to change logical address state;
Change logical address state is when automatic mode is enabled and during CF card non-NULL, then cumulative LBA address jumps to configuration status automatically; When the CF card is read sky, jump to idle condition, finish the read operation of a CF card.
6. IP kernel is controlled in the special-purpose CF card read-write of described DSP according to claim 4, it is characterized in that, the described control state machine of writing comprises five states: be respectively idle condition, init state, configuration status, write data mode and change LBA (Logical Block Addressing) state, wherein:
Idle condition is the acquiescence attitude that system starts, and is used for each signal is set to disarmed state; When detecting the rising edge of start up command signals, jump to init state;
Init state, then the parameter of initializtion protocol dispensing unit, transmission configuration unit, PIO protocol transmission control module and UDMA protocol transmission control module, and activated protocol dispensing unit jump to configuration status;
Configuration status reads protocol configuration information and according to described information configuration host-host protocol from overall control register; Sector count register, sector number register, low cylinder register and high cylinder register in the configuration CF card, configuration jumps to and writes data mode after finishing;
Write data mode, adopt the host-host protocol of configuration, activate PIO protocol transmission unit or UDMA protocol transmission unit, initiate the write operation that data transmission realizes the CF card, the process of write operation is: the data in the FIFO storer are written in the CF card; Write finish after, jump to change logical address state;
Change logical address state is when automatic mode is enabled and ceases and desist order the invalid or Stop of Stop effectively but during FIFO storer non-NULL, then cumulative LBA address jumps to configuration status automatically; When ceasing and desisting order Stop effectively and FIFO storer when empty, jump to idle condition, finish CF card write operation one time.
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| CN109446126A (en) * | 2018-10-17 | 2019-03-08 | 天津津航计算技术研究所 | DSP and FPGA high-speed communication system and method based on EMIF bus |
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