CN102857215A - Three-valued thermal-insulation domino direct circulation valve and reverse circulation valve - Google Patents

Abstract

The invention discloses a three-valued thermal-insulation domino direct circulation valve and a three-valued thermal-insulation domino reverse circulation valve which respectively comprise a three-valued low-power dissipation domino JKL trigger, wherein each three-valued low-power dissipation domino JKL trigger consists of a first three-valued thermal-insulation domino text calculation circuit, a second three-valued thermal-insulation domino text calculation circuit, a third three-valued thermal-insulation domino text calculation circuit, a fourth three-valued thermal-insulation domino text calculation circuit and a basic three-valued JKL trigger circuit; thermal-insulation logic, multi-valued logic and multi-domino circuits are combined together through the first to fourth three-valued thermal-insulation domino text calculation circuits, thus realizing a three-valued low-power dissipation domino JKL trigger; and the three-valued thermal-insulation domino direct circulation valve and the three-valued thermal-insulation domino reverse circulation valve have the advantages of being high in circuit integration and information density and low in power dissipation on the basis of the three-valued low-power dissipation domino JKL trigger.

Description

A kind of tri-valued, thermal-insulating domino direct circulation door and anti-circulation door

Technical field

The present invention relates to the circulation door, especially relate to a kind of tri-valued, thermal-insulating domino direct circulation door and anti-circulation door.

Background technology

Along with the continuous progress of semiconductor technology, the needed area ratio of wiring is increasing on the silicon chip, thereby has limited the further raising of integrated level and information density.Adopt multi valued logic can improve the amount of information that every connecting line carries, greatly reduce the quantity of connecting line in the circuit, thereby reduce the area of chip, strengthen data-handling capacity.The good characteristic that domino circuit is fast with its speed, area is little is widely used in therefore multi valued logic being combined with domino circuit and can improving to a greater extent circuit level and information density in the high-speed computation circuit and critical path in processor, register, the buffer.

Positive and negative circulation gate circuit is one of basic module of valued counter, can finish the function that increases progressively, subtracts counting to clock pulse, is widely used in frequency divider, encoder, memory and the arithmetic circuity.The power consumption of positive and negative circulation gate circuit is determining the power consumption of whole multivalued circuit to a great extent, so the research of the positive and negative circulation gate circuit of low-power consumption is extremely important.

Summary of the invention

First technical problem to be solved by this invention provides and is a kind ofly guaranteeing to have under the prerequisite of correct logic function the tri-valued, thermal-insulating domino direct circulation door that power consumption is lower.

The present invention solves the technical scheme that first technical problem adopts: a kind of tri-valued, thermal-insulating domino direct circulation door, it is characterized in that being formed by three value low-power consumption domino JKL triggers, described three value low-power consumption domino JKL triggers are by the first tri-valued, thermal-insulating domino literal computing circuit, the second tri-valued, thermal-insulating domino literal computing circuit, the 3rd tri-valued, thermal-insulating domino literal computing circuit, the 4th tri-valued, thermal-insulating domino literal computing circuit, three value JKL trigger basic circuits and adiabatic domino buffer form, described the first tri-valued, thermal-insulating domino literal computing circuit, described the second tri-valued, thermal-insulating domino literal computing circuit, described the 3rd tri-valued, thermal-insulating domino literal computing circuit and described the 4th tri-valued, thermal-insulating domino literal computing circuit are provided with the first clock signal input terminal and second clock signal input part, described three value JKL trigger basic circuits are provided with the first clock signal input terminal, the second clock signal input part, the 3rd clock signal input terminal, the first signal input, the secondary signal input, the 3rd signal input part and the 4th signal input part, the signal output part of described the first tri-valued, thermal-insulating domino literal computing circuit is connected with the first signal input of described three value JKL trigger basic circuits, the signal output part of described the second tri-valued, thermal-insulating domino literal computing circuit is connected with the secondary signal input of described three value JKL trigger basic circuits, the signal output part of described the 3rd tri-valued, thermal-insulating domino literal computing circuit is connected with the 3rd signal input part of described three value JKL trigger basic circuits, the signal output part of described the 4th tri-valued, thermal-insulating domino literal computing circuit is connected with the 4th signal input part of described three value JKL trigger basic circuits, the signal output part of described three value JKL trigger basic circuits is connected with the signal input part of described adiabatic domino buffer, the signal output part of described adiabatic domino buffer is connected with the signal input part of described the 4th tri-valued, thermal-insulating domino literal computing circuit, the first clock signal input terminal of described the first tri-valued, thermal-insulating domino literal computing circuit, the first clock signal input terminal of described the second tri-valued, thermal-insulating domino literal computing circuit, the first clock signal input terminal of described the 3rd tri-valued, thermal-insulating domino literal computing circuit, the first clock signal input terminal of the first clock signal input terminal of described the 4th tri-valued, thermal-insulating domino literal computing circuit and described three value JKL trigger basic circuits and connect and itself and connect the end be the first clock signal input terminal of three value low-power consumption domino JKL triggers, the second clock signal input part of described the first tri-valued, thermal-insulating domino literal computing circuit, the second clock signal input part of described the second tri-valued, thermal-insulating domino literal computing circuit, the second clock signal input part of described the 3rd tri-valued, thermal-insulating domino literal computing circuit, the second clock signal input part of the second clock signal input part of described the 4th tri-valued, thermal-insulating domino literal computing circuit and described three value JKL trigger basic circuits and connect and itself and connect the end be the second clock signal input part of three value low-power consumption domino JKL triggers, the 3rd clock signal input terminal of described three value JKL trigger basic circuits is the 3rd clock signal input terminal of three value low-power consumption domino JKL triggers, this three values low-power consumption domino JKL trigger also is provided with the 4th clock signal input terminal, described the first clock signal input terminal access amplitude level is the first clock signal of 2, described second clock signal input part access amplitude level is 2 second clock signal, described the 3rd clock signal input terminal access amplitude level is 1 the 3rd clock signal, described the 4th clock signal input terminal access amplitude level is 1 the 4th clock signal, described the first clock signal is identical with described the 4th clock signal phase, described second clock signal is identical with described the 3rd clock signal phase, described the first clock signal and described second clock signal phase differ 180 degree, the signal input part of described the first tri-valued, thermal-insulating domino literal computing circuit, the signal input part of described the second tri-valued, thermal-insulating domino literal computing circuit, the signal input part of described the 3rd tri-valued, thermal-insulating domino literal computing circuit be connected the 4th clock signal input terminal and connect.

Described the first tri-valued, thermal-insulating domino literal computing circuit comprises literal computing module and waveform transformation module, described literal computing module is managed by a PMOS, the 2nd PMOS pipe, the 3rd PMOS pipe, the 4th PMOS pipe, the 5th PMOS pipe, the 6th PMOS pipe, the one NMOS pipe, the 2nd NMOS pipe, the 3rd NMOS pipe, the 4th NMOS pipe, the 5th NMOS pipe, the 6th NMOS pipe and the 7th NMOS pipe form, the grid of the grid of a described NMOS pipe and described the 4th NMOS pipe and connect and itself and connect end for signal input part, the drain electrode of a described NMOS pipe, the grid of the source electrode of a described PMOS pipe and described the 3rd PMOS pipe also connects, the source electrode of a described NMOS pipe is connected with the drain electrode of described the 2nd NMOS pipe, the source electrode of described the 2nd PMOS pipe is connected with the drain electrode of described the 3rd PMOS pipe, the source electrode of described the 3rd PMOS pipe, the drain electrode of the drain electrode of described the 3rd NMOS pipe and described the 7th NMOS pipe also connects, the source electrode of described the 4th PMOS pipe, the drain electrode of described the 4th NMOS pipe, the grid of the grid of described the 6th PMOS pipe and described the 7th NMOS pipe also connects, the source electrode of described the 4th NMOS pipe is connected with the drain electrode of described the 5th NMOS pipe, the source electrode of described the 5th PMOS pipe is connected with the drain electrode of described the 6th PMOS pipe, the drain electrode of the source electrode of described the 6th PMOS pipe and described the 6th NMOS pipe also connects, the grid of a described PMOS pipe, the drain electrode of described the 2nd PMOS pipe, the grid of described the 4th PMOS pipe, the drain electrode of described the 5th PMOS pipe, the grid of described the 2nd NMOS pipe, the source electrode of described the 3rd NMOS pipe, the source electrode of the grid of described the 5th NMOS pipe and described the 6th NMOS pipe is connected to the first clock signal input terminal, the drain electrode of a described PMOS pipe, the grid of described the 2nd PMOS pipe, the drain electrode of described the 4th PMOS pipe, the grid of described the 5th PMOS pipe, the source electrode of described the 2nd NMOS pipe, the grid of described the 3rd NMOS pipe, the grid of the source electrode of described the 5th NMOS pipe and described the 6th NMOS pipe is connected to the second clock signal input part, described waveform transformation module is managed by the 8th NMOS, the 9th NMOS pipe, the tenth NMOS pipe, the 11 NMOS pipe, the 12 NMOS pipe and the 13 NMOS pipe form, the drain electrode of described the 8th NMOS pipe is connected with the drain electrode of a described NMOS pipe, the source electrode of described the 8th NMOS pipe is connected with the grid of described the 9th NMOS pipe, the drain electrode of described the tenth NMOS pipe is connected with the source electrode of described the 7th NMOS pipe, the source electrode of described the tenth NMOS pipe is connected with the grid of described the 11 NMOS pipe, the drain electrode of described the 12 NMOS pipe is connected with the source electrode of described the 6th PMOS pipe, the source electrode of described the 12 NMOS pipe is connected with the grid of described the 13 NMOS pipe, the grid of described the 8th NMOS pipe, the grid of described the tenth NMOS pipe and the grid of described the 12 NMOS pipe are connected to the first clock signal input terminal, the source electrode of described the 9th NMOS pipe, the source electrode of described the 11 NMOS pipe and the source electrode of described the 13 NMOS pipe are connected to the second clock signal input part, the drain electrode of described the 9th NMOS pipe is the first signal output, the drain electrode of described the 11 NMOS pipe is the secondary signal output, the drain electrode of described the 13 NMOS pipe is the 3rd signal output part, the circuit structure of described the second tri-valued, thermal-insulating domino literal computing circuit, the circuit structure of described the 3rd tri-valued, thermal-insulating domino literal computing circuit, the circuit structure of described the 4th tri-valued, thermal-insulating domino literal computing circuit is all identical with described the first tri-valued, thermal-insulating domino literal computing circuit.

Described three value JKL trigger basic circuits comprise that the first control signal produces circuit, the second control signal produces circuit and next state signal generating circuit, described the first control signal produces circuit and is managed by the 7th PMOS, the 14 NMOS pipe, the 15 NMOS pipe, the 16 NMOS pipe, the 17 NMOS pipe, the 18 NMOS pipe, the 19 NMOS pipe and the 20 NMOS pipe form, the source electrode of described the 7th PMOS pipe, the drain electrode of described the 14 NMOS pipe, the drain electrode of described the 16 NMOS pipe and the drain electrode of described the 18 NMOS pipe and connect and itself and connect the end be the first control signal output, the source electrode of described the 14 NMOS pipe is connected with the drain electrode of described the 15 NMOS pipe, the source electrode of described the 16 NMOS pipe is connected with the drain electrode of described the 17 NMOS pipe, the source electrode of described the 18 NMOS pipe is connected with the drain electrode of described the 19 NMOS pipe, the source electrode of described the 15 NMOS pipe, the source electrode of described the 17 NMOS pipe, the source electrode of described the 19 NMOS pipe be connected the drain electrode of the 20 NMOS pipe and connect, described the second control signal produces circuit and is managed by the 8th PMOS, the 21 NMOS pipe, the 22 NMOS pipe, the 23 NMOS pipe, the 24 NMOS pipe, the 25 NMOS pipe, the 26 NMOS pipe and the 27 NMOS pipe form, the source electrode of described the 8th PMOS pipe, the drain electrode of described the 21 NMOS pipe, the drain electrode of described the 23 NMOS pipe and the drain electrode of described the 25 NMOS pipe and connect and itself and connect the end be the second control signal output, the source electrode of described the 21 NMOS pipe is connected with the drain electrode of described the 22 NMOS pipe, the source electrode of described the 23 NMOS pipe is connected with the drain electrode of described the 24 NMOS pipe, the source electrode of described the 25 NMOS pipe is connected with the drain electrode of described the 26 NMOS pipe, the source electrode of described the 22 NMOS pipe, the source electrode of described the 24 NMOS pipe, the source electrode of described the 26 NMOS pipe be connected the drain electrode of the 27 NMOS pipe and connect, described next state signal generating circuit is managed by the 9th PMOS, the tenth PMOS pipe and the 28 NMOS pipe form, the grid of described the 9th PMOS pipe is connected with described the first control signal output, the grid of described the tenth PMOS pipe is connected with described the second control signal output, the source electrode of described the 9th PMOS pipe, the drain electrode of the source electrode of described the tenth PMOS pipe and described the 28 NMOS pipe and connect and itself and connect end for signal output part, the grid of described the 14 NMOS pipe is connected with the secondary signal output of described the first tri-valued, thermal-insulating domino literal computing circuit, the grid of the 15 NMOS pipe be connected the grid of the 22 NMOS pipe and all be connected with the first signal output of described the 4th tri-valued, thermal-insulating domino literal computing circuit, the grid of described the 16 NMOS pipe is connected with the first signal output of described the second tri-valued, thermal-insulating domino literal computing circuit, the grid of described the 17 NMOS pipe be connected the grid of the 24 NMOS pipe and all be connected with the secondary signal output of described the 4th tri-valued, thermal-insulating domino literal computing circuit, the grid of described the 18 NMOS pipe is connected with the 3rd signal output part of described the 3rd tri-valued, thermal-insulating domino literal computing circuit, the grid of described the 19 NMOS pipe be connected the grid of the 26 NMOS pipe and all be connected with the 3rd signal output part of described the 4th tri-valued, thermal-insulating domino literal computing circuit, the grid of described the 21 NMOS pipe is connected with the 3rd signal output part of described the first tri-valued, thermal-insulating domino literal computing circuit, the grid of described the 23 NMOS pipe is connected with the secondary signal output of described the second tri-valued, thermal-insulating domino literal computing circuit, the grid of described the 25 NMOS pipe is connected with the first signal output of described the 3rd tri-valued, thermal-insulating domino literal computing circuit, the drain electrode of described the 7th PMOS pipe, the drain electrode of described the 8th PMOS pipe, the source electrode of described the 20 NMOS pipe, the source electrode of described the 27 NMOS pipe and the grid of described the 28 NMOS pipe are connected to the first clock signal input terminal, the grid of described the 7th PMOS pipe, the grid of described the 8th PMOS pipe, the drain electrode of described the tenth PMOS pipe, the grid of described the 20 NMOS pipe, the grid of described the 27 NMOS pipe and described the 28 NMOS pipe source electrode are connected to the second clock signal input part, and the drain electrode of described the 9th PMOS pipe is the 3rd clock signal input terminal.

Described adiabatic domino buffer is managed by the 11 PMOS, the 12 PMOS pipe, the 13 PMOS pipe, the 14 PMOS pipe, the 15 PMOS pipe, the 16 PMOS pipe, the 29 NMOS pipe, the 30 NMOS pipe, the 31 NMOS pipe, the 32 NMOS pipe, the 33 NMOS pipe, the 34 NMOS pipe, the 35 NMOS pipe, the 36 NMOS pipe, the 37 NMOS pipe, the 38 NMOS pipe and the 39 NMOS pipe form, the source electrode of described the 11 PMOS pipe, the grid of described the 13 PMOS pipe be connected the drain electrode of the 29 NMOS pipe and connect, the source electrode of described the 29 NMOS pipe be connected the drain electrode of the 30 NMOS pipe and connect, the source electrode of described the 12 PMOS pipe be connected the drain electrode of the 13 PMOS pipe and connect, the source electrode of described the 13 PMOS pipe, the drain electrode of described the 31 NMOS pipe be connected the drain electrode of the 35 NMOS pipe and connect, the source electrode of described the 14 PMOS pipe, the grid of described the 16 PMOS pipe, the drain electrode of described the 32 NMOS pipe be connected the grid of the 35 NMOS pipe and connect, the source electrode of described the 32 NMOS pipe be connected the drain electrode of the 33 NMOS pipe and connect, the source electrode of described the 15 PMOS pipe be connected the drain electrode of the 16 PMOS pipe and connect, the drain electrode of described the 16 PMOS pipe, the drain electrode of described the 34 NMOS pipe be connected the drain electrode of the 38 NMOS pipe and connect, the drain electrode of described the 35 NMOS pipe be connected the drain electrode of the 36 NMOS pipe and connect, the source electrode of described the 36 NMOS pipe be connected the grid of the 37 NMOS pipe and connect, the source electrode of described the 38 NMOS pipe be connected the grid of the 39 NMOS pipe and connect, the grid of the grid of described the 29 NMOS pipe and described the 32 NMOS pipe and connect and itself and connect end for signal input part, the drain electrode of the drain electrode of described the 37 NMOS pipe and described the 39 NMOS pipe and connect and itself and connect end for signal output part, the drain electrode of described the 11 PMOS pipe, the grid of described the 12 PMOS pipe, the drain electrode of described the 14 PMOS pipe, the grid of described the 15 PMOS pipe, the source electrode of described the 30 NMOS pipe, the grid of described the 31 NMOS pipe, the source electrode of described the 33 NMOS pipe, the grid of described the 34 NMOS pipe and the source electrode of described the 39 NMOS pipe and connect and itself and connect the end be the first clock signal input terminal, the grid of described the 11 PMOS pipe, the drain electrode of described the 12 PMOS pipe, the grid of described the 14 PMOS pipe, the drain electrode of described the 15 PMOS pipe, the grid of described the 30 NMOS pipe, the source electrode of described the 31 NMOS pipe, the grid of described the 33 NMOS pipe, the source electrode of described the 34 NMOS pipe, the grid of the grid of described the 36 NMOS pipe and described the 38 NMOS pipe and connect and itself and connect end for the second clock signal input part, the source electrode of described the 37 NMOS pipe is the 3rd clock signal input terminal, the output signal of described adiabatic domino buffer is identical with its input signal, and its input signal of the output signal ratio of described adiabatic domino buffer postpones the clock cycle half, the first clock signal input terminal of described adiabatic domino buffer is connected with the first clock signal input terminal of described the first tri-valued, thermal-insulating domino literal computing circuit, the second clock signal input part of described adiabatic domino buffer is connected with the second clock signal input part of described the first tri-valued, thermal-insulating domino literal computing circuit, and the 3rd clock signal input terminal of described adiabatic domino buffer is connected with described the 4th clock signal input terminal.

Second technical problem to be solved by this invention provides and a kind ofly guaranteeing to have under the prerequisite of correct logic function the anti-door that circulates of the tri-valued, thermal-insulating domino that power consumption is lower.

The present invention solves the technical scheme that second technical problem adopt: the anti-door that circulates of a kind of tri-valued, thermal-insulating domino, formed by three value low-power consumption domino JKL triggers, described three value low-power consumption domino JKL triggers are by the first tri-valued, thermal-insulating domino literal computing circuit, the second tri-valued, thermal-insulating domino literal computing circuit, the 3rd tri-valued, thermal-insulating domino literal computing circuit, the 4th tri-valued, thermal-insulating domino literal computing circuit and three value JKL trigger basic circuits form, described the first tri-valued, thermal-insulating domino literal computing circuit, described the second tri-valued, thermal-insulating domino literal computing circuit, described the 3rd tri-valued, thermal-insulating domino literal computing circuit and described the 4th tri-valued, thermal-insulating domino literal computing circuit are provided with the first clock signal input terminal and second clock signal input part, described three value JKL trigger basic circuits are provided with the first clock signal input terminal, the second clock signal input part, the 3rd clock signal input terminal, the 4th signal input part, the first signal input, secondary signal input and the 3rd signal input part, the signal output part of described the first tri-valued, thermal-insulating domino literal computing circuit is connected with the first signal input of described three value JKL trigger basic circuits, the signal output part of described the second tri-valued, thermal-insulating domino literal computing circuit is connected with the secondary signal input of described three value JKL trigger basic circuits, the signal output part of described the 3rd tri-valued, thermal-insulating domino literal computing circuit is connected with the 3rd signal input part of described three value JKL trigger basic circuits, the signal output part of described the 4th tri-valued, thermal-insulating domino literal computing circuit is connected with the 4th signal input part of described three value JKL trigger basic circuits, the signal output part of described three value JKL trigger basic circuits is connected by an adiabatic domino buffer with the signal input part of described the 4th tri-valued, thermal-insulating domino literal computing circuit, the first clock signal input terminal of described the first tri-valued, thermal-insulating domino literal computing circuit, the first clock signal input terminal of described the second tri-valued, thermal-insulating domino literal computing circuit, the first clock signal input terminal of described the 3rd tri-valued, thermal-insulating domino literal computing circuit, the first clock signal input terminal of the first clock signal input terminal of described the 4th tri-valued, thermal-insulating domino literal computing circuit and described three value JKL trigger basic circuits and connect and itself and connect the end be the first clock signal input terminal of three value low-power consumption domino JKL triggers, the second clock signal input part of described the first tri-valued, thermal-insulating domino literal computing circuit, the second clock signal input part of described the second tri-valued, thermal-insulating domino literal computing circuit, the second clock signal input part of described the 3rd tri-valued, thermal-insulating domino literal computing circuit, the second clock signal input part of the second clock signal input part of described the 4th tri-valued, thermal-insulating domino literal computing circuit and described three value JKL trigger basic circuits and connect and itself and connect the end be the second clock signal input part of three value low-power consumption domino JKL triggers, the 3rd clock signal input terminal of described three value JKL trigger basic circuits is the 3rd clock signal input terminal of three value low-power consumption domino JKL triggers, this three values low-power consumption domino JKL trigger also is provided with the 4th clock signal input terminal, described the first clock signal input terminal access amplitude level is the first clock signal of 2, described second clock signal input part access amplitude level is 2 second clock signal, described the 3rd clock signal input terminal access amplitude level is 1 the 3rd clock signal, described the 4th clock signal input terminal access amplitude level is 1 the 4th clock signal, described the first clock signal is identical with described the 4th clock signal phase, described second clock signal is identical with described the 3rd clock signal phase, described the first clock signal and described second clock signal phase differ 180 degree, the signal input part of described the first tri-valued, thermal-insulating domino literal computing circuit, the signal input part of described the second tri-valued, thermal-insulating domino literal computing circuit, the signal input part of described the 3rd tri-valued, thermal-insulating domino literal computing circuit be connected the first clock signal input terminal and connect.

Described the first tri-valued, thermal-insulating domino literal computing circuit comprises literal computing module and waveform transformation module, described literal computing module is managed by a PMOS, the 2nd PMOS pipe, the 3rd PMOS pipe, the 4th PMOS pipe, the 5th PMOS pipe, the 6th PMOS pipe, the one NMOS pipe, the 2nd NMOS pipe, the 3rd NMOS pipe, the 4th NMOS pipe, the 5th NMOS pipe, the 6th NMOS pipe and the 7th NMOS pipe form, the grid of the grid of a described NMOS pipe and described the 4th NMOS pipe and connect and itself and connect end for signal input part, the drain electrode of a described NMOS pipe, the grid of the source electrode of a described PMOS pipe and described the 3rd PMOS pipe also connects, the source electrode of a described NMOS pipe is connected with the drain electrode of described the 2nd NMOS pipe, the source electrode of described the 2nd PMOS pipe is connected with the drain electrode of described the 3rd PMOS pipe, the source electrode of described the 3rd PMOS pipe, the drain electrode of the drain electrode of described the 3rd NMOS pipe and described the 7th NMOS pipe also connects, the source electrode of described the 4th PMOS pipe, the drain electrode of described the 4th NMOS pipe, the grid of the grid of described the 6th PMOS pipe and described the 7th NMOS pipe also connects, the source electrode of described the 4th NMOS pipe is connected with the drain electrode of described the 5th NMOS pipe, the source electrode of described the 5th PMOS pipe is connected with the drain electrode of described the 6th PMOS pipe, the drain electrode of the source electrode of described the 6th PMOS pipe and described the 6th NMOS pipe also connects, the grid of a described PMOS pipe, the drain electrode of described the 2nd PMOS pipe, the grid of described the 4th PMOS pipe, the drain electrode of described the 5th PMOS pipe, the grid of described the 2nd NMOS pipe, the source electrode of described the 3rd NMOS pipe, the source electrode of the grid of described the 5th NMOS pipe and described the 6th NMOS pipe is connected to the first clock signal input terminal, the drain electrode of a described PMOS pipe, the grid of described the 2nd PMOS pipe, the drain electrode of described the 4th PMOS pipe, the grid of described the 5th PMOS pipe, the source electrode of described the 2nd NMOS pipe, the grid of described the 3rd NMOS pipe, the grid of the source electrode of described the 5th NMOS pipe and described the 6th NMOS pipe is connected to the second clock signal input part, described waveform transformation module is managed by the 8th NMOS, the 9th NMOS pipe, the tenth NMOS pipe, the 11 NMOS pipe, the 12 NMOS pipe and the 13 NMOS pipe form, the drain electrode of described the 8th NMOS pipe is connected with the drain electrode of a described NMOS pipe, the source electrode of described the 8th NMOS pipe is connected with the grid of described the 9th NMOS pipe, the drain electrode of described the tenth NMOS pipe is connected with the source electrode of described the 7th NMOS pipe, the source electrode of described the tenth NMOS pipe is connected with the grid of described the 11 NMOS pipe, the drain electrode of described the 12 NMOS pipe is connected with the source electrode of described the 6th PMOS pipe, the source electrode of described the 12 NMOS pipe is connected with the grid of described the 13 NMOS pipe, the grid of described the 8th NMOS pipe, the grid of described the tenth NMOS pipe and the grid of described the 12 NMOS pipe are connected to the first clock signal input terminal, the source electrode of described the 9th NMOS pipe, the source electrode of described the 11 NMOS pipe and the source electrode of described the 13 NMOS pipe are connected to the second clock signal input part, the drain electrode of described the 9th NMOS pipe is the first signal output, the drain electrode of described the 11 NMOS pipe is the secondary signal output, the drain electrode of described the 13 NMOS pipe is the 3rd signal output part, the circuit structure of described the second tri-valued, thermal-insulating domino literal computing circuit, the circuit structure of described the 3rd tri-valued, thermal-insulating domino literal computing circuit, the circuit structure of described the 4th tri-valued, thermal-insulating domino literal computing circuit is all identical with described the first tri-valued, thermal-insulating domino literal computing circuit.

Described three value JKL trigger basic circuits comprise that the first control signal produces circuit, the second control signal produces circuit and next state signal generating circuit, described the first control signal produces circuit and is managed by the 7th PMOS, the 14 NMOS pipe, the 15 NMOS pipe, the 16 NMOS pipe, the 17 NMOS pipe, the 18 NMOS pipe, the 19 NMOS pipe and the 20 NMOS pipe form, the source electrode of described the 7th PMOS pipe, the drain electrode of described the 14 NMOS pipe, the drain electrode of described the 16 NMOS pipe and the drain electrode of described the 18 NMOS pipe and connect and itself and connect the end be the first control signal output, the source electrode of described the 14 NMOS pipe is connected with the drain electrode of described the 15 NMOS pipe, the source electrode of described the 16 NMOS pipe is connected with the drain electrode of described the 17 NMOS pipe, the source electrode of described the 18 NMOS pipe is connected with the drain electrode of described the 19 NMOS pipe, the source electrode of described the 15 NMOS pipe, the source electrode of described the 17 NMOS pipe, the source electrode of described the 19 NMOS pipe be connected the drain electrode of the 20 NMOS pipe and connect, described the second control signal produces circuit and is managed by the 8th PMOS, the 21 NMOS pipe, the 22 NMOS pipe, the 23 NMOS pipe, the 24 NMOS pipe, the 25 NMOS pipe, the 26 NMOS pipe and the 27 NMOS pipe form, the source electrode of described the 8th PMOS pipe, the drain electrode of described the 21 NMOS pipe, the drain electrode of described the 23 NMOS pipe and the drain electrode of described the 25 NMOS pipe and connect and itself and connect the end be the second control signal output, the source electrode of described the 21 NMOS pipe is connected with the drain electrode of described the 22 NMOS pipe, the source electrode of described the 23 NMOS pipe is connected with the drain electrode of described the 24 NMOS pipe, the source electrode of described the 25 NMOS pipe is connected with the drain electrode of described the 26 NMOS pipe, the source electrode of described the 22 NMOS pipe, the source electrode of described the 24 NMOS pipe, the source electrode of described the 26 NMOS pipe be connected the drain electrode of the 27 NMOS pipe and connect, described next state signal generating circuit is managed by the 9th PMOS, the tenth PMOS pipe and the 28 NMOS pipe form, the grid of described the 9th PMOS pipe is connected with described the first control signal output, the grid of described the tenth PMOS pipe is connected with described the second control signal output, the source electrode of described the 9th PMOS pipe, the drain electrode of the source electrode of described the tenth PMOS pipe and described the 28 NMOS pipe and connect and itself and connect end for signal output part, the grid of described the 14 NMOS pipe is connected with the secondary signal output of described the first tri-valued, thermal-insulating domino literal computing circuit, the grid of the 15 NMOS pipe be connected the grid of the 22 NMOS pipe and all be connected with the first signal output of described the 4th tri-valued, thermal-insulating domino literal computing circuit, the grid of described the 16 NMOS pipe is connected with the first signal output of described the second tri-valued, thermal-insulating domino literal computing circuit, the grid of described the 17 NMOS pipe be connected the grid of the 24 NMOS pipe and all be connected with the secondary signal output of described the 4th tri-valued, thermal-insulating domino literal computing circuit, the grid of described the 18 NMOS pipe is connected with the 3rd signal output part of described the 3rd tri-valued, thermal-insulating domino literal computing circuit, the grid of described the 19 NMOS pipe be connected the grid of the 26 NMOS pipe and all be connected with the 3rd signal output part of described the 4th tri-valued, thermal-insulating domino literal computing circuit, the grid of described the 21 NMOS pipe is connected with the 3rd signal output part of described the first tri-valued, thermal-insulating domino literal computing circuit, the grid of described the 23 NMOS pipe is connected with the secondary signal output of described the second tri-valued, thermal-insulating domino literal computing circuit, the grid of described the 25 NMOS pipe is connected with the first signal output of described the 3rd tri-valued, thermal-insulating domino literal computing circuit, the drain electrode of described the 7th PMOS pipe, the drain electrode of described the 8th PMOS pipe, the source electrode of described the 20 NMOS pipe, the source electrode of described the 27 NMOS pipe and the grid of described the 28 NMOS pipe are connected to the first clock signal input terminal, the grid of described the 7th PMOS pipe, the grid of described the 8th PMOS pipe, the drain electrode of described the tenth PMOS pipe, the grid of described the 20 NMOS pipe, the grid of described the 27 NMOS pipe and described the 28 NMOS pipe source electrode are connected to the second clock signal input part, and the drain electrode of described the 9th PMOS pipe is the 3rd clock signal input terminal.

Described adiabatic domino buffer is managed by the 11 PMOS, the 12 PMOS pipe, the 13 PMOS pipe, the 14 PMOS pipe, the 15 PMOS pipe, the 16 PMOS pipe, the 29 NMOS pipe, the 30 NMOS pipe, the 31 NMOS pipe, the 32 NMOS pipe, the 33 NMOS pipe, the 34 NMOS pipe, the 35 NMOS pipe, the 36 NMOS pipe, the 37 NMOS pipe, the 38 NMOS pipe and the 39 NMOS pipe form, the source electrode of described the 11 PMOS pipe, the grid of described the 13 PMOS pipe be connected the drain electrode of the 29 NMOS pipe and connect, the source electrode of described the 29 NMOS pipe be connected the drain electrode of the 30 NMOS pipe and connect, the source electrode of described the 12 PMOS pipe be connected the drain electrode of the 13 PMOS pipe and connect, the source electrode of described the 13 PMOS pipe, the drain electrode of described the 31 NMOS pipe be connected the drain electrode of the 35 NMOS pipe and connect, the source electrode of described the 14 PMOS pipe, the grid of described the 16 PMOS pipe, the drain electrode of described the 32 NMOS pipe be connected the grid of the 35 NMOS pipe and connect, the source electrode of described the 32 NMOS pipe be connected the drain electrode of the 33 NMOS pipe and connect, the source electrode of described the 15 PMOS pipe be connected the drain electrode of the 16 PMOS pipe and connect, the drain electrode of described the 16 PMOS pipe, the drain electrode of described the 34 NMOS pipe be connected the drain electrode of the 38 NMOS pipe and connect, the drain electrode of described the 35 NMOS pipe be connected the drain electrode of the 36 NMOS pipe and connect, the source electrode of described the 36 NMOS pipe be connected the grid of the 37 NMOS pipe and connect, the source electrode of described the 38 NMOS pipe be connected the grid of the 39 NMOS pipe and connect, the grid of the grid of described the 29 NMOS pipe and described the 32 NMOS pipe and connect and itself and connect end for signal input part, the drain electrode of the drain electrode of described the 37 NMOS pipe and described the 39 NMOS pipe and connect and itself and connect end for signal output part, the drain electrode of described the 11 PMOS pipe, the grid of described the 12 PMOS pipe, the drain electrode of described the 14 PMOS pipe, the grid of described the 15 PMOS pipe, the source electrode of described the 30 NMOS pipe, the grid of described the 31 NMOS pipe, the source electrode of described the 33 NMOS pipe, the grid of described the 34 NMOS pipe and the source electrode of described the 39 NMOS pipe and connect and itself and connect the end be the first clock signal input terminal, the grid of described the 11 PMOS pipe, the drain electrode of described the 12 PMOS pipe, the grid of described the 14 PMOS pipe, the drain electrode of described the 15 PMOS pipe, the grid of described the 30 NMOS pipe, the source electrode of described the 31 NMOS pipe, the grid of described the 33 NMOS pipe, the source electrode of described the 34 NMOS pipe, the grid of the grid of described the 36 NMOS pipe and described the 38 NMOS pipe and connect and itself and connect end for the second clock signal input part, the source electrode of described the 37 NMOS pipe is the 3rd clock signal input terminal, the output signal of described adiabatic domino buffer is identical with its input signal, and its input signal of the output signal ratio of described adiabatic domino buffer postpones the clock cycle half, the first clock signal input terminal of described adiabatic domino buffer is connected with the first clock signal input terminal of described the first tri-valued, thermal-insulating domino literal computing circuit, the second clock signal input part of described adiabatic domino buffer is connected with the second clock signal input part of described the first tri-valued, thermal-insulating domino literal computing circuit, and the 3rd clock signal input terminal of described adiabatic domino buffer is connected with described the 4th clock signal input terminal.

Compared with prior art, the invention has the advantages that by design by the first tri-valued, thermal-insulating domino literal computing circuit, the second tri-valued, thermal-insulating domino literal computing circuit, the 3rd tri-valued, thermal-insulating domino literal computing circuit, the three value low-power consumption domino JKL triggers that the 4th tri-valued, thermal-insulating domino literal computing circuit and three value JKL trigger basic circuits form are realized tri-valued, thermal-insulating domino direct circulation door and anti-circulation door, with adiabatic logic, multi valued logic and domino circuit are applied in the design of JKL trigger, circuit level and the information density of JKL trigger have been improved, compare with conventional three value domino JKL triggers, energy consumption saves approximately 69%, thereby obtain circuit level and information density is higher, the tri-valued, thermal-insulating domino direct circulation door that power consumption is lower and anti-circulation door.

Description of drawings

Fig. 1 is the circuit theory diagrams of tri-valued, thermal-insulating domino direct circulation door of the present invention;

Fig. 2 (a) is the circuit diagram of three value low-power consumption domino JKL triggers of the present invention;

Fig. 2 (b) is the circuit symbol figure of three value low-power consumption domino JKL triggers of the present invention;

Fig. 3 (a) is the circuit diagram of the literal computing module of the first tri-valued, thermal-insulating domino literal computing circuit of the present invention;

Fig. 3 (b) is the waveform transformation module circuit diagram of the first tri-valued, thermal-insulating domino literal computing circuit of the present invention;

Fig. 3 (c) is the circuit symbol figure of the first tri-valued, thermal-insulating domino literal computing circuit of the present invention;

Fig. 4 (a) is the circuit diagram that the first control signal produces circuit in the three value JKL trigger basic circuits of the present invention;

Fig. 4 (b) is the circuit diagram that the second control signal produces circuit in the three value JKL trigger basic circuits of the present invention;

Fig. 4 (c) is the circuit diagram that the next state control signal produces circuit in the three value JKL trigger basic circuits of the present invention;

Fig. 4 (d) is the circuit symbol figure of three value JKL trigger basic circuits of the present invention;

Fig. 5 is the clock signal oscillogram;

Fig. 6 (a) is the circuit diagram of adiabatic domino buffer;

Fig. 6 (b) is the graphical diagram of adiabatic domino buffer;

Fig. 7 is the circuit theory diagrams of tri-valued, thermal-insulating domino direct circulation door of the present invention;

Fig. 8 is the analog waveform figure of the three value low-power consumption domino JKL triggers of tri-valued, thermal-insulating domino direct circulation door embodiment;

Fig. 9 be three value low-power consumption domino JKL of the present invention trigger with the power consumption comparison diagram conventional domino JKL trigger of three values.

Embodiment

Embodiment is described in further detail the present invention below in conjunction with accompanying drawing.

Design principle of the present invention is: three value JKL trigger truth tables are as shown in table 1, wherein J, K, LBe input signal, QWith Q' be respectively the existing attitude of trigger and next state, dFor arbitrary value and d∈ { 0,1,2}.By truth table as can be known, the next state of trigger Q' depend on input signal J, K, LWith existing attitude Q, so trigger is the sharp type circuit of typical rice, now attitude QNeed through behind the buffer circuits as the input signal of next working stage.

Table 1 three value JKL trigger truth tables

Owing to generally only having NMOS pipe or PMOS pipe in the evaluation circuit of domino circuit, can't directly differentiate the logical one signal, so the input signal of three value JKL triggers at first will pass through tri-valued, thermal-insulating domino literal computing circuit.If input signal J, K, LAnd the existing attitude of trigger QThrough the output signal behind the tri-valued, thermal-insulating domino literal computing circuit be ⁰ J ⁰, ¹ J ¹, ² J ², ⁰ K ⁰, ¹ K ¹, ² K ², ⁰ L ⁰, ¹ L ¹, ² L ², ⁰ Q ⁰, ¹ Q ¹, ² Q ², the first clock signal Clk, the second clock signal

Amplitude level counterlogic 2, the three clock signals Amplitude level counterlogic 1, the second clock signal

With the 3rd clock signal

Homophase, the first clock signal ClkWith the above two anti-phase (being phase phasic difference 180 degree), according to the truth table of switch-signal theory and three value JKL triggers, can deriving the circuit structure formula of three value JKL trigger basic circuits, thereby obtain three value low-power consumption domino JKL triggers.

Three value direct circulation operator definitions are in the Post algebraically:

X ^→=( X+1). mod 3

Wherein X, X ^→Be respectively the input and output of direct circulation door.Table 2 has provided three value direct circulation door truth tables, by contrasting as can be known with three value JKL trigger truth tables, when the input of three value JKL triggers J= K= L=1 o'clock, both logic functions were identical, therefore can realize with three value low-power consumption domino JKL triggers the design of tri-valued, thermal-insulating domino direct circulation door.

Table 2 three value direct circulation door truth tables

With three value low-power consumption domino JKL triggers J, K, LSignal input part and clock Clk ₁Link to each other, just can obtain tri-valued, thermal-insulating domino direct circulation door, realize clock pulse is increased progressively the function of counting.Together should J, K, LSignal input part and clock ClkWhen linking to each other, can realize the design of the anti-door that circulates of tri-valued, thermal-insulating domino.

Such as Fig. 1, shown in Fig. 2 (a) and Fig. 2 (b), the invention provides a kind of tri-valued, thermal-insulating domino direct circulation door, formed by three value low-power consumption domino JKL triggers, three value low-power consumption domino JKL triggers are by the first tri-valued, thermal-insulating domino literal computing circuit, the second tri-valued, thermal-insulating domino literal computing circuit, the 3rd tri-valued, thermal-insulating domino literal computing circuit, the 4th tri-valued, thermal-insulating domino literal computing circuit, three value JKL trigger basic circuits and adiabatic domino buffer form, the first tri-valued, thermal-insulating domino literal computing circuit, the second tri-valued, thermal-insulating domino literal computing circuit, the 3rd tri-valued, thermal-insulating domino literal computing circuit and the 4th tri-valued, thermal-insulating domino literal computing circuit are provided with the first clock signal input terminal and second clock signal input part, three value JKL trigger basic circuits are provided with the first clock signal input terminal, the second clock signal input part, the 3rd clock signal input terminal, the first signal input, the secondary signal input, the 3rd signal input part and the 4th signal input part, the signal output part of the first tri-valued, thermal-insulating domino literal computing circuit is connected with the first signal input of three value JKL trigger basic circuits, the signal output part of the second tri-valued, thermal-insulating domino literal computing circuit is connected with the secondary signal input of three value JKL trigger basic circuits, the signal output part of the 3rd tri-valued, thermal-insulating domino literal computing circuit is connected with the 3rd signal input part of three value JKL trigger basic circuits, the signal output part of the 4th tri-valued, thermal-insulating domino literal computing circuit is connected with the 4th signal input part of three value JKL trigger basic circuits, the signal output part of three value JKL trigger basic circuits is connected with the signal input part of adiabatic domino buffer, the signal output part of adiabatic domino buffer is connected with the signal input part of the 4th tri-valued, thermal-insulating domino literal computing circuit, the first clock signal input terminal of the first tri-valued, thermal-insulating domino literal computing circuit, the first clock signal input terminal of the second tri-valued, thermal-insulating domino literal computing circuit, the first clock signal input terminal of the 3rd tri-valued, thermal-insulating domino literal computing circuit, the first clock signal input terminal of the first clock signal input terminal of the 4th tri-valued, thermal-insulating domino literal computing circuit and described three value JKL trigger basic circuits and connect and itself and connect the end be the first clock signal input terminal of three value low-power consumption domino JKL triggers, the second clock signal input part of the first tri-valued, thermal-insulating domino literal computing circuit, the second clock signal input part of the second tri-valued, thermal-insulating domino literal computing circuit, the second clock signal input part of the 3rd tri-valued, thermal-insulating domino literal computing circuit, the second clock signal input part of the second clock signal input part of the 4th tri-valued, thermal-insulating domino literal computing circuit and three value JKL trigger basic circuits and connect and itself and connect the end be the second clock signal input part of three value low-power consumption domino JKL triggers, the 3rd clock signal input terminal of three value JKL trigger basic circuits is the 3rd clock signal input terminal of three value low-power consumption domino JKL triggers, this three values low-power consumption domino JKL trigger also is provided with the 4th clock signal input terminal, and the first clock signal input terminal access amplitude level is the first clock signal of 2 , second clock signal input part access amplitude level is 2 second clock signal

, the 3rd clock signal input terminal access amplitude level is 1 the 3rd clock signal

, the 4th clock signal input terminal access amplitude level is 1 the 4th clock signal

, the first clock signal With the 4th clock signal

Phase place is identical, the second clock signal

With the 3rd clock signal phase

Identical, the first clock signal

With the second clock signal

Phase phasic difference 180 degree, the signal input part of the signal input part of the first tri-valued, thermal-insulating domino literal computing circuit, the second tri-valued, thermal-insulating domino literal computing circuit, the signal input part of the 3rd tri-valued, thermal-insulating domino literal computing circuit connect with the 4th clock signal input terminal.The first clock signal

, the second clock signal , the 3rd clock signal With the 4th clock signal

Oscillogram as shown in Figure 5.

In the present embodiment, the first tri-valued, thermal-insulating domino literal computing circuit comprises literal computing module and waveform transformation module.Shown in Fig. 3 (a), described literal computing module is by PMOS pipe P1, the 2nd PMOS manages P2, the 3rd PMOS manages P3, the 4th PMOS manages P4, the 5th PMOS manages P5, the 6th PMOS manages P6, the one NMOS manages N1, the 2nd NMOS manages N2, the 3rd NMOS manages N3, the 4th NMOS manages N4, the 5th NMOS manages N5, the 6th NMOS pipe N6 and the 7th NMOS pipe N7 form, the grid of the grid of the one NMOS pipe N1 and the 4th NMOS pipe N4 and connect and itself and connect end and be signal input part, the drain electrode of the one NMOS pipe N1, the grid of the source electrode of the one PMOS pipe P1 and the 3rd PMOS pipe P3 also connects, the source electrode of the one NMOS pipe N1 is connected with the drain electrode of the 2nd NMOS pipe N2, the source electrode of the 2nd PMOS pipe P2 is connected with the drain electrode of the 3rd PMOS pipe P3, the source electrode of the 3rd PMOS pipe P3, the drain electrode of the drain electrode of the 3rd NMOS pipe N3 and the 7th NMOS pipe N7 also connects, the source electrode of the 4th PMOS pipe P4, the drain electrode of the 4th NMOS pipe N4, the grid of the grid of the 6th PMOS pipe P6 and the 7th NMOS pipe N7 also connects, the source electrode of the 4th NMOS pipe N4 is connected with the drain electrode of the 5th NMOS pipe N5, the source electrode of the 5th PMOS pipe P5 is connected with the drain electrode of the 6th PMOS pipe P6, the drain electrode of the source electrode of the 6th PMOS pipe P6 and the 6th NMOS pipe N6 also connects, the grid of the one PMOS pipe P1, the drain electrode of the 2nd PMOS pipe P2, the grid of the 4th PMOS pipe P4, the drain electrode of the 5th PMOS pipe P5, the grid of the 2nd NMOS pipe N2, the source electrode of the 3rd NMOS pipe N3, the source electrode of the grid of the 5th NMOS pipe N5 and the 6th NMOS pipe N6 is connected to the first clock signal input terminal, the drain electrode of PMOS pipe P1, the grid of the 2nd PMOS pipe P2, the drain electrode of the 4th PMOS pipe P4, the grid of the 5th PMOS pipe P5, the source electrode of the 2nd NMOS pipe N2, the grid of the 3rd NMOS pipe N3, the grid of the source electrode of the 5th NMOS pipe N5 and the 6th NMOS pipe N6 is connected to the second clock signal input part; Shown in Fig. 3 (b), the waveform transformation module is by the 8th NMOS pipe N8, the 9th NMOS manages N9, the tenth NMOS manages N10, the 11 NMOS manages N11, the 12 NMOS pipe N12 and the 13 NMOS pipe N13 form, the drain electrode of the 8th NMOS pipe N8 is connected with the drain electrode of NMOS pipe N1, the source electrode of the 8th NMOS pipe N8 is connected with the grid of the 9th NMOS pipe N9, the drain electrode of the tenth NMOS pipe N10 is connected with the source electrode of the 7th NMOS pipe N7, the source electrode of the tenth NMOS pipe N10 is connected with the grid of the 11 NMOS pipe N11, the drain electrode of the 12 NMOS pipe N12 is connected with the source electrode of the 6th PMOS pipe P6, the source electrode of the 12 NMOS pipe N12 is connected with the grid of the 13 NMOS pipe N13, the grid of the 8th NMOS pipe N8, the grid of the grid of the tenth NMOS pipe N10 and the 12 NMOS pipe N12 is connected to the first clock signal input terminal, accesses the first clock signal

, the source electrode of the source electrode of the 9th NMOS pipe N9, the 11 NMOS pipe N11 and the source electrode of the 13 NMOS pipe N13 are connected to the second clock signal input part, access second clock signal

, the drain electrode of the 9th NMOS pipe N9 is the first signal output, and the drain electrode of the 11 NMOS pipe N11 is the secondary signal output, and the drain electrode of the 13 NMOS pipe N13 is the 3rd signal output part; The circuit structure of the circuit structure of the circuit structure of the second tri-valued, thermal-insulating domino literal computing circuit, the 3rd tri-valued, thermal-insulating domino literal computing circuit, the 4th tri-valued, thermal-insulating domino literal computing circuit is all identical with the first tri-valued, thermal-insulating domino literal computing circuit, wherein, the signal input part of the first tri-valued, thermal-insulating domino literal computing circuit accesses the first input signal J, the signal output part of the first tri-valued, thermal-insulating domino literal computing circuit is exported the first input signal JThree corresponding literal computing signals, namely first signal output output logic value is the first literal computing signal of 0

, secondary signal output output logic value is the second literal computing signal of 1

, the 3rd signal output part output logic value is 2 the 3rd literal computing signal

, the signal input part of the second tri-valued, thermal-insulating domino literal computing circuit accesses the second input signal K, the signal output part of the second tri-valued, thermal-insulating domino literal computing circuit is exported the second input signal KThree corresponding literal computing signals

,

With

, the signal input part of the 3rd tri-valued, thermal-insulating domino literal computing circuit accesses the 3rd input signal L, the signal output part of the 3rd tri-valued, thermal-insulating domino literal computing circuit is exported the 3rd input signal LThree corresponding literal computing signals

, With

, the output signal of the signal input part access three value JKL trigger basic circuits of the 4th tri-valued, thermal-insulating domino literal computing circuit Q, the signal output part output signal of the 4th tri-valued, thermal-insulating domino literal computing circuit QThree corresponding literal computing signals

,

With

In the present embodiment, three value JKL trigger basic circuits comprise that the first control signal produces circuit, the second control signal produces circuit and next state signal generating circuit.Shown in Fig. 4 (a), the first control signal produces circuit and is comprised of the 7th PMOS pipe P7, the 14 NMOS pipe N14, the 15 NMOS pipe N15, the 16 NMOS pipe N16, the 17 NMOS pipe N17, the 18 NMOS pipe N18, the 19 NMOS pipe N19 and the 20 NMOS pipe N20, the drain electrode of the drain electrode of the drain electrode of the source electrode of the 7th PMOS pipe P7, the 14 NMOS pipe N14, the 16 NMOS pipe N16 and the 18 NMOS pipe N18 and connect and itself and to connect end be the first control signal output, the control signal of the first control signal output output logic 1 signal

The source electrode of the 14 NMOS pipe N14 is connected with the drain electrode of the 15 NMOS pipe N15, the source electrode of the 16 NMOS pipe N16 is connected with the drain electrode of the 17 NMOS pipe N17, the source electrode of the 18 NMOS pipe N18 is connected with the drain electrode of the 19 NMOS pipe N19, and the drain electrode of the source electrode of the source electrode of the 15 NMOS pipe N15, the 17 NMOS pipe N17, the source electrode of the 19 NMOS pipe N19 and the 20 NMOS pipe N20 connects; Shown in Fig. 4 (b), the second control signal produces circuit by the 8th PMOS pipe P8, the 21 NMOS manages N21, the 22 NMOS manages N22, the 23 NMOS manages N23, the 24 NMOS manages N24, the 25 NMOS manages N25, the 26 NMOS pipe N26 and the 27 NMOS pipe N27 form, the source electrode of the 8th PMOS pipe P8, the drain electrode of the 21 NMOS pipe N21, the drain electrode of the drain electrode of the 23 NMOS pipe N23 and the 25 NMOS pipe N25 and connect and itself and to connect end be the second control signal output, the source electrode of the 21 NMOS pipe N21 is connected with the drain electrode of the 22 NMOS pipe N22, the source electrode of the 23 NMOS pipe N23 is connected with the drain electrode of the 24 NMOS pipe N24, the source electrode of the 25 NMOS pipe N25 is connected with the drain electrode of the 26 NMOS pipe N26, the source electrode of the 22 NMOS pipe N22, the source electrode of the 24 NMOS pipe N24, the source electrode of the 26 NMOS pipe N26 connects with the drain electrode of the 27 NMOS pipe N27; Shown in Fig. 4 (c), the next state signal generating circuit is comprised of the 9th PMOS pipe P9, the tenth PMOS pipe P10 and the 28 NMOS pipe N28, the grid of the 9th PMOS pipe P9 is connected with the first control signal output, the grid of the tenth PMOS pipe P10 is connected the control signal of the second control signal output output logic 2 signals with the second control signal output

The source electrode of the 9th PMOS pipe P9, the drain electrode of the source electrode of the tenth PMOS pipe P10 and the 28 NMOS pipe N28 and connect and itself and connect end and be signal output part, the grid of the 14 NMOS pipe N14 is connected with the secondary signal output of the first tri-valued, thermal-insulating domino literal computing circuit, the grid of the 15 NMOS pipe N15 all is connected with the first signal output of the 4th tri-valued, thermal-insulating domino literal computing circuit with the grid of the 22 NMOS pipe N22, the grid of the 16 NMOS pipe N16 is connected with the first signal output of the second tri-valued, thermal-insulating domino literal computing circuit, the grid of the 17 NMOS pipe N17 all is connected with the secondary signal output of the 4th tri-valued, thermal-insulating domino literal computing circuit with the grid of the 24 NMOS pipe N24, the grid of the 18 NMOS pipe N18 is connected with the 3rd signal output part of the 3rd tri-valued, thermal-insulating domino literal computing circuit, the grid of the 19 NMOS pipe N19 all is connected with the 3rd signal output part of the 4th tri-valued, thermal-insulating domino literal computing circuit with the grid of the 26 NMOS pipe N26, the grid of the 21 NMOS pipe N21 is connected with the 3rd signal output part of the first tri-valued, thermal-insulating domino literal computing circuit, the grid of the 23 NMOS pipe N23 is connected with the secondary signal output of the second tri-valued, thermal-insulating domino literal computing circuit, the grid of the 25 NMOS pipe N25 is connected with the first signal output of the 3rd tri-valued, thermal-insulating domino literal computing circuit, the drain electrode of the 7th PMOS pipe P7, the drain electrode of the 8th PMOS pipe P8, the source electrode of the 20 NMOS pipe N20, the grid of the source electrode of the 27 NMOS pipe N27 and the 28 NMOS pipe N28 is connected to the first clock signal input terminal, the grid of the 7th PMOS pipe P7, the grid of the 8th PMOS pipe P8, the drain electrode of the tenth PMOS pipe P10, the grid of the 20 NMOS pipe N20, the grid of the 27 NMOS pipe N27 and the 28 NMOS pipe N28 source electrode are connected to the second clock signal input part, and the drain electrode of the 9th PMOS pipe P9 is the 3rd clock signal input terminal; The circuit symbol of three value JKL trigger basic circuits is shown in Fig. 4 (d).

In the present embodiment, the design principle of adiabatic domino buffer is identical with the first tri-valued, thermal-insulating domino literal computing circuit.Shown in Fig. 6 (a), adiabatic domino buffer is by the 11 PMOS pipe P11, the 12 PMOS manages P12, the 13 PMOS manages P13, the 14 PMOS manages P14, the 15 PMOS manages P15, the 16 PMOS manages P16, the 29 NMOS manages N29, the 30 NMOS manages N30, the 31 NMOS manages N31, the 32 NMOS manages N32, the 33 NMOS manages N33, the 34 NMOS manages N34, the 35 NMOS manages N35, the 36 NMOS manages N36, the 37 NMOS manages N37, the 38 NMOS pipe N38 and the 39 NMOS pipe N39 form, the source electrode of the 11 PMOS pipe P11, the grid of the 13 PMOS pipe P13 connects with the drain electrode of the 29 NMOS pipe N29, the source electrode of the 29 NMOS pipe N29 connects with the drain electrode of the 30 NMOS pipe N30, the source electrode of the 12 PMOS pipe P12 connects with the drain electrode of the 13 PMOS pipe P13, the source electrode of the 13 PMOS pipe P13, the drain electrode of the 31 NMOS pipe N31 connects with the drain electrode of the 35 NMOS pipe N35, the source electrode of the 14 PMOS pipe P14, the grid of the 16 PMOS pipe P16, the drain electrode of the 32 NMOS pipe N32 connects with the grid of the 35 NMOS pipe N35, the source electrode of the 32 NMOS pipe N32 connects with the drain electrode of the 33 NMOS pipe N33, the source electrode of the 15 PMOS pipe P15 connects with the drain electrode of the 16 PMOS pipe P16, the drain electrode of the 16 PMOS pipe P16, the drain electrode of the 34 NMOS pipe N34 connects with the drain electrode of the 38 NMOS pipe N38, the drain electrode of the 35 NMOS pipe N35 connects with the drain electrode of the 36 NMOS pipe N36, the source electrode of the 36 NMOS pipe N36 connects with the grid of the 37 NMOS pipe N37, the source electrode of the 38 NMOS pipe N38 connects with the grid of the 39 NMOS pipe N39, the grid of the grid of the 29 NMOS pipe N29 and the 32 NMOS pipe N32 and connect and itself and connect end and be signal input part, the drain electrode of the drain electrode of the 37 NMOS pipe N37 and the 39 NMOS pipe N39 and connect and itself and connect end and be signal output part, the drain electrode of the 11 PMOS pipe P11, the grid of the 12 PMOS pipe P12, the drain electrode of the 14 PMOS pipe P14, the grid of the 15 PMOS pipe P15, the source electrode of the 30 NMOS pipe N30, the grid of the 31 NMOS pipe N31, the source electrode of the 33 NMOS pipe N33, the source electrode of the grid of the 34 NMOS pipe N34 and the 39 NMOS pipe N39 and connect and itself and to connect end be the first clock signal input terminal, the grid of the 11 PMOS pipe P11, the drain electrode of the 12 PMOS pipe P12, the grid of the 14 PMOS pipe P14, the drain electrode of the 15 PMOS pipe P15, the grid of the 30 NMOS pipe N30, the source electrode of the 31 NMOS pipe N31, the grid of the 33 NMOS pipe N33, the source electrode of the 34 NMOS pipe N34, the grid of the grid of the 36 NMOS pipe N36 and the 38 NMOS pipe N38 and connect and itself and connect end and be the second clock signal input part, the source electrode of the 37 NMOS pipe N37 is the 3rd clock signal input terminal, the output signal of adiabatic domino buffer is identical with its input signal, and its input signal of the output signal ratio of adiabatic domino buffer postpones the clock cycle half, the first clock signal input terminal of adiabatic domino buffer is connected with the first clock signal input terminal of the first tri-valued, thermal-insulating domino literal computing circuit, the first clock signal of access amplitude level counterlogic 2

, the second clock signal input part of adiabatic domino buffer is connected the second clock signal of access amplitude level counterlogic 2 with the second clock signal input part of the first tri-valued, thermal-insulating domino literal computing circuit

, the 3rd clock signal input terminal of adiabatic domino buffer is connected with the 4th clock signal input terminal, the 4th clock signal of access amplitude level counterlogic 1

, its circuit symbol is shown in Fig. 6 (b).

Such as Fig. 7, shown in Fig. 2 (a) and Fig. 2 (b), the present invention also provides a kind of tri-valued, thermal-insulating domino the anti-door that circulates, formed by three value low-power consumption domino JKL triggers, three value low-power consumption domino JKL triggers are by the first tri-valued, thermal-insulating domino literal computing circuit, the second tri-valued, thermal-insulating domino literal computing circuit, the 3rd tri-valued, thermal-insulating domino literal computing circuit, the 4th tri-valued, thermal-insulating domino literal computing circuit and three value JKL trigger basic circuits form, the first tri-valued, thermal-insulating domino literal computing circuit, the second tri-valued, thermal-insulating domino literal computing circuit, the 3rd tri-valued, thermal-insulating domino literal computing circuit and the 4th tri-valued, thermal-insulating domino literal computing circuit are provided with the first clock signal input terminal and second clock signal input part, three value JKL trigger basic circuits are provided with the first clock signal input terminal, the second clock signal input part, the 3rd clock signal input terminal, the 4th signal input part, the first signal input, secondary signal input and the 3rd signal input part, the signal output part of the first tri-valued, thermal-insulating domino literal computing circuit is connected with the first signal input of three value JKL trigger basic circuits, the signal output part of the second tri-valued, thermal-insulating domino literal computing circuit is connected with the secondary signal input of three value JKL trigger basic circuits, the signal output part of the 3rd tri-valued, thermal-insulating domino literal computing circuit is connected with the 3rd signal input part of three value JKL trigger basic circuits, the signal output part of the 4th tri-valued, thermal-insulating domino literal computing circuit is connected with the 4th signal input part of three value JKL trigger basic circuits, the signal output part of three value JKL trigger basic circuits is connected by an adiabatic domino buffer with the signal input part of the 4th tri-valued, thermal-insulating domino literal computing circuit, the first clock signal input terminal of the first tri-valued, thermal-insulating domino literal computing circuit, the first clock signal input terminal of the second tri-valued, thermal-insulating domino literal computing circuit, the first clock signal input terminal of the 3rd tri-valued, thermal-insulating domino literal computing circuit, the first clock signal input terminal of the first clock signal input terminal of the 4th tri-valued, thermal-insulating domino literal computing circuit and described three value JKL trigger basic circuits and connect and itself and connect the end be the first clock signal input terminal of three value low-power consumption domino JKL triggers, the second clock signal input part of the first tri-valued, thermal-insulating domino literal computing circuit, the second clock signal input part of the second tri-valued, thermal-insulating domino literal computing circuit, the second clock signal input part of the 3rd tri-valued, thermal-insulating domino literal computing circuit, the second clock signal input part of the second clock signal input part of the 4th tri-valued, thermal-insulating domino literal computing circuit and three value JKL trigger basic circuits and connect and itself and connect the end be the second clock signal input part of three value low-power consumption domino JKL triggers, the 3rd clock signal input terminal of three value JKL trigger basic circuits is the 3rd clock signal input terminal of three value low-power consumption domino JKL triggers, this three values low-power consumption domino JKL trigger also is provided with the 4th clock signal input terminal, and the first clock signal input terminal access amplitude level is the first clock signal of 2 , second clock signal input part access amplitude level is 2 second clock signal

, the 3rd clock signal input terminal access amplitude level is 1 the 3rd clock signal

, the 4th clock signal input terminal access amplitude level is 1 the 4th clock signal , the first clock signal

With the 4th clock signal

Phase place is identical, the second clock signal

With the 3rd clock signal phase Identical, the first clock signal

With the second clock signal

Phase phasic difference 180 degree, the signal input part of the signal input part of the first tri-valued, thermal-insulating domino literal computing circuit, the second tri-valued, thermal-insulating domino literal computing circuit, the signal input part of the 3rd tri-valued, thermal-insulating domino literal computing circuit and the clock signal input terminal of being connected connect; The first clock signal

, the second clock signal

, the 3rd clock signal

With the 4th clock signal

Oscillogram as shown in Figure 5.

In the present embodiment, the first tri-valued, thermal-insulating domino literal computing circuit comprises literal computing module and waveform transformation module.Shown in Fig. 3 (a), described literal computing module is by PMOS pipe P1, the 2nd PMOS manages P2, the 3rd PMOS manages P3, the 4th PMOS manages P4, the 5th PMOS manages P5, the 6th PMOS manages P6, the one NMOS manages N1, the 2nd NMOS manages N2, the 3rd NMOS manages N3, the 4th NMOS manages N4, the 5th NMOS manages N5, the 6th NMOS pipe N6 and the 7th NMOS pipe N7 form, the grid of the grid of the one NMOS pipe N1 and the 4th NMOS pipe N4 and connect and itself and connect end and be signal input part, the drain electrode of the one NMOS pipe N1, the grid of the source electrode of the one PMOS pipe P1 and the 3rd PMOS pipe P3 also connects, the source electrode of the one NMOS pipe N1 is connected with the drain electrode of the 2nd NMOS pipe N2, the source electrode of the 2nd PMOS pipe P2 is connected with the drain electrode of the 3rd PMOS pipe P3, the source electrode of the 3rd PMOS pipe P3, the drain electrode of the drain electrode of the 3rd NMOS pipe N3 and the 7th NMOS pipe N7 also connects, the source electrode of the 4th PMOS pipe P4, the drain electrode of the 4th NMOS pipe N4, the grid of the grid of the 6th PMOS pipe P6 and the 7th NMOS pipe N7 and connect and itself and connect end, the source electrode of the 4th NMOS pipe N4 is connected with the drain electrode of the 5th NMOS pipe N5, the source electrode of the 5th PMOS pipe P5 is connected with the drain electrode of the 6th PMOS pipe P6, the drain electrode of the source electrode of the 6th PMOS pipe P6 and the 6th NMOS pipe N6 also connects, the grid of the one PMOS pipe P1, the drain electrode of the 2nd PMOS pipe P2, the grid of the 4th PMOS pipe P4, the drain electrode of the 5th PMOS pipe P5, the grid of the 2nd NMOS pipe N2, the source electrode of the 3rd NMOS pipe N3, the source electrode of the grid of the 5th NMOS pipe N5 and the 6th NMOS pipe N6 is connected to the first clock signal input terminal, the drain electrode of PMOS pipe P1, the grid of the 2nd PMOS pipe P2, the drain electrode of the 4th PMOS pipe P4, the grid of the 5th PMOS pipe P5, the source electrode of the 2nd NMOS pipe N2, the grid of the 3rd NMOS pipe N3, the grid of the source electrode of the 5th NMOS pipe N5 and the 6th NMOS pipe N6 is connected to the second clock signal input part; Shown in Fig. 3 (b), the waveform transformation module is by the 8th NMOS pipe N8, the 9th NMOS manages N9, the tenth NMOS manages N10, the 11 NMOS manages N11, the 12 NMOS pipe N12 and the 13 NMOS pipe N13 form, the drain electrode of the 8th NMOS pipe N8 is connected with the drain electrode of NMOS pipe N1, the source electrode of the 8th NMOS pipe N8 is connected with the grid of the 9th NMOS pipe N9, the drain electrode of the tenth NMOS pipe N10 is connected with the source electrode of the 7th NMOS pipe N7, the source electrode of the tenth NMOS pipe N10 is connected with the grid of the 11 NMOS pipe N11, the drain electrode of the 12 NMOS pipe N12 is connected with the source electrode of the 6th PMOS pipe P6, the source electrode of the 12 NMOS pipe N12 is connected with the grid of the 13 NMOS pipe N13, the grid of the 8th NMOS pipe N8, the grid of the grid of the tenth NMOS pipe N10 and the 12 NMOS pipe N12 is connected to the first clock signal input terminal, accesses the first clock signal

, the source electrode of the source electrode of the 9th NMOS pipe N9, the 11 NMOS pipe N11 and the source electrode of the 13 NMOS pipe N13 are connected to the second clock signal input part, access second clock signal

, the drain electrode of the 9th NMOS pipe N9 is the first signal output, and the drain electrode of the 11 NMOS pipe N11 is the secondary signal output, and the drain electrode of the 13 NMOS pipe N13 is the 3rd signal output part; The circuit structure of the circuit structure of the circuit structure of the second tri-valued, thermal-insulating domino literal computing circuit, the 3rd tri-valued, thermal-insulating domino literal computing circuit, the 4th tri-valued, thermal-insulating domino literal computing circuit is all identical with the first tri-valued, thermal-insulating domino literal computing circuit, wherein, the signal input part of the first tri-valued, thermal-insulating domino literal computing circuit accesses the first input signal J, the signal output part of the first tri-valued, thermal-insulating domino literal computing circuit is exported the first input signal JThree corresponding literal computing signals, namely first signal output output logic value is the first literal computing signal of 0

, secondary signal output output logic value is the second literal computing signal of 1 , the 3rd signal output part output logic value is 2 the 3rd literal computing signal , the signal input part of the second tri-valued, thermal-insulating domino literal computing circuit accesses the second input signal K, the signal output part of the second tri-valued, thermal-insulating domino literal computing circuit is exported the second input signal KThree corresponding literal computing signals

,

With , the signal input part of the 3rd tri-valued, thermal-insulating domino literal computing circuit accesses the 3rd input signal L, the signal output part of the 3rd tri-valued, thermal-insulating domino literal computing circuit is exported the 3rd input signal LThree corresponding literal computing signals

,

With

, the output signal of the signal input part access three value JKL trigger basic circuits of the 4th tri-valued, thermal-insulating domino literal computing circuit Q, the signal output part output signal of the 4th tri-valued, thermal-insulating domino literal computing circuit QThree corresponding literal computing signals

,

With

In the present embodiment, three value JKL trigger basic circuits comprise that the first control signal produces circuit, the second control signal produces circuit and next state signal generating circuit.Shown in Fig. 4 (a), the first control signal produces circuit and is comprised of the 7th PMOS pipe P7, the 14 NMOS pipe N14, the 15 NMOS pipe N15, the 16 NMOS pipe N16, the 17 NMOS pipe N17, the 18 NMOS pipe N18, the 19 NMOS pipe N19 and the 20 NMOS pipe N20, the drain electrode of the drain electrode of the drain electrode of the source electrode of the 7th PMOS pipe P7, the 14 NMOS pipe N14, the 16 NMOS pipe N16 and the 18 NMOS pipe N18 and connect and itself and to connect end be the first control signal output, the control signal of the first control signal output output logic 1 signal

The source electrode of the 14 NMOS pipe N14 is connected with the drain electrode of the 15 NMOS pipe N15, the source electrode of the 16 NMOS pipe N16 is connected with the drain electrode of the 17 NMOS pipe N17, the source electrode of the 18 NMOS pipe N18 is connected with the drain electrode of the 19 NMOS pipe N19, and the drain electrode of the source electrode of the source electrode of the 15 NMOS pipe N15, the 17 NMOS pipe N17, the source electrode of the 19 NMOS pipe N19 and the 20 NMOS pipe N20 connects; Shown in Fig. 4 (b), the second control signal produces circuit by the 8th PMOS pipe P8, the 21 NMOS manages N21, the 22 NMOS manages N22, the 23 NMOS manages N23, the 24 NMOS manages N24, the 25 NMOS manages N25, the 26 NMOS pipe N26 and the 27 NMOS pipe N27 form, the source electrode of the 8th PMOS pipe P8, the drain electrode of the 21 NMOS pipe N21, the drain electrode of the drain electrode of the 23 NMOS pipe N23 and the 25 NMOS pipe N25 and connect and itself and to connect end be the second control signal output, the source electrode of the 21 NMOS pipe N21 is connected with the drain electrode of the 22 NMOS pipe N22, the source electrode of the 23 NMOS pipe N23 is connected with the drain electrode of the 24 NMOS pipe N24, the source electrode of the 25 NMOS pipe N25 is connected with the drain electrode of the 26 NMOS pipe N26, the source electrode of the 22 NMOS pipe N22, the source electrode of the 24 NMOS pipe N24, the source electrode of the 26 NMOS pipe N26 connects with the drain electrode of the 27 NMOS pipe N27; Shown in Fig. 4 (c), the next state signal generating circuit is comprised of the 9th PMOS pipe P9, the tenth PMOS pipe P10 and the 28 NMOS pipe N28, the grid of the 9th PMOS pipe P9 is connected with the first control signal output, the grid of the tenth PMOS pipe P10 is connected the control signal of the second control signal output output logic 2 signals with the second control signal output

The source electrode of the 9th PMOS pipe P9, the drain electrode of the source electrode of the tenth PMOS pipe P10 and the 28 NMOS pipe N28 and connect and itself and connect end and be signal output part, the grid of the 14 NMOS pipe N14 is connected with the secondary signal output of the first tri-valued, thermal-insulating domino literal computing circuit, the grid of the 15 NMOS pipe N15 all is connected with the first signal output of the 4th tri-valued, thermal-insulating domino literal computing circuit with the grid of the 22 NMOS pipe N22, the grid of the 16 NMOS pipe N16 is connected with the first signal output of the second tri-valued, thermal-insulating domino literal computing circuit, the grid of the 17 NMOS pipe N17 all is connected with the secondary signal output of the 4th tri-valued, thermal-insulating domino literal computing circuit with the grid of the 24 NMOS pipe N24, the grid of the 18 NMOS pipe N18 is connected with the 3rd signal output part of the 3rd tri-valued, thermal-insulating domino literal computing circuit, the grid of the 19 NMOS pipe N19 all is connected with the 3rd signal output part of the 4th tri-valued, thermal-insulating domino literal computing circuit with the grid of the 26 NMOS pipe N26, the grid of the 21 NMOS pipe N21 is connected with the 3rd signal output part of the first tri-valued, thermal-insulating domino literal computing circuit, the grid of the 23 NMOS pipe N23 is connected with the secondary signal output of the second tri-valued, thermal-insulating domino literal computing circuit, the grid of the 25 NMOS pipe N25 is connected with the first signal output of the 3rd tri-valued, thermal-insulating domino literal computing circuit, the drain electrode of the 7th PMOS pipe P7, the drain electrode of the 8th PMOS pipe P8, the source electrode of the 20 NMOS pipe N20, the grid of the source electrode of the 27 NMOS pipe N27 and the 28 NMOS pipe N28 is connected to the first clock signal input terminal, the grid of the 7th PMOS pipe P7, the grid of the 8th PMOS pipe P8, the drain electrode of the tenth PMOS pipe P10, the grid of the 20 NMOS pipe N20, the grid of the 27 NMOS pipe N27 and the 28 NMOS pipe N28 source electrode are connected to the second clock signal input part, and the drain electrode of the 9th PMOS pipe P9 is the 3rd clock signal input terminal; The circuit symbol of three value JKL trigger basic circuits is shown in Fig. 4 (d).

In the present embodiment, the design principle of adiabatic domino buffer is identical with the first tri-valued, thermal-insulating domino literal computing circuit.Shown in Fig. 6 (a), adiabatic domino buffer is by the 11 PMOS pipe P11, the 12 PMOS manages P12, the 13 PMOS manages P13, the 14 PMOS manages P14, the 15 PMOS manages P15, the 16 PMOS manages P16, the 29 NMOS manages N29, the 30 NMOS manages N30, the 31 NMOS manages N31, the 32 NMOS manages N32, the 33 NMOS manages N33, the 34 NMOS manages N34, the 35 NMOS manages N35, the 36 NMOS manages N36, the 37 NMOS manages N37, the 38 NMOS pipe N38 and the 39 NMOS pipe N39 form, the source electrode of the 11 PMOS pipe P11, the grid of the 13 PMOS pipe P13 connects with the drain electrode of the 29 NMOS pipe N29, the source electrode of the 29 NMOS pipe N29 connects with the drain electrode of the 30 NMOS pipe N30, the source electrode of the 12 PMOS pipe P12 connects with the drain electrode of the 13 PMOS pipe P13, the source electrode of the 13 PMOS pipe P13, the drain electrode of the 31 NMOS pipe N31 connects with the drain electrode of the 35 NMOS pipe N35, the source electrode of the 14 PMOS pipe P14, the grid of the 16 PMOS pipe P16, the drain electrode of the 32 NMOS pipe N32 connects with the grid of the 35 NMOS pipe N35, the source electrode of the 32 NMOS pipe N32 connects with the drain electrode of the 33 NMOS pipe N33, the source electrode of the 15 PMOS pipe P15 connects with the drain electrode of the 16 PMOS pipe P16, the drain electrode of the 16 PMOS pipe P16, the drain electrode of the 34 NMOS pipe N34 connects with the drain electrode of the 38 NMOS pipe N38, the drain electrode of the 35 NMOS pipe N35 connects with the drain electrode of the 36 NMOS pipe N36, the source electrode of the 36 NMOS pipe N36 connects with the grid of the 37 NMOS pipe N37, the source electrode of the 38 NMOS pipe N38 connects with the grid of the 39 NMOS pipe N39, the grid of the grid of the 29 NMOS pipe N29 and the 32 NMOS pipe N32 and connect and itself and connect end and be signal input part, the drain electrode of the drain electrode of the 37 NMOS pipe N37 and the 39 NMOS pipe N39 and connect and itself and connect end and be signal output part, the drain electrode of the 11 PMOS pipe P11, the grid of the 12 PMOS pipe P12, the drain electrode of the 14 PMOS pipe P14, the grid of the 15 PMOS pipe P15, the source electrode of the 30 NMOS pipe N30, the grid of the 31 NMOS pipe N31, the source electrode of the 33 NMOS pipe N33, the source electrode of the grid of the 34 NMOS pipe N34 and the 39 NMOS pipe N39 and connect and itself and to connect end be the first clock signal input terminal, the grid of the 11 PMOS pipe P11, the drain electrode of the 12 PMOS pipe P12, the grid of the 14 PMOS pipe P14, the drain electrode of the 15 PMOS pipe P15, the grid of the 30 NMOS pipe N30, the source electrode of the 31 NMOS pipe N31, the grid of the 33 NMOS pipe N33, the source electrode of the 34 NMOS pipe N34, the grid of the grid of the 36 NMOS pipe N36 and the 38 NMOS pipe N38 and connect and itself and connect end and be the second clock signal input part, the source electrode of the 37 NMOS pipe N37 is the 3rd clock signal input terminal, the output signal of adiabatic domino buffer is identical with its input signal, and its input signal of the output signal ratio of adiabatic domino buffer postpones the clock cycle half, the first clock signal input terminal of adiabatic domino buffer is connected with the first clock signal input terminal of the first tri-valued, thermal-insulating domino literal computing circuit, the first clock signal of access amplitude level counterlogic 2 , the second clock signal input part of adiabatic domino buffer is connected the second clock signal of access amplitude level counterlogic 2 with the second clock signal input part of the first tri-valued, thermal-insulating domino literal computing circuit , the 3rd clock signal input terminal of adiabatic domino buffer is connected with the 4th clock signal input terminal, the 4th clock signal of access amplitude level counterlogic 1

, its circuit symbol is shown in Fig. 6 (b).

Utilize Spice software, under TSMC 0.25 μ m CMOS technological parameter, three value low-power consumption domino JKL triggers are simulated, waveform as shown in Figure 8.Wherein the level of logical value 0,1,2 correspondences is respectively 0V, 1.25V, 2.5V; Clk ₁, , Clk,

Amplitude be respectively 1.25 V, 1.25 V, 2.5 V, 2.5 V, frequency all is 20 MHz; The NMOS breadth length ratio is all got 0.36 μ m/0.24 μ m, and the PMOS breadth length ratio is all got 0.72 μ m/0.24 μ m; Load capacitance is 10 fF; J, K, LBe input signal, QBe output signal.Analysis chart 8 as can be known, the logic function of this circuit and three value JKL trigger truth tables are consistent, prove that designed circuit logic function is correct.

Under identical parameters, tri-valued, thermal-insulating domino JKL trigger and the conventional domino JKL trigger of three values that adopts DC power supply are carried out power dissipation ratio, as shown in Figure 9.The electric charge of storing in the concave bottom proof circuit node among Fig. 9 in the tri-valued, thermal-insulating domino JKL trigger power consumption curve is recovered to power clock, thereby effectively reduces circuit power consumption.By analysis, this tri-valued, thermal-insulating domino JKL trigger is compared with the conventional domino JKL trigger of three values that adopts DC power supply, and power consumption saves approximately 69%, proves that designed circuit low-power consumption characteristic is obvious.

In sum, has lower power consumption by three value low-power consumption domino JKL triggers tri-valued, thermal-insulating domino direct circulation door in groups and anti-circulation door on the basis with correct logic.

Claims (8)

1. tri-valued, thermal-insulating domino direct circulation door, it is characterized in that being formed by three value low-power consumption domino JKL triggers, described three value low-power consumption domino JKL triggers are by the first tri-valued, thermal-insulating domino literal computing circuit, the second tri-valued, thermal-insulating domino literal computing circuit, the 3rd tri-valued, thermal-insulating domino literal computing circuit, the 4th tri-valued, thermal-insulating domino literal computing circuit, three value JKL trigger basic circuits and adiabatic domino buffer form, described the first tri-valued, thermal-insulating domino literal computing circuit, described the second tri-valued, thermal-insulating domino literal computing circuit, described the 3rd tri-valued, thermal-insulating domino literal computing circuit and described the 4th tri-valued, thermal-insulating domino literal computing circuit are provided with the first clock signal input terminal and second clock signal input part, described three value JKL trigger basic circuits are provided with the first clock signal input terminal, the second clock signal input part, the 3rd clock signal input terminal, the first signal input, the secondary signal input, the 3rd signal input part and the 4th signal input part, the signal output part of described the first tri-valued, thermal-insulating domino literal computing circuit is connected with the first signal input of described three value JKL trigger basic circuits, the signal output part of described the second tri-valued, thermal-insulating domino literal computing circuit is connected with the secondary signal input of described three value JKL trigger basic circuits, the signal output part of described the 3rd tri-valued, thermal-insulating domino literal computing circuit is connected with the 3rd signal input part of described three value JKL trigger basic circuits, the signal output part of described the 4th tri-valued, thermal-insulating domino literal computing circuit is connected with the 4th signal input part of described three value JKL trigger basic circuits, the signal output part of described three value JKL trigger basic circuits is connected with the signal input part of described adiabatic domino buffer, the signal output part of described adiabatic domino buffer is connected with the signal input part of described the 4th tri-valued, thermal-insulating domino literal computing circuit, the first clock signal input terminal of described the first tri-valued, thermal-insulating domino literal computing circuit, the first clock signal input terminal of described the second tri-valued, thermal-insulating domino literal computing circuit, the first clock signal input terminal of described the 3rd tri-valued, thermal-insulating domino literal computing circuit, the first clock signal input terminal of the first clock signal input terminal of described the 4th tri-valued, thermal-insulating domino literal computing circuit and described three value JKL trigger basic circuits and connect and itself and connect the end be the first clock signal input terminal of three value low-power consumption domino JKL triggers, the second clock signal input part of described the first tri-valued, thermal-insulating domino literal computing circuit, the second clock signal input part of described the second tri-valued, thermal-insulating domino literal computing circuit, the second clock signal input part of described the 3rd tri-valued, thermal-insulating domino literal computing circuit, the second clock signal input part of the second clock signal input part of described the 4th tri-valued, thermal-insulating domino literal computing circuit and described three value JKL trigger basic circuits and connect and itself and connect the end be the second clock signal input part of three value low-power consumption domino JKL triggers, the 3rd clock signal input terminal of described three value JKL trigger basic circuits is the 3rd clock signal input terminal of three value low-power consumption domino JKL triggers, this three values low-power consumption domino JKL trigger also is provided with the 4th clock signal input terminal, described the first clock signal input terminal access amplitude level is the first clock signal of 2, described second clock signal input part access amplitude level is 2 second clock signal, described the 3rd clock signal input terminal access amplitude level is 1 the 3rd clock signal, described the 4th clock signal input terminal access amplitude level is 1 the 4th clock signal, described the first clock signal is identical with described the 4th clock signal phase, described second clock signal is identical with described the 3rd clock signal phase, described the first clock signal and described second clock signal phase differ 180 degree, the signal input part of described the first tri-valued, thermal-insulating domino literal computing circuit, the signal input part of described the second tri-valued, thermal-insulating domino literal computing circuit, the signal input part of described the 3rd tri-valued, thermal-insulating domino literal computing circuit be connected the 4th clock signal input terminal and connect.

2. a kind of tri-valued, thermal-insulating domino direct circulation door according to claim 1, it is characterized in that described the first tri-valued, thermal-insulating domino literal computing circuit comprises literal computing module and waveform transformation module, described literal computing module is managed by a PMOS, the 2nd PMOS pipe, the 3rd PMOS pipe, the 4th PMOS pipe, the 5th PMOS pipe, the 6th PMOS pipe, the one NMOS pipe, the 2nd NMOS pipe, the 3rd NMOS pipe, the 4th NMOS pipe, the 5th NMOS pipe, the 6th NMOS pipe and the 7th NMOS pipe form, the grid of the grid of a described NMOS pipe and described the 4th NMOS pipe and connect and itself and connect end for signal input part, the drain electrode of a described NMOS pipe, the grid of the source electrode of a described PMOS pipe and described the 3rd PMOS pipe also connects, the source electrode of a described NMOS pipe is connected with the drain electrode of described the 2nd NMOS pipe, the source electrode of described the 2nd PMOS pipe is connected with the drain electrode of described the 3rd PMOS pipe, the source electrode of described the 3rd PMOS pipe, the drain electrode of the drain electrode of described the 3rd NMOS pipe and described the 7th NMOS pipe also connects, the source electrode of described the 4th PMOS pipe, the drain electrode of described the 4th NMOS pipe, the grid of the grid of described the 6th PMOS pipe and described the 7th NMOS pipe also connects, the source electrode of described the 4th NMOS pipe is connected with the drain electrode of described the 5th NMOS pipe, the source electrode of described the 5th PMOS pipe is connected with the drain electrode of described the 6th PMOS pipe, the drain electrode of the source electrode of described the 6th PMOS pipe and described the 6th NMOS pipe also connects, the grid of a described PMOS pipe, the drain electrode of described the 2nd PMOS pipe, the grid of described the 4th PMOS pipe, the drain electrode of described the 5th PMOS pipe, the grid of described the 2nd NMOS pipe, the source electrode of described the 3rd NMOS pipe, the source electrode of the grid of described the 5th NMOS pipe and described the 6th NMOS pipe is connected to the first clock signal input terminal, the drain electrode of a described PMOS pipe, the grid of described the 2nd PMOS pipe, the drain electrode of described the 4th PMOS pipe, the grid of described the 5th PMOS pipe, the source electrode of described the 2nd NMOS pipe, the grid of described the 3rd NMOS pipe, the grid of the source electrode of described the 5th NMOS pipe and described the 6th NMOS pipe is connected to the second clock signal input part, described waveform transformation module is managed by the 8th NMOS, the 9th NMOS pipe, the tenth NMOS pipe, the 11 NMOS pipe, the 12 NMOS pipe and the 13 NMOS pipe form, the drain electrode of described the 8th NMOS pipe is connected with the drain electrode of a described NMOS pipe, the source electrode of described the 8th NMOS pipe is connected with the grid of described the 9th NMOS pipe, the drain electrode of described the tenth NMOS pipe is connected with the source electrode of described the 7th NMOS pipe, the source electrode of described the tenth NMOS pipe is connected with the grid of described the 11 NMOS pipe, the drain electrode of described the 12 NMOS pipe is connected with the source electrode of described the 6th PMOS pipe, the source electrode of described the 12 NMOS pipe is connected with the grid of described the 13 NMOS pipe, the grid of described the 8th NMOS pipe, the grid of described the tenth NMOS pipe and the grid of described the 12 NMOS pipe are connected to the first clock signal input terminal, the source electrode of described the 9th NMOS pipe, the source electrode of described the 11 NMOS pipe and the source electrode of described the 13 NMOS pipe are connected to the second clock signal input part, the drain electrode of described the 9th NMOS pipe is the first signal output, the drain electrode of described the 11 NMOS pipe is the secondary signal output, the drain electrode of described the 13 NMOS pipe is the 3rd signal output part, the circuit structure of described the second tri-valued, thermal-insulating domino literal computing circuit, the circuit structure of described the 3rd tri-valued, thermal-insulating domino literal computing circuit, the circuit structure of described the 4th tri-valued, thermal-insulating domino literal computing circuit is all identical with described the first tri-valued, thermal-insulating domino literal computing circuit.

3. a kind of tri-valued, thermal-insulating domino direct circulation door according to claim 2, it is characterized in that described three value JKL trigger basic circuits comprise that the first control signal produces circuit, the second control signal produces circuit and next state signal generating circuit, described the first control signal produces circuit and is managed by the 7th PMOS, the 14 NMOS pipe, the 15 NMOS pipe, the 16 NMOS pipe, the 17 NMOS pipe, the 18 NMOS pipe, the 19 NMOS pipe and the 20 NMOS pipe form, the source electrode of described the 7th PMOS pipe, the drain electrode of described the 14 NMOS pipe, the drain electrode of described the 16 NMOS pipe and the drain electrode of described the 18 NMOS pipe and connect and itself and connect the end be the first control signal output, the source electrode of described the 14 NMOS pipe is connected with the drain electrode of described the 15 NMOS pipe, the source electrode of described the 16 NMOS pipe is connected with the drain electrode of described the 17 NMOS pipe, the source electrode of described the 18 NMOS pipe is connected with the drain electrode of described the 19 NMOS pipe, the source electrode of described the 15 NMOS pipe, the source electrode of described the 17 NMOS pipe, the source electrode of described the 19 NMOS pipe be connected the drain electrode of the 20 NMOS pipe and connect, described the second control signal produces circuit and is managed by the 8th PMOS, the 21 NMOS pipe, the 22 NMOS pipe, the 23 NMOS pipe, the 24 NMOS pipe, the 25 NMOS pipe, the 26 NMOS pipe and the 27 NMOS pipe form, the source electrode of described the 8th PMOS pipe, the drain electrode of described the 21 NMOS pipe, the drain electrode of described the 23 NMOS pipe and the drain electrode of described the 25 NMOS pipe and connect and itself and connect the end be the second control signal output, the source electrode of described the 21 NMOS pipe is connected with the drain electrode of described the 22 NMOS pipe, the source electrode of described the 23 NMOS pipe is connected with the drain electrode of described the 24 NMOS pipe, the source electrode of described the 25 NMOS pipe is connected with the drain electrode of described the 26 NMOS pipe, the source electrode of described the 22 NMOS pipe, the source electrode of described the 24 NMOS pipe, the source electrode of described the 26 NMOS pipe be connected the drain electrode of the 27 NMOS pipe and connect, described next state signal generating circuit is managed by the 9th PMOS, the tenth PMOS pipe and the 28 NMOS pipe form, the grid of described the 9th PMOS pipe is connected with described the first control signal output, the grid of described the tenth PMOS pipe is connected with described the second control signal output, the source electrode of described the 9th PMOS pipe, the drain electrode of the source electrode of described the tenth PMOS pipe and described the 28 NMOS pipe and connect and itself and connect end for signal output part, the grid of described the 14 NMOS pipe is connected with the secondary signal output of described the first tri-valued, thermal-insulating domino literal computing circuit, the grid of the 15 NMOS pipe be connected the grid of the 22 NMOS pipe and all be connected with the first signal output of described the 4th tri-valued, thermal-insulating domino literal computing circuit, the grid of described the 16 NMOS pipe is connected with the first signal output of described the second tri-valued, thermal-insulating domino literal computing circuit, the grid of described the 17 NMOS pipe be connected the grid of the 24 NMOS pipe and all be connected with the secondary signal output of described the 4th tri-valued, thermal-insulating domino literal computing circuit, the grid of described the 18 NMOS pipe is connected with the 3rd signal output part of described the 3rd tri-valued, thermal-insulating domino literal computing circuit, the grid of described the 19 NMOS pipe be connected the grid of the 26 NMOS pipe and all be connected with the 3rd signal output part of described the 4th tri-valued, thermal-insulating domino literal computing circuit, the grid of described the 21 NMOS pipe is connected with the 3rd signal output part of described the first tri-valued, thermal-insulating domino literal computing circuit, the grid of described the 23 NMOS pipe is connected with the secondary signal output of described the second tri-valued, thermal-insulating domino literal computing circuit, the grid of described the 25 NMOS pipe is connected with the first signal output of described the 3rd tri-valued, thermal-insulating domino literal computing circuit, the drain electrode of described the 7th PMOS pipe, the drain electrode of described the 8th PMOS pipe, the source electrode of described the 20 NMOS pipe, the source electrode of described the 27 NMOS pipe and the grid of described the 28 NMOS pipe are connected to the first clock signal input terminal, the grid of described the 7th PMOS pipe, the grid of described the 8th PMOS pipe, the drain electrode of described the tenth PMOS pipe, the grid of described the 20 NMOS pipe, the grid of described the 27 NMOS pipe and described the 28 NMOS pipe source electrode are connected to the second clock signal input part, and the drain electrode of described the 9th PMOS pipe is the 3rd clock signal input terminal.

4. each described a kind of tri-valued, thermal-insulating domino direct circulation door in the claim 1～3, it is characterized in that described adiabatic domino buffer managed by the 11 PMOS, the 12 PMOS pipe, the 13 PMOS pipe, the 14 PMOS pipe, the 15 PMOS pipe, the 16 PMOS pipe, the 29 NMOS pipe, the 30 NMOS pipe, the 31 NMOS pipe, the 32 NMOS pipe, the 33 NMOS pipe, the 34 NMOS pipe, the 35 NMOS pipe, the 36 NMOS pipe, the 37 NMOS pipe, the 38 NMOS pipe and the 39 NMOS pipe form, the source electrode of described the 11 PMOS pipe, the grid of described the 13 PMOS pipe be connected the drain electrode of the 29 NMOS pipe and connect, the source electrode of described the 29 NMOS pipe be connected the drain electrode of the 30 NMOS pipe and connect, the source electrode of described the 12 PMOS pipe be connected the drain electrode of the 13 PMOS pipe and connect, the source electrode of described the 13 PMOS pipe, the drain electrode of described the 31 NMOS pipe be connected the drain electrode of the 35 NMOS pipe and connect, the source electrode of described the 14 PMOS pipe, the grid of described the 16 PMOS pipe, the drain electrode of described the 32 NMOS pipe be connected the grid of the 35 NMOS pipe and connect, the source electrode of described the 32 NMOS pipe be connected the drain electrode of the 33 NMOS pipe and connect, the source electrode of described the 15 PMOS pipe be connected the drain electrode of the 16 PMOS pipe and connect, the drain electrode of described the 16 PMOS pipe, the drain electrode of described the 34 NMOS pipe be connected the drain electrode of the 38 NMOS pipe and connect, the drain electrode of described the 35 NMOS pipe be connected the drain electrode of the 36 NMOS pipe and connect, the source electrode of described the 36 NMOS pipe be connected the grid of the 37 NMOS pipe and connect, the source electrode of described the 38 NMOS pipe be connected the grid of the 39 NMOS pipe and connect, the grid of the grid of described the 29 NMOS pipe and described the 32 NMOS pipe and connect and itself and connect end for signal input part, the drain electrode of the drain electrode of described the 37 NMOS pipe and described the 39 NMOS pipe and connect and itself and connect end for signal output part, the drain electrode of described the 11 PMOS pipe, the grid of described the 12 PMOS pipe, the drain electrode of described the 14 PMOS pipe, the grid of described the 15 PMOS pipe, the source electrode of described the 30 NMOS pipe, the grid of described the 31 NMOS pipe, the source electrode of described the 33 NMOS pipe, the grid of described the 34 NMOS pipe and the source electrode of described the 39 NMOS pipe and connect and itself and connect the end be the first clock signal input terminal, the grid of described the 11 PMOS pipe, the drain electrode of described the 12 PMOS pipe, the grid of described the 14 PMOS pipe, the drain electrode of described the 15 PMOS pipe, the grid of described the 30 NMOS pipe, the source electrode of described the 31 NMOS pipe, the grid of described the 33 NMOS pipe, the source electrode of described the 34 NMOS pipe, the grid of the grid of described the 36 NMOS pipe and described the 38 NMOS pipe and connect and itself and connect end for the second clock signal input part, the source electrode of described the 37 NMOS pipe is the 3rd clock signal input terminal, the output signal of described adiabatic domino buffer is identical with its input signal, and its input signal of the output signal ratio of described adiabatic domino buffer postpones the clock cycle half, the first clock signal input terminal of described adiabatic domino buffer is connected with the first clock signal input terminal of described the first tri-valued, thermal-insulating domino literal computing circuit, the second clock signal input part of described adiabatic domino buffer is connected with the second clock signal input part of described the first tri-valued, thermal-insulating domino literal computing circuit, and the 3rd clock signal input terminal of described adiabatic domino buffer is connected with described the 4th clock signal input terminal.

5. anti-door that circulates of tri-valued, thermal-insulating domino, it is characterized in that being formed by three value low-power consumption domino JKL triggers, described three value low-power consumption domino JKL triggers are by the first tri-valued, thermal-insulating domino literal computing circuit, the second tri-valued, thermal-insulating domino literal computing circuit, the 3rd tri-valued, thermal-insulating domino literal computing circuit, the 4th tri-valued, thermal-insulating domino literal computing circuit and three value JKL trigger basic circuits form, described the first tri-valued, thermal-insulating domino literal computing circuit, described the second tri-valued, thermal-insulating domino literal computing circuit, described the 3rd tri-valued, thermal-insulating domino literal computing circuit and described the 4th tri-valued, thermal-insulating domino literal computing circuit are provided with the first clock signal input terminal and second clock signal input part, described three value JKL trigger basic circuits are provided with the first clock signal input terminal, the second clock signal input part, the 3rd clock signal input terminal, the 4th signal input part, the first signal input, secondary signal input and the 3rd signal input part, the signal output part of described the first tri-valued, thermal-insulating domino literal computing circuit is connected with the first signal input of described three value JKL trigger basic circuits, the signal output part of described the second tri-valued, thermal-insulating domino literal computing circuit is connected with the secondary signal input of described three value JKL trigger basic circuits, the signal output part of described the 3rd tri-valued, thermal-insulating domino literal computing circuit is connected with the 3rd signal input part of described three value JKL trigger basic circuits, the signal output part of described the 4th tri-valued, thermal-insulating domino literal computing circuit is connected with the 4th signal input part of described three value JKL trigger basic circuits, the signal output part of described three value JKL trigger basic circuits is connected by an adiabatic domino buffer with the signal input part of described the 4th tri-valued, thermal-insulating domino literal computing circuit, the first clock signal input terminal of described the first tri-valued, thermal-insulating domino literal computing circuit, the first clock signal input terminal of described the second tri-valued, thermal-insulating domino literal computing circuit, the first clock signal input terminal of described the 3rd tri-valued, thermal-insulating domino literal computing circuit, the first clock signal input terminal of the first clock signal input terminal of described the 4th tri-valued, thermal-insulating domino literal computing circuit and described three value JKL trigger basic circuits and connect and itself and connect the end be the first clock signal input terminal of three value low-power consumption domino JKL triggers, the second clock signal input part of described the first tri-valued, thermal-insulating domino literal computing circuit, the second clock signal input part of described the second tri-valued, thermal-insulating domino literal computing circuit, the second clock signal input part of described the 3rd tri-valued, thermal-insulating domino literal computing circuit, the second clock signal input part of the second clock signal input part of described the 4th tri-valued, thermal-insulating domino literal computing circuit and described three value JKL trigger basic circuits and connect and itself and connect the end be the second clock signal input part of three value low-power consumption domino JKL triggers, the 3rd clock signal input terminal of described three value JKL trigger basic circuits is the 3rd clock signal input terminal of three value low-power consumption domino JKL triggers, this three values low-power consumption domino JKL trigger also is provided with the 4th clock signal input terminal, described the first clock signal input terminal access amplitude level is the first clock signal of 2, described second clock signal input part access amplitude level is 2 second clock signal, described the 3rd clock signal input terminal access amplitude level is 1 the 3rd clock signal, described the 4th clock signal input terminal access amplitude level is 1 the 4th clock signal, described the first clock signal is identical with described the 4th clock signal phase, described second clock signal is identical with described the 3rd clock signal phase, described the first clock signal and described second clock signal phase differ 180 degree, the signal input part of described the first tri-valued, thermal-insulating domino literal computing circuit, the signal input part of described the second tri-valued, thermal-insulating domino literal computing circuit, the signal input part of described the 3rd tri-valued, thermal-insulating domino literal computing circuit be connected the first clock signal input terminal and connect.

6. the anti-door that circulates of a kind of tri-valued, thermal-insulating domino according to claim 5, it is characterized in that described the first tri-valued, thermal-insulating domino literal computing circuit comprises literal computing module and waveform transformation module, described literal computing module is managed by a PMOS, the 2nd PMOS pipe, the 3rd PMOS pipe, the 4th PMOS pipe, the 5th PMOS pipe, the 6th PMOS pipe, the one NMOS pipe, the 2nd NMOS pipe, the 3rd NMOS pipe, the 4th NMOS pipe, the 5th NMOS pipe, the 6th NMOS pipe and the 7th NMOS pipe form, the grid of the grid of a described NMOS pipe and described the 4th NMOS pipe and connect and itself and connect end for signal input part, the drain electrode of a described NMOS pipe, the grid of the source electrode of a described PMOS pipe and described the 3rd PMOS pipe also connects, the source electrode of a described NMOS pipe is connected with the drain electrode of described the 2nd NMOS pipe, the source electrode of described the 2nd PMOS pipe is connected with the drain electrode of described the 3rd PMOS pipe, the source electrode of described the 3rd PMOS pipe, the drain electrode of the drain electrode of described the 3rd NMOS pipe and described the 7th NMOS pipe also connects, the source electrode of described the 4th PMOS pipe, the drain electrode of described the 4th NMOS pipe, the grid of the grid of described the 6th PMOS pipe and described the 7th NMOS pipe also connects, the source electrode of described the 4th NMOS pipe is connected with the drain electrode of described the 5th NMOS pipe, the source electrode of described the 5th PMOS pipe is connected with the drain electrode of described the 6th PMOS pipe, the drain electrode of the source electrode of described the 6th PMOS pipe and described the 6th NMOS pipe also connects, the grid of a described PMOS pipe, the drain electrode of described the 2nd PMOS pipe, the grid of described the 4th PMOS pipe, the drain electrode of described the 5th PMOS pipe, the grid of described the 2nd NMOS pipe, the source electrode of described the 3rd NMOS pipe, the source electrode of the grid of described the 5th NMOS pipe and described the 6th NMOS pipe is connected to the first clock signal input terminal, the drain electrode of a described PMOS pipe, the grid of described the 2nd PMOS pipe, the drain electrode of described the 4th PMOS pipe, the grid of described the 5th PMOS pipe, the source electrode of described the 2nd NMOS pipe, the grid of described the 3rd NMOS pipe, the grid of the source electrode of described the 5th NMOS pipe and described the 6th NMOS pipe is connected to the second clock signal input part, described waveform transformation module is managed by the 8th NMOS, the 9th NMOS pipe, the tenth NMOS pipe, the 11 NMOS pipe, the 12 NMOS pipe and the 13 NMOS pipe form, the drain electrode of described the 8th NMOS pipe is connected with the drain electrode of a described NMOS pipe, the source electrode of described the 8th NMOS pipe is connected with the grid of described the 9th NMOS pipe, the drain electrode of described the tenth NMOS pipe is connected with the source electrode of described the 7th NMOS pipe, the source electrode of described the tenth NMOS pipe is connected with the grid of described the 11 NMOS pipe, the drain electrode of described the 12 NMOS pipe is connected with the source electrode of described the 6th PMOS pipe, the source electrode of described the 12 NMOS pipe is connected with the grid of described the 13 NMOS pipe, the grid of described the 8th NMOS pipe, the grid of described the tenth NMOS pipe and the grid of described the 12 NMOS pipe are connected to the first clock signal input terminal, the source electrode of described the 9th NMOS pipe, the source electrode of described the 11 NMOS pipe and the source electrode of described the 13 NMOS pipe are connected to the second clock signal input part, the drain electrode of described the 9th NMOS pipe is the first signal output, the drain electrode of described the 11 NMOS pipe is the secondary signal output, the drain electrode of described the 13 NMOS pipe is the 3rd signal output part, the circuit structure of described the second tri-valued, thermal-insulating domino literal computing circuit, the circuit structure of described the 3rd tri-valued, thermal-insulating domino literal computing circuit, the circuit structure of described the 4th tri-valued, thermal-insulating domino literal computing circuit is all identical with described the first tri-valued, thermal-insulating domino literal computing circuit.

7. the anti-door that circulates of a kind of tri-valued, thermal-insulating domino according to claim 6, it is characterized in that described three value JKL trigger basic circuits comprise that the first control signal produces circuit, the second control signal produces circuit and next state signal generating circuit, described the first control signal produces circuit and is managed by the 7th PMOS, the 14 NMOS pipe, the 15 NMOS pipe, the 16 NMOS pipe, the 17 NMOS pipe, the 18 NMOS pipe, the 19 NMOS pipe and the 20 NMOS pipe form, the source electrode of described the 7th PMOS pipe, the drain electrode of described the 14 NMOS pipe, the drain electrode of described the 16 NMOS pipe and the drain electrode of described the 18 NMOS pipe and connect and itself and connect the end be the first control signal output, the source electrode of described the 14 NMOS pipe is connected with the drain electrode of described the 15 NMOS pipe, the source electrode of described the 16 NMOS pipe is connected with the drain electrode of described the 17 NMOS pipe, the source electrode of described the 18 NMOS pipe is connected with the drain electrode of described the 19 NMOS pipe, the source electrode of described the 15 NMOS pipe, the source electrode of described the 17 NMOS pipe, the source electrode of described the 19 NMOS pipe be connected the drain electrode of the 20 NMOS pipe and connect, described the second control signal produces circuit and is managed by the 8th PMOS, the 21 NMOS pipe, the 22 NMOS pipe, the 23 NMOS pipe, the 24 NMOS pipe, the 25 NMOS pipe, the 26 NMOS pipe and the 27 NMOS pipe form, the source electrode of described the 8th PMOS pipe, the drain electrode of described the 21 NMOS pipe, the drain electrode of described the 23 NMOS pipe and the drain electrode of described the 25 NMOS pipe and connect and itself and connect the end be the second control signal output, the source electrode of described the 21 NMOS pipe is connected with the drain electrode of described the 22 NMOS pipe, the source electrode of described the 23 NMOS pipe is connected with the drain electrode of described the 24 NMOS pipe, the source electrode of described the 25 NMOS pipe is connected with the drain electrode of described the 26 NMOS pipe, the source electrode of described the 22 NMOS pipe, the source electrode of described the 24 NMOS pipe, the source electrode of described the 26 NMOS pipe be connected the drain electrode of the 27 NMOS pipe and connect, described next state signal generating circuit is managed by the 9th PMOS, the tenth PMOS pipe and the 28 NMOS pipe form, the grid of described the 9th PMOS pipe is connected with described the first control signal output, the grid of described the tenth PMOS pipe is connected with described the second control signal output, the source electrode of described the 9th PMOS pipe, the drain electrode of the source electrode of described the tenth PMOS pipe and described the 28 NMOS pipe and connect and itself and connect end for signal output part, the grid of described the 14 NMOS pipe is connected with the secondary signal output of described the first tri-valued, thermal-insulating domino literal computing circuit, the grid of the 15 NMOS pipe be connected the grid of the 22 NMOS pipe and all be connected with the first signal output of described the 4th tri-valued, thermal-insulating domino literal computing circuit, the grid of described the 16 NMOS pipe is connected with the first signal output of described the second tri-valued, thermal-insulating domino literal computing circuit, the grid of described the 17 NMOS pipe be connected the grid of the 24 NMOS pipe and all be connected with the secondary signal output of described the 4th tri-valued, thermal-insulating domino literal computing circuit, the grid of described the 18 NMOS pipe is connected with the 3rd signal output part of described the 3rd tri-valued, thermal-insulating domino literal computing circuit, the grid of described the 19 NMOS pipe be connected the grid of the 26 NMOS pipe and all be connected with the 3rd signal output part of described the 4th tri-valued, thermal-insulating domino literal computing circuit, the grid of described the 21 NMOS pipe is connected with the 3rd signal output part of described the first tri-valued, thermal-insulating domino literal computing circuit, the grid of described the 23 NMOS pipe is connected with the secondary signal output of described the second tri-valued, thermal-insulating domino literal computing circuit, the grid of described the 25 NMOS pipe is connected with the first signal output of described the 3rd tri-valued, thermal-insulating domino literal computing circuit, the drain electrode of described the 7th PMOS pipe, the drain electrode of described the 8th PMOS pipe, the source electrode of described the 20 NMOS pipe, the source electrode of described the 27 NMOS pipe and the grid of described the 28 NMOS pipe are connected to the first clock signal input terminal, the grid of described the 7th PMOS pipe, the grid of described the 8th PMOS pipe, the drain electrode of described the tenth PMOS pipe, the grid of described the 20 NMOS pipe, the grid of described the 27 NMOS pipe and described the 28 NMOS pipe source electrode are connected to the second clock signal input part, and the drain electrode of described the 9th PMOS pipe is the 3rd clock signal input terminal.

8. the anti-door that circulates of each described a kind of tri-valued, thermal-insulating domino in the claim 5～7, it is characterized in that described adiabatic domino buffer managed by the 11 PMOS, the 12 PMOS pipe, the 13 PMOS pipe, the 14 PMOS pipe, the 15 PMOS pipe, the 16 PMOS pipe, the 29 NMOS pipe, the 30 NMOS pipe, the 31 NMOS pipe, the 32 NMOS pipe, the 33 NMOS pipe, the 34 NMOS pipe, the 35 NMOS pipe, the 36 NMOS pipe, the 37 NMOS pipe, the 38 NMOS pipe and the 39 NMOS pipe form, the source electrode of described the 11 PMOS pipe, the grid of described the 13 PMOS pipe be connected the drain electrode of the 29 NMOS pipe and connect, the source electrode of described the 29 NMOS pipe be connected the drain electrode of the 30 NMOS pipe and connect, the source electrode of described the 12 PMOS pipe be connected the drain electrode of the 13 PMOS pipe and connect, the source electrode of described the 13 PMOS pipe, the drain electrode of described the 31 NMOS pipe be connected the drain electrode of the 35 NMOS pipe and connect, the source electrode of described the 14 PMOS pipe, the grid of described the 16 PMOS pipe, the drain electrode of described the 32 NMOS pipe be connected the grid of the 35 NMOS pipe and connect, the source electrode of described the 32 NMOS pipe be connected the drain electrode of the 33 NMOS pipe and connect, the source electrode of described the 15 PMOS pipe be connected the drain electrode of the 16 PMOS pipe and connect, the drain electrode of described the 16 PMOS pipe, the drain electrode of described the 34 NMOS pipe be connected the drain electrode of the 38 NMOS pipe and connect, the drain electrode of described the 35 NMOS pipe be connected the drain electrode of the 36 NMOS pipe and connect, the source electrode of described the 36 NMOS pipe be connected the grid of the 37 NMOS pipe and connect, the source electrode of described the 38 NMOS pipe be connected the grid of the 39 NMOS pipe and connect, the grid of the grid of described the 29 NMOS pipe and described the 32 NMOS pipe and connect and itself and connect end for signal input part, the drain electrode of the drain electrode of described the 37 NMOS pipe and described the 39 NMOS pipe and connect and itself and connect end for signal output part, the drain electrode of described the 11 PMOS pipe, the grid of described the 12 PMOS pipe, the drain electrode of described the 14 PMOS pipe, the grid of described the 15 PMOS pipe, the source electrode of described the 30 NMOS pipe, the grid of described the 31 NMOS pipe, the source electrode of described the 33 NMOS pipe, the grid of described the 34 NMOS pipe and the source electrode of described the 39 NMOS pipe and connect and itself and connect the end be the first clock signal input terminal, the grid of described the 11 PMOS pipe, the drain electrode of described the 12 PMOS pipe, the grid of described the 14 PMOS pipe, the drain electrode of described the 15 PMOS pipe, the grid of described the 30 NMOS pipe, the source electrode of described the 31 NMOS pipe, the grid of described the 33 NMOS pipe, the source electrode of described the 34 NMOS pipe, the grid of the grid of described the 36 NMOS pipe and described the 38 NMOS pipe and connect and itself and connect end for the second clock signal input part, the source electrode of described the 37 NMOS pipe is the 3rd clock signal input terminal, the output signal of described adiabatic domino buffer is identical with its input signal, and its input signal of the output signal ratio of described adiabatic domino buffer postpones the clock cycle half, the first clock signal input terminal of described adiabatic domino buffer is connected with the first clock signal input terminal of described the first tri-valued, thermal-insulating domino literal computing circuit, the second clock signal input part of described adiabatic domino buffer is connected with the second clock signal input part of described the first tri-valued, thermal-insulating domino literal computing circuit, and the 3rd clock signal input terminal of described adiabatic domino buffer is connected with described the 4th clock signal input terminal.

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