CN102856491B - Method for forming bottom electrode and phase-change resistor - Google Patents
Method for forming bottom electrode and phase-change resistor Download PDFInfo
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- CN102856491B CN102856491B CN201110180750.8A CN201110180750A CN102856491B CN 102856491 B CN102856491 B CN 102856491B CN 201110180750 A CN201110180750 A CN 201110180750A CN 102856491 B CN102856491 B CN 102856491B
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Abstract
A method for forming a bottom electrode and a phase-change resistor includes the steps of providing a substrate; forming a first dielectric layer with the bottom electrode of which the surface is flush with the surface of the first dielectric layer on the substrate; sequentially forming a middle layer and a cap layer on the bottom electrode to cover the bottom electrode; implanting ions to the middle layer by using the cap layer as a mask, and forming outer sides with doped ions on the middle layer which is a middle portion; removing the cap layer and the outer sides; etching the bottom electrode by using the middle portion as a mask, removing height parts of the bottom electrode without being covered by the middle portion; forming a groove between the rest bottom electrode and the first dielectric layer; removing the middle portion; forming a second dielectric layer of which the surface is flush with the surface of the first dielectric layer in the groove; and forming the phase-change resistor on the rest bottom electrode. According to the technical scheme, a process is simple and is easy to control.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to the method forming bottom electrode and phase change resistor.
Background technology
Along with the development of information technology, the needs of memory device are increasing, therefore facilitate memory device towards high-performance, low pressure, low-power consumption, high speed and high density future development.Phase transition storage (PCRAM, phase change Random Access Memory) be the nonvolatile memory of new generation grown up on CMOS integrated circuit basis, it uses the alloy of one or more elements of V race or VI race in the periodic table of elements as phase change resistor, with phase change resistor as memory cell, phase change resistor, when concentrating heating with the form of electric pulse, can be unordered amorphous state (resistance is much higher) from orderly crystalline state (resistance is low) fast transition.Typical phase transition storage uses chalcogenide alloy (such as GST, GeSbTe) as phase change resistor, memory cell is a kind of minimum chalcogenide alloy particle, amorphous (the a-GST of phase change resistor, and crystallization (c-GST a-GeSbTe), c-GeSbTe) state has different resistivity, crystalline state has and is approximately kilohm typical resistances of (k Ω), and noncrystalline state has the typical resistances being approximately megohm (M Ω), therefore chalcogenide alloy materials (such as GST, GeSbTe) is usually utilized to make phase change resistor.PCRAM unit is read by the resistance value (i.e. the resistance value of phase change resistor) measuring PCRAM memory cell.
For phase transition storage, the contact area between bottom electrode and phase change resistor is less, and the performance of phase transition storage is better.Fig. 1 to Fig. 6 is the cross-sectional view that prior art forms the method for bottom electrode and phase change resistor, referring to figs. 1 to Fig. 6, the method forming bottom electrode and phase change resistor in prior art comprises: with reference to figure 1, substrate 10 is provided, substrate 10 is formed with the first medium layer 11 with bottom electrode 12; With reference to figure 2, the surface that first medium layer 11 and bottom electrode 12 are formed forms silicon oxide layer 13, silicon nitride layer 14, silicon oxide layer 15 successively, utilize silica 15 described in photoetching/etched features to form opening 151 wherein, the bottom-exposed of this opening 151 goes out silicon nitride layer 14; With reference to figure 3, deposited silicon nitride layer 16, covers the surface of described silicon oxide layer 15, the bottom of opening 151 and sidewall; With reference to figure 4, etching removes the silicon nitride layer 16 bottom silicon oxide layer 15 surface, opening 151, the silicon nitride layer 161 (being called side wall) of residue opening 151 sidewall, the sidewall due to opening 151 adds this silicon nitride layer 161, and the bore of opening 151 is reduced; With reference to figure 5, be silicon nitride layer 14 below mask etching opening 151 and silicon oxide layer 13 to have the silicon oxide layer 15 of opening 151, form through hole 17; With reference to figure 6, in through hole 17, fill phase-change material form phase change resistor 18.
Sidewall due to opening 151 adds this silicon nitride layer 161, and the bore of opening 151 is reduced, and the bore of the through hole 17 therefore formed also reduces, the reduction that such phase change resistor 18 is also just corresponding to the contact area of bottom electrode 12.But along with the development of semiconductor technology, the characteristic size of device is more and more less, reduced the very difficult control of technique of the bore of opening 151 by the method forming side wall at the sidewall of opening 151, the technique that is utilizing above-described method to form bottom electrode and the phase change resistor with little contact area is difficult to control.
Summary of the invention
The problem that the embodiment of the present invention solves is the very difficult control of technique that prior art forms bottom electrode and the phase change resistor with little contact area.
For solving the problem, the embodiment of the present invention provides a kind of method forming bottom electrode and phase change resistor, comprising:
Substrate is provided;
Form the first medium layer with bottom electrode on the substrate, the surface of described bottom electrode is equal with the surface of described first medium layer;
Described bottom electrode forms intermediate layer and cap layers successively, covers described bottom electrode;
With described cap layers for mask carries out ion implantation to described intermediate layer, forming in described intermediate layer the intermediate layer had between the outside portion of Doped ions, described outside portion is pars intermedia;
Remove described cap layers and described outside portion;
With described pars intermedia for bottom electrode described in mask etching, remove the bottom electrode of the Partial Height do not hidden by described pars intermedia, between remaining bottom electrode and described first medium layer, form groove;
Remove described pars intermedia;
In described groove, form second dielectric layer, the surface of described second dielectric layer is equal with the surface of described first medium layer;
Described remaining bottom electrode forms phase change resistor.
Alternatively, the material in described intermediate layer is silicon nitride, and the material of described cap layers is polysilicon.
Alternatively, described bottom electrode forms intermediate layer and cap layers successively, covers described bottom electrode and comprise:
Form intermediate layer, cover the surface of described first medium layer and the formation of described bottom electrode;
Form cap layers, cover described intermediate layer;
Etch described cap layers and intermediate layer successively, remove the cap layers on described first medium layer and intermediate layer.
Alternatively, the method for the described cap layers of described removal and described outside portion is: utilize wet etching to remove described cap layers and described outside portion.
Alternatively, described with the described pars intermedia method that is bottom electrode described in mask etching for: with described pars intermedia for bottom electrode described in mask dry etching.
Alternatively, the method removing described pars intermedia is wet etching.
Alternatively, describedly in described groove, form second dielectric layer, the surface of described second dielectric layer is equal with the surface of described first medium layer to be comprised:
Form second dielectric layer, fill up described groove and cover described first medium layer, remaining bottom electrode;
Remove the second dielectric layer exceeding described first medium layer surface, remain the second dielectric layer in described groove, make the surface of described second dielectric layer equal with the surface of described first medium layer.
Alternatively, the material of described first medium layer is silica.
Alternatively, the material of described bottom electrode is tungsten or copper or polysilicon.
Alternatively, the material of described second dielectric layer is silica.
Compared with prior art, the present invention has the following advantages:
The technical program, by forming intermediate layer and cap layers successively on bottom electrode, covers described bottom electrode; Be that mask carries out ion implantation to intermediate layer with cap layers, forming in intermediate layer the intermediate layer had between the outside portion of Doped ions, described outside portion is pars intermedia; Then, remove cap layers and outside portion, only remain pars intermedia; Then, take pars intermedia as bottom electrode described in mask etching, remove the bottom electrode of the Partial Height do not hidden by described pars intermedia, the area of the end face of such bottom electrode also just reduces, when forming phase change resistor afterwards on remaining bottom electrode, the contact area between phase change resistor and bottom electrode reduces.By regulating the size of the outside portion of intermediate layer being carried out to the energy hole intermediate layer of the ion of ion implantation, thus can control the area of the end face of the pars intermedia in intermediate layer, therefore technique simply, easily controls.
Accompanying drawing explanation
Fig. 1 to Fig. 6 is the cross-sectional view that prior art forms the method for bottom electrode and phase change resistor;
Fig. 7 is the schematic flow sheet of the formation bottom electrode of the specific embodiment of the invention and the method for phase change resistor;
Fig. 8 a, Fig. 8 b to Figure 16 a, Figure 16 b are cross-sectional view, the schematic top plan view of the formation bottom electrode of the specific embodiment of the invention and the method for phase change resistor.
Embodiment
The formation bottom electrode of the specific embodiment of the invention and the method for phase change resistor, by forming intermediate layer and cap layers successively on bottom electrode, cover described bottom electrode; Be that mask carries out ion implantation to intermediate layer with cap layers, forming in intermediate layer the intermediate layer had between the outside portion of Doped ions, described outside portion is pars intermedia; Then, remove cap layers and outside portion, only remain pars intermedia; Then, take pars intermedia as bottom electrode described in mask etching, remove the bottom electrode of the Partial Height do not hidden by described pars intermedia, the area of the end face of such bottom electrode also just reduces, when forming phase change resistor afterwards on remaining bottom electrode, the contact area between phase change resistor and bottom electrode reduces.By regulating the size of the outside portion of intermediate layer being carried out to the energy hole intermediate layer of the ion of ion implantation, thus can control the area of the end face of the pars intermedia in intermediate layer, therefore technique simply, easily controls.
In order to make those skilled in the art can better understand the present invention, describe the formation bottom electrode of the specific embodiment of the invention and the method for phase change resistor in detail below in conjunction with accompanying drawing.
Fig. 7 is the schematic flow sheet of the formation bottom electrode of the specific embodiment of the invention and the method for phase change resistor, and with reference to figure 7, the formation bottom electrode of the specific embodiment of the invention and the method for phase change resistor comprise:
Step S11, provides substrate;
Step S12, is formed with the first medium layer with bottom electrode on the substrate, and the surface of described bottom electrode is equal with the surface of described first medium layer;
Step S13, described bottom electrode forms intermediate layer and cap layers successively, covers described bottom electrode;
Step S14, with described cap layers for mask carries out ion implantation to described intermediate layer, forming in described intermediate layer the intermediate layer had between the outside portion of Doped ions, described outside portion is pars intermedia;
Step S15, removes described cap layers and described outside portion;
Step S16, with described pars intermedia for bottom electrode described in mask etching, removes the bottom electrode of the Partial Height do not hidden by described pars intermedia, between remaining bottom electrode and described first medium layer, forms groove;
Step S17, removes described pars intermedia;
Step S18, forms second dielectric layer in described groove, and the surface of described second dielectric layer is equal with the surface of described first medium layer;
Step S19, described remaining bottom electrode forms phase change resistor.
Fig. 8 a, Fig. 8 b to Figure 16 a, Figure 16 b are cross-sectional view, the schematic top plan view of the formation bottom electrode of the specific embodiment of the invention and the method for phase change resistor, the figure a of each picture group is the cross-sectional view of figure b along a-a direction of correspondence, below in conjunction with Fig. 7 and Fig. 8 a, Fig. 8 b to Figure 16 a, the formation bottom electrode of the detailed specific embodiment of the invention of Figure 16 b and the method for phase change resistor.
In conjunction with reference to figure 7 and Fig. 8 a, Fig. 8 b, perform step S11, substrate 30 is provided; Step S12, described substrate 30 is formed the first medium layer 31 with bottom electrode 32, and the surface of described bottom electrode 32 is equal with the surface of described first medium layer 31.It should be noted that, in the present invention, the surface of bottom electrode 32 is equal with the surface of described first medium layer 31 and do not mean that the surface of bottom electrode 32 is completely equal with the surface of described first medium layer 31, and it is not exclusively equal that the surface both allowing in certain process conditions exists certain error.In the specific embodiment of the invention, the material of substrate 30 can be monocrystalline silicon (Si), monocrystalline germanium (Ge) or SiGe (GeSi), carborundum (SiC); Also can be silicon-on-insulator (SOI), germanium on insulator (GOI); Or can also be other material, the III-V such as such as GaAs.In the specific embodiment of the invention, the material of first medium layer 31 is silica, but is not limited to silica, the other materials that can be known to the skilled person.The material of bottom electrode 32 is tungsten or copper or polysilicon, but is not limited to tungsten or copper or polysilicon, the other materials that can be known to the skilled person.The method forming bottom electrode 32 is: utilize chemical vapour deposition (CVD) or physical vapour deposition (PVD) or well known to a person skilled in the art additive method, substrate 30 is formed first medium layer 31; Utilize photoetching, the graphical first medium layer 31 of etching technics, in first medium layer 31, form through hole; Filled conductive material in through-holes afterwards, such as copper or tungsten or polysilicon, form bottom electrode 32.
In conjunction with reference to figure 7 and Figure 10 a, 10b, perform step S13, described bottom electrode 32 is formed intermediate layer 33 and cap layers 34 successively, covers described bottom electrode 32.Described bottom electrode 32 forms intermediate layer 33 successively and cap layers 34 is specially: on described bottom electrode 32, form intermediate layer 33, described intermediate layer 33 forms cap layers 34.In a particular embodiment, described bottom electrode 32 forms intermediate layer 33 and cap layers 34 successively, cover described bottom electrode 32 and comprise: with reference to figure 9a, Fig. 9 b, form intermediate layer 33, cover the surface of described first medium layer 31 and described bottom electrode 32 formation; Form cap layers 34, cover described intermediate layer 33; Etch described intermediate layer 33 and cap layers 34 successively, remove the intermediate layer on described first medium layer 31 and cap layers.The material in described intermediate layer 33 is silicon nitride, and the material of described cap layers 34 is polysilicon.
In conjunction with reference to figure 7 and Figure 11 a, Figure 11 b, perform step S14, carry out ion implantation for mask to described intermediate layer 33 with described cap layers 34, forming outside portion 331, the intermediate layer between described outside portion 331 with Doped ions in described intermediate layer 33 is pars intermedia 332.Wherein, the end face of described pars intermedia 332 has predetermined area.When carrying out ion implantation for mask to intermediate layer 33 with cap layers 34, because the end face in intermediate layer 33 is hidden by cap layers 34, therefore the ion injected can only enter in intermediate layer 33 by the side in intermediate layer 33, the lateral depth that ion enters intermediate layer 33 can be controlled by controlling the energy of ion implantation and dosage etc., the i.e. degree of depth in end face direction, parallel intermediate layer 33, the part being doped into ion is outside portion 331, and pars intermedia 332 does not have Doped ions.The predetermined area of the end face of pars intermedia 332 is determined according to actual needs, and can control by the energy of control ion implantation and dosage etc. the lateral depth that ion enters intermediate layer 33, namely controls the predetermined area of pars intermedia 332 end face.
At outside portion 331 Doped ions in intermediate layer 33, pars intermedia 332 does not have Doped ions, therefore the material behavior consistency of pars intermedia 332 and outside portion 331 is destroyed, outside portion 331 is after Doped ions, when wet etching is carried out to intermediate layer 33, outside portion 331 and pars intermedia 332 have high etching selection ratio, wet etching can be utilized to remove outside portion 331, retain pars intermedia 332.
In conjunction with reference to figure 7 and Figure 12 a, Figure 12 b, perform step S15, remove described cap layers 34 and described outside portion 331.In instantiation of the present invention, the method removing described cap layers 34 and described outside portion 331 is: utilize wet etching to remove described cap layers 34 and described outside portion 331.Wherein cap layers 34, outside portion 331 and pars intermedia 332 have high etching selection ratio, and wet etching therefore can be utilized to remove described cap layers 34 and described outside portion 331, retain pars intermedia 332.
In the specific embodiment of the invention, the material in intermediate layer 33 is silicon nitride, and the material of described cap layers 34 is polysilicon, carries out wet etching remove cap layers 34 and described outside portion 331 to intermediate layer 33 and cap layers 34.In the specific embodiment of the invention, the material in intermediate layer 33 is not limited to silicon nitride, and the material of cap layers 34 is not limited to polysilicon, as long as when meeting removal cap layers 33 and outside portion 331, cap layers 33, outside portion 331 and pars intermedia 332 have high etching selection ratio.
In conjunction with reference to figure 7 and Figure 13 a, Figure 13 b, perform step S16, with described pars intermedia 332 for bottom electrode described in mask etching 32, remove the bottom electrode 32 of the Partial Height do not hidden by described pars intermedia 332, between remaining bottom electrode 32 and described first medium layer 31, form groove 35.With described pars intermedia 332 for bottom electrode 32 described in mask dry etching, wherein, the Partial Height removing the bottom electrode 32 do not hidden by pars intermedia 332 can according to actual needs by controlling the time controling of etching.
In conjunction with reference to figure 7 and Figure 14 a, Figure 14 b, perform step S17, remove described pars intermedia 332.In the specific embodiment of the invention, the method removing described pars intermedia 332 is wet etching, but is not limited to wet etching.
In conjunction with reference to figure 7 and Figure 15 a, Figure 15 b, perform step S18, in described groove 35, form second dielectric layer 36, the surface of described second dielectric layer 36 is equal with the surface of described first medium layer 31.First medium layer 31 is with second dielectric layer 36 and non-critical is equal, allows to there is certain error in certain process conditions.Second dielectric layer 36 is formed in described groove 35, the surface of described second dielectric layer 36 is equal with the surface of described first medium layer 31 to be comprised: form second dielectric layer 36, fills up described groove 35 and covers described first medium layer 31, remaining bottom electrode 32; Remove the second dielectric layer exceeding described first medium layer 31 surface, remain the second dielectric layer 36 in described groove 35, make the surface of described second dielectric layer 36 equal with the surface of described first medium layer 31.
In conjunction with reference to figure 7 and Figure 16 a, Figure 16 b, perform step S19, described remaining bottom electrode 32 forms phase change resistor 37.The method forming phase change resistor 37 is: depositing phase change material, and cover first medium layer 31, second dielectric layer 36 and remaining bottom electrode 32, this phase-change material is chalcogenide alloy, can be Ge
xsb
yte
z(0 < x, y, z < 1, x+y+z=1), Ag-In-Sb-Te or Ge-Bi-Te, afterwards patterned phase change material residue second dielectric layer 36 and remaining bottom electrode 32 on phase-change material as phase change resistor 37.
Above-described method, the figure being positioned at cap layers 34 on bottom electrode 32 and intermediate layer 33 is strip, bottom electrode 32 on row is covered by the cap layers 34 of same strip and intermediate layer 33, therefore after ion implantation being carried out to intermediate layer 33, be doped with the outside portion 331 of ion in strip, pars intermedia 332 is in strip, and outside portion 331 is positioned at the both sides of pars intermedia 332.In other embodiments, the figure being positioned at cap layers 34 on bottom electrode 32 and intermediate layer 33 can for square, and the intermediate layer 33 on each bottom electrode 32 and cap layers 34 are separated from each other.
The foregoing is only specific embodiments of the invention; spirit of the present invention is better understood in order to make those skilled in the art; but protection scope of the present invention not with the specific descriptions of this specific embodiment for limited range; any those skilled in the art without departing from the spirit of the scope of the invention; can make an amendment specific embodiments of the invention, and not depart from protection scope of the present invention.
Claims (10)
1. form a method for bottom electrode and phase change resistor, it is characterized in that, comprising:
Substrate is provided;
Form the first medium layer with bottom electrode on the substrate, the surface of described bottom electrode is equal with the surface of described first medium layer;
Described bottom electrode forms intermediate layer and cap layers successively, covers described bottom electrode, the end face in described intermediate layer is covered by described cap layers;
With described cap layers for mask carries out ion implantation to described intermediate layer, the ion of injection can only enter in described intermediate layer by the side in intermediate layer, and to form the outside portion with Doped ions in described intermediate layer, the intermediate layer between described outside portion is pars intermedia;
Remove described cap layers and described outside portion;
With described pars intermedia for bottom electrode described in mask etching, remove the bottom electrode of the Partial Height do not hidden by described pars intermedia, between remaining bottom electrode and described first medium layer, form groove;
Remove described pars intermedia;
In described groove, form second dielectric layer, the surface of described second dielectric layer is equal with the surface of described first medium layer;
Described remaining bottom electrode forms phase change resistor.
2. the method forming bottom electrode and phase change resistor as claimed in claim 1, it is characterized in that, the material in described intermediate layer is silicon nitride, and the material of described cap layers is polysilicon.
3. the method forming bottom electrode and phase change resistor as claimed in claim 1, is characterized in that, described bottom electrode forms intermediate layer and cap layers successively, cover described bottom electrode and comprise:
Form intermediate layer, cover described first medium layer and described bottom electrode;
Form cap layers, cover described intermediate layer;
Etch described cap layers and intermediate layer successively, remove the cap layers on described first medium layer and intermediate layer.
4. the method forming bottom electrode and phase change resistor as claimed in claim 1, it is characterized in that, the method for the described cap layers of described removal and described outside portion is: utilize wet etching to remove described cap layers and described outside portion.
5. the as claimed in claim 1 method forming bottom electrode and phase change resistor, is characterized in that, described with the described pars intermedia method that is bottom electrode described in mask etching for: with described pars intermedia for bottom electrode described in mask dry etching.
6. the method forming bottom electrode and phase change resistor as claimed in claim 1, it is characterized in that, the method removing described pars intermedia is wet etching.
7. the as claimed in claim 1 method forming bottom electrode and phase change resistor, is characterized in that, describedly in described groove, forms second dielectric layer, and the surface of described second dielectric layer is equal with the surface of described first medium layer to be comprised:
Form second dielectric layer, fill up described groove and cover described first medium layer, remaining bottom electrode;
Remove the second dielectric layer exceeding described first medium layer surface, remain the second dielectric layer in described groove, make the surface of described second dielectric layer equal with the surface of described first medium layer.
8. the method forming bottom electrode and phase change resistor as claimed in claim 1, it is characterized in that, the material of described first medium layer is silica.
9. the as claimed in claim 1 method forming bottom electrode and phase change resistor, is characterized in that, the material of described bottom electrode is tungsten or copper or polysilicon.
10. the method forming bottom electrode and phase change resistor as claimed in claim 1, it is characterized in that, the material of described second dielectric layer is silica.
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| CN201110180750.8A CN102856491B (en) | 2011-06-29 | 2011-06-29 | Method for forming bottom electrode and phase-change resistor |
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| CN201110180750.8A CN102856491B (en) | 2011-06-29 | 2011-06-29 | Method for forming bottom electrode and phase-change resistor |
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| CN102856491B true CN102856491B (en) | 2015-01-21 |
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| JPS6040702B2 (en) * | 1976-10-07 | 1985-09-12 | 日本電気株式会社 | Method for manufacturing semiconductor integrated circuit device |
| JPS60735A (en) * | 1983-06-16 | 1985-01-05 | Pioneer Electronic Corp | Formation of electrode |
| JPH06735A (en) * | 1992-06-22 | 1994-01-11 | Toyoda Mach Works Ltd | Guide support device for slide body |
| TW201032370A (en) * | 2009-02-20 | 2010-09-01 | Ind Tech Res Inst | Phase change memory device and fabrications thereof |
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