CN102820340A - Shallow slot type metal oxide semiconductor diode - Google Patents
Shallow slot type metal oxide semiconductor diode Download PDFInfo
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Abstract
The invention provides a shallow slot type metal oxide semiconductor diode, belonging to the technical field of a semiconductor device. The shallow slot type metal oxide semiconductor diode provided by the invention is uniformly provided with a plurality of P-type strips which are parallel to the width direction of the entire device and arranged in an N-epitaxial layer between two deep P body areas on the basis of the conventional shallow slot type metal oxide semiconductor diode (the Chinese Patent No. 201010519680.X); and the tail parts of the P-type strips are connected with the deep P body areas on the back of the entire device in a broadened manner, or are connected with a metallic anode through shallow slot metal located on the back of the entire device, so that the P-type strips and the deep P body areas are equipotential. The two deep P body areas, the P-type strips between the two deep P body areas, and the N-epitaxial layer form a junction field effect transistor (JFET) structure. With the adoption of the shallow slot type metal oxide semiconductor diode provided by the invention, the break-over voltage drop can be further reduced; the breakdown voltage is greatly improved; and the leakage current is reduced, so that the compromise between the forward break-over voltage drop and the reverse recovery time can be realized better.
Description
Technical field
The invention belongs to technical field of semiconductor device, relate to metal-oxide-semiconductor diode.
Background technology
In electronic circuit, diode is one of the most frequently used basic device; In Power Electronic Circuit, diode is more followed someone like his shadow with switching device, and is indispensable.Conventional diode mainly contains two types of PN junction diode and Schottky diodes.Wherein PN junction diode forward conduction voltage drop is bigger, and reverse recovery time is longer, but the reliability of PN junction diode is better, can work in high pressure.Schottky diode is the metal-semiconductor junction principles utilizing metal to contact with semiconductor to form.Schottky Rectifier is only used a kind of charge carrier (electronics) delivered charge; Therefore accumulation at the no excess minority carrier in the potential barrier outside, does not exist the charge storage problem; Extremely lack (may diminish to several nanoseconds) its reverse recovery time, and forward conduction voltage drop is only about 0.4V.But because the reverse potential barrier of Schottky diode is thinner, and very easily punctures on its surface, so reverse breakdown voltage is lower, reverse withstand voltage is lower.And the temperature characterisitic of Schottky diode is relatively poor, and reverse leakage current is also big than PN junction diode.
In order to improve diode behavior; Researchers attempt to combine the advantage of PN junction diode and Schottky diode always; A series of new construction device has been proposed; As: Junction Barrier Controlled rectifier JBS (JBS:Junction Barrier Controlled Schottky Rectifier), mix PiN/ Schottky rectification MPS (MPS:Merged P-i-N/Schottky Rectifier), MOS control diode MCD devices such as (MCD:MOS Controlled Diode).
Patent " Li Zehong, Tang Wenxiong; shallow slot metal-oxide-semiconductor diode, application number: 201010519680.X " has proposed a kind of novel semiconductor diode device, in conjunction with electron accumulation layer structure and junction field tubular construction; Obtained low-down conduction voltage drop; Improved puncture voltage greatly and reduced leakage current, compared, had trading off between better forward conduction voltage drop and the reverse breakdown voltage with existing diode technologies.
Summary of the invention
The purpose of this invention is to provide a kind of shallow slot metal-oxide-semiconductor diode; The technical problem that solves is on the basis of patent " shallow slot metal-oxide-semiconductor diode "; Further reduce the reverse leakage current and the forward conduction voltage drop of diode, strengthen current handling capability.
Technical scheme of the present invention is following:
A kind of shallow slot metal-oxide-semiconductor diode, device up is metallization negative electrode 1, N type heavy doping monocrystalline substrate 2, N from bottom successively
- Epitaxial loayer 3, be positioned at N
-Dark P tagma, both sides, epitaxial loayer 3 top 4, be positioned at shallow slot metal 6 on the dark P tagma, be positioned at the inboard N type heavily doped region 7 of shallow slot metal 6, be positioned at N
-Epi-layer surface silicon dioxide gate oxide 8, be positioned at silicon dioxide gate oxide 8 surface gate electrode 9, be positioned at the metallization anode 10 of top device.Said metallization anode 10 is covered in the device top layer, contacts with gate electrode 9 with N type heavily doped region 7, and contacts with dark P tagma 4 through shallow slot metal 6; N between said two dark P tagmas 4
-Evenly distribute to such an extent that some P type bars 5 that are parallel to the entire device Width (also can be referred to as the P island, adopt the appellation on P island when hereinafter relates to here) are arranged in the epitaxial loayer 3; The afterbody of said P type bar 5 promptly links to each other with dark P tagma 4 with the mode of broadening at the back of entire device or links to each other with metallization anode 10 through the shallow slot metal 6 ' that is positioned at the entire device back, to realize P type bar 5 and P tagma 4 equipotentials deeply.
In the above-mentioned shallow slot metal-oxide-semiconductor diode, said two dark P tagmas 4 and P type bar 5 and N between the two
- Epitaxial loayer 3 forms junction field effect transistor (JFET) structure 11.The N type heavily doped region 7 of telling, silicon dioxide gate oxide 8, gate electrode 9 and near the N them
- Epitaxial loayer 3 constitutes electron accumulation layer structure 12.The concrete number of said P type bar 5 can change according to the designs demand.
The doping content in said dark P tagma 4 is greater than N
-Doping content two one magnitude of epitaxial loayer 3.
Said dark P tagma 4 shapes are rectangle, arc, semicircle, trapezoidal or oval.
Said silicon dioxide gate oxide 8 is a thin gate oxide, and its thickness range is that 5nm is to 100nm.
Said gate material is polysilicon or metal, metal nitride, metal oxide or the metal silicide with electric conductivity.
Semi-conducting material in the said shallow slot metal-oxide-semiconductor diode can adopt semi-conducting materials such as body silicon, carborundum, GaAs, indium phosphide or germanium silicon.
Beneficial effect of the present invention shows:
The present invention compared with prior art; Employing has electron accumulation layer structure and junction field tubular construction, because the gate oxide of electron accumulation layer structure is extremely thin, diode can obtain low-down conduction voltage drop; The introducing of junction field tubular construction; Improved puncture voltage greatly and reduced leakage current, thin gate oxide has quickened the pinch off of semiconductor surface conducting channel under reverse voltage, has realized forward conduction voltage drop and the compromise between reverse recovery time better.With application number is that the patent application " shallow slot metal-oxide-semiconductor diode " of 201010519680.X is compared, because the introducing on P island can further reduce the reverse leakage current and the forward conduction voltage drop of diode, strengthens current handling capability.
In order to verify beneficial effect of the present invention, the shallow slot metal oxide layer semiconductor diode that the present invention is contained the shallow slot metal-oxide-semiconductor diode on P island and do not contain the P island has carried out contrast simulation.Outside two kinds of device places dark P tagma width difference, other device parameters are all identical, and P island number is 1.Like Fig. 7 and shown in Figure 8, emulation is illustrated under the identical forward current density, and the shallow slot metal-oxide-semiconductor diode that contains the P island has lower forward conduction voltage drop.Two kinds of shallow slot metal-oxide-semiconductor diodes have same reverse breakdown characteristics.
Description of drawings
Fig. 1 is the three-dimensional structure sketch map of shallow slot metal-oxide-semiconductor diode provided by the invention.
Fig. 2 is the longitudinal cross-section sketch map of shallow slot metal-oxide-semiconductor diode provided by the invention along AA ' line among Fig. 1.
Fig. 3 .1 is a shallow slot metal-oxide-semiconductor diode provided by the invention along one of longitudinal cross-section sketch map of BB ' line among Fig. 1.
Fig. 3 .2 is a shallow slot metal-oxide-semiconductor diode provided by the invention along two of the longitudinal cross-section sketch map of BB ' line among Fig. 1.
Fig. 4 is the shallow slot metal-oxide-semiconductor diode structural representation that does not contain the P island.
More than each figure in: the 1st, the metallization negative electrode, the 2nd, N type heavy doping monocrystalline substrate, the 3rd, N
-Epitaxial loayer, the 4th, dark P tagma, the 5th, P type bar, the 6th, shallow slot metal; 6 ' is the shallow slot metal that is positioned at the entire device back, the 7th, and N type heavily doped region, the 8th, silicon dioxide gate oxide; The 9th, gate electrode, the 10th, the metallization anode, 11 is two dark P tagmas 4 and P type bar 5 and N between the two
- Epitaxial loayer 3 forms junction field effect transistor (JFET) structure, and the 12nd, N type heavily doped region 7, silicon dioxide gate oxide 8, gate electrode 9 and near the N them
-Epitaxial loayer 3 constitutes the electron accumulation layer structures, and the 13rd, do not contain in the shallow slot metal-oxide-semiconductor diode on P island two dark P tagmas 4 and the N-epitaxial loayer between it 3 and constitute jfet structures.
Fig. 5 .1 and Fig. 5 .2 are respectively the current path sketch mapes that contains the shallow slot metal-oxide-semiconductor diode on P island and do not contain the shallow slot metal oxide layer semiconductor diode on P island.
The structural representation of the shallow slot metal oxide layer semiconductor diode that Fig. 6 .1 and Fig. 6 .2 have provided the shallow slot metal-oxide-semiconductor diode that contains the P island respectively and do not contained the P island.Wherein L1 is the spacing that contains between two dark P of shallow slot metal-oxide-semiconductor diode tagma 4 on P island, and L2 is the spacing that does not contain between two dark P tagmas 4 of shallow slot metal oxide layer semiconductor diode structure on P island, and L3 is a P island width.W1 is dark P tagma 4 and N when adding 0 voltage
-The PN junction that epitaxial loayer constitutes is at N
-Width of depletion region in the epitaxial loayer, W2 are P island and N when adding 0 voltage
-The PN junction that epitaxial loayer constitutes is at N
-Width of depletion region in the epitaxial loayer.
Fig. 7 .1 and Fig. 7 .2 are respectively the forward conduction current distributing figure and the I-V performance plot of the shallow slot metal-oxide-semiconductor diode that contains the P island.
Avalanche current distribution map when Fig. 7 .3 and Fig. 7 .4 are respectively the reverse breakdown of the shallow slot metal-oxide-semiconductor diode that contains the P island with puncture the I-V performance plot.
Fig. 8 .1 and Fig. 8 .2 are respectively the forward conduction current distributing figure and the I-V performance plot of the shallow slot metal-oxide-semiconductor diode that does not contain the P island.
Avalanche current distribution map when Fig. 8 .3 and Fig. 8 .4 are respectively the reverse breakdown of the shallow slot metal-oxide-semiconductor diode that does not contain the P island with puncture the I-V performance plot.
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is done further explain.
Shown in Figure 1 is the three-dimensional structure sketch map that contains the shallow slot metal-oxide-semiconductor diode on P island of the present invention.Device up is metallization negative electrode 1, N type heavy doping monocrystalline substrate 2, N from bottom successively
-Epitaxial loayer 3, be positioned at N
-Dark P tagma, both sides, epitaxial loayer 3 top 4, be positioned at shallow slot metal 6 on the dark P tagma, be positioned at the inboard N type heavily doped region 7 of shallow slot metal 6, be positioned at N
-Epi-layer surface silicon dioxide gate oxide 8, be positioned at silicon dioxide gate oxide 8 surface gate electrode 9, be positioned at the metallization anode 10 of top device.Said metallization anode 10 is covered in the device top layer, contacts with gate electrode 9 with N type heavily doped region 7, and contacts with dark P tagma 4 through shallow slot metal 6; N between said two dark P tagmas 4
-Evenly distribute to such an extent that some P type bars 5 that are parallel to the entire device Width are arranged in the epitaxial loayer 3; The afterbody of said P type bar 5 promptly links to each other with dark P tagma 4 with the mode of broadening at the back of entire device or links to each other with metallization anode 10 through the shallow slot metal 6 ' that is positioned at the entire device back, to realize P type bar 5 and P tagma 4 equipotentials deeply.
The shallow slot metal-oxide-semiconductor diode that contains the P island of telling, as shown in Figure 2 along the longitudinal sectional drawing of AA ' line among Fig. 1.Its physical structure up is metallization negative electrode 1, N type heavy doping monocrystalline substrate 2, N from bottom successively
-Epitaxial loayer 3, be positioned at N
-The N type heavily doped region 7 of two dark P tagmas 4 of both sides, epitaxial loayer 3 top, P type bar (P island) 5, the shallow slot metal 6 that links to each other with dark P tagma 4, shallow slot metal 6 inboards, silicon dioxide gate oxide 8, gate electrode 9, metallization anode 10.Metallization anode 10 and dark P tagma 4, shallow slot metal 6, N type heavily doped region 7 and gate electrode 9 short circuits connect the anode potential of external circuit.Metallization anode 10 and dark P tagma 4 link to each other through shallow slot metal 6, and the anode 10 that metallizes has covered gate electrode 9, shallow slot metal 6 and N type heavily doped region 7.Dark P tagma 4, P island 5 and the N-epitaxial loayer between it 3 constitute a plurality of jfet structures (shown in 11).Metallize anode when external anode potential, N type heavily doped region 7, silicon dioxide gate oxide 8, polysilicon gate 9 and N
-The upper surface of epitaxial loayer 3 constitutes electron accumulation layer structure (shown in 12).
The shallow slot metal-oxide-semiconductor diode that contains the P island of telling, the metallization anode has been linked in the specific region on its P island, to realize and dark P tagma equipotential.Shown in Fig. 3 .1 or Fig. 3 .2, the mode that the P island is connected to the metallization anode has two kinds along the longitudinal sectional drawing of BB ' line among Fig. 1: the one, P type bar afterbody at the back of entire device broadening, directly link to each other (shown in Fig. 3 .1) with dark P tagma 4; The 2nd, the shallow slot metal 6 ' of the afterbody of P type bar through being positioned at the entire device back link to each other with metallization anode 10 (shown in Fig. 3 .2).The shallow slot metal 6 ' that wherein is positioned at the entire device back can adopt identical processing step to make with positive shallow slot metal 6.
The shallow slot metal-oxide-semiconductor diode operation principle on the P of containing of the present invention island: when external voltage is zero; Two dark P tagmas 4; P island 5 and N-epitaxial loayer therebetween 3 constitute a plurality of jfet structures; Each junction field tubular construction just exhausts well under the effect of PN junction internal electric field entirely, makes device be normal pass type device.During external positive voltage, the PN junction depletion region narrows down, and junction field effect transistor is opened, and contains the shallow slot MOS diode forward conduction on P island.Current path sketch map when Fig. 5 .1 has provided the shallow slot MOS diode conducting that contains the P island, electronics arrive N type heavily doped region from negative electrode three the JFET districts that under electric field action, flow through through electron accumulation layer.Current path sketch map when Fig. 5 .2 has provided the shallow slot burning diode forward conducting that does not contain the P island, electronics are from the negative electrode JFET district that under electric field action, flows through, through thin gate oxide electron accumulation layer arrival N type heavily doped region down.Because the introducing on P island can assist dark P-structure to exhaust N
-Epitaxial loayer, therefore the width of dark P-structure of the present invention has shortened, and promptly the spacing between two dark P-structure is wideer.
Shown in Fig. 6 .1 and Fig. 6 .2, the spacing of establishing between shallow slot metal-oxide-semiconductor diode (Fig. 6 .1) that contains the P island and the dark P tagma of the shallow slot metal oxide layer semiconductor diode (Fig. 6 .2) that does not contain the P island is respectively L1 and L2, and P island width is L3.It is all identical that the dark P tagma structure of two kinds of devices is removed different other parameters of width, therefore dark P tagma and N
-The PN junction that epitaxial loayer forms is positioned at N when adding the same electrical pressure
-Depletion width in the district is identical, establishes that this width of depletion region is W1 when adding no-voltage.The PN junction that P island and N-epitaxial loayer constitute is positioned at N when adding no-voltage
-Depletion width in the district is W2.When adding positive forward voltage, be positioned at N
-Depletion width in the district corresponds to W1 ', W2 '.
Two kinds of structures are all to satisfy the N-district at 0 o'clock just to exhaust entirely at applied voltage, are normal pass type device to guarantee device.Then have: L1=2W1+4W2+2L3, L2=2W1.
Containing the channel width that can flow through electric current in the shallow slot metal-oxide-semiconductor diode on P island when adding positive voltage is:
L1-2L3-2W1’-4W2’=L2-2W1’+4（W2-W2’）；
And the channel width that does not contain the shallow slot metal-oxide-semiconductor diode on P island when adding positive voltage is: L2-2W1 ';
Obviously, for the device of same unit size, add under the positive voltage identical, the channel width of shallow slot metal-oxide-semiconductor diode that contains the P island is greater than the channel width of the shallow slot metal-oxide-semiconductor diode that does not contain the P island.Therefore the shallow slot metal-oxide-semiconductor diode that contains the P island has stronger current handling capability, thereby can obtain lower conduction voltage drop.
When metallization anode 10 added reverse voltage with respect to metallization negative electrode 1, the conducting channel of jfet structure 11 was continued to increase reverse voltage by pinch off, and depletion layer is to the N of metallization negative electrode 1 one sides
- Epitaxial loayer 3 expansions, the reverse voltage of increase is mainly by low-doped N
- Epitaxial loayer 3 bears, and is reverse withstand voltage mainly by N
-The doping content of epitaxial loayer and thickness decision.Polygate electrodes connection this moment reverse voltage has quickened and the contacted N of gate oxide
-Exhausting of epitaxial loayer, thus make leakage current of the present invention be mainly dark P tagma 4 and the reverse leakage current of P island 5 with the PN junction of epitaxial loayer 3 formation, shortened reverse recovery time simultaneously.
Structure of the present invention can adopt following method to prepare, and processing step is:
1, monocrystalline silicon is prepared.Adopt N type heavy doping monocrystalline silicon (N type impurity) substrate 2, the crystal orientation is < 100 >.
2, epitaxial growth.Adopt the N of method such as meteorological extension VPE growth certain thickness and doping content
- Epitaxial loayer 3.
3, dark P tagma is injected.At the thick photoresist of whole silicon wafer surface deposition one deck 1 μ m, make the figure in dark P tagma 4 by lithography with mask plate, the high-energy boron ion injects then, and implant angle can change as requested, forms dark P tagma 4.Inject energy and DM doping content and junction depth through adjustment.
4, the P island is injected.At the thick photoresist of whole silicon wafer surface deposition one deck 1 μ m, make the figure on P island 5 by lithography with mask plate, the high-energy boron ion injects then, and implant angle can change as requested, forms P island districts identical with P tagma junction depth deeply but that concentration is different.
5, preparation grid structure.Dry oxidation growth gate oxide, deposit polysilicon gate or electric conducting material grid.
6, preparation N type heavily doped region 7.Use mask plate to make N type heavily doped region shape by lithography, and carry out heavily doped region arsenic and inject.
7, shallow slot etching.Adopt the shallow slot mask plate, etch the shallow slot of certain depth, comprise shallow slot that links to each other with dark P tagma and the shallow slot that links to each other with the P island.
8, front-side metallization anode.At entire device surface sputtering one layer thickness is the metallic aluminium of 4 μ m, and the shallow slot that links to each other with dark P tagma and the shallow slot that links to each other with the P island form metallization anode 10 all by the metal complete filling.
9, back face metalization negative electrode.At device back spatter thickness is the metallic aluminium of 4 μ m, forms metallization negative electrode 1.
The preparation process adopts 5 mask plates altogether, is followed successively by dark P tagma mask plate, P island mask, multi-crystal silicon area mask, N type heavily doped region mask, shallow slot mask plate according to the order of version number.The ion implantation process that the method for present embodiment is carried out has: dark P tagma boron injects, P island boron injects, N heavily doped region arsenic injects.
In the preparation process, can be as the case may be, under the constant situation of basic structure, carry out certain accommodation design.For example: also can do the P island earlier, do dark P tagma again.If, can make simultaneously of a mask plate if the P island is identical with dark P tagma concentration.
Semi-conducting materials such as also available carborundum, GaAs, indium phosphide or germanium silicon replace body silicon when making device.
Claims (6)
1. shallow slot metal-oxide-semiconductor diode, device up is metallization negative electrode (1), N type heavy doping monocrystalline substrate (2), N from bottom successively
-Epitaxial loayer (3), be positioned at N
-Dark P tagmas, epitaxial loayer (3) both sides, top (4), be positioned at shallow slot metal (6) on the dark P tagma, be positioned at the inboard N type heavily doped region (7) of shallow slot metal (6), be positioned at N
-Epi-layer surface silicon dioxide gate oxide (8), be positioned at silicon dioxide gate oxide (8) surface gate electrode (9), be positioned at the metallization anode (10) of top device; Said metallization anode (10) is covered in the device top layer, contacts with gate electrode (9) with N type heavily doped region (7), and contacts with dark P tagma (4) through shallow slot metal (6);
It is characterized in that the N between said two dark P tagmas (4)
-Evenly distribute to such an extent that some P type bars (5) that are parallel to the entire device Width are arranged in the epitaxial loayer (3); The afterbody of said P type bar (5) links to each other with dark P tagma (4) or links to each other with metallization anode (10) through the shallow slot metal (6 ') that is positioned at the entire device back with the mode of broadening at the back of entire device, with realization P type bar (5) and P tagma (4) equipotential deeply.
2. shallow slot metal-oxide-semiconductor diode according to claim 1 is characterized in that, the longitudinal cross-section in said dark P tagma (4) is shaped as rectangle, arc, semicircle, trapezoidal or oval.
3. shallow slot metal-oxide-semiconductor diode according to claim 1 is characterized in that, the doping content in said dark P tagma (4) is greater than N
-Doping content two one magnitude of epitaxial loayer (3).
4. shallow slot metal-oxide-semiconductor diode according to claim 1 is characterized in that, said silicon dioxide gate oxide (8) is a thin gate oxide, and its thickness range is that 5nm is to 100nm.
5. shallow slot metal-oxide-semiconductor diode according to claim 1 is characterized in that, said gate material is polysilicon or metal, metal nitride, metal oxide or the metal silicide with electric conductivity.
6. shallow slot metal-oxide-semiconductor diode according to claim 1 is characterized in that, the semi-conducting material in the said shallow slot metal-oxide-semiconductor diode adopts body silicon, carborundum, GaAs, indium phosphide or germanium silicon.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105977302A (en) * | 2016-07-06 | 2016-09-28 | 电子科技大学 | Grooved gate MOS having buried layer structure |
| CN117059654A (en) * | 2023-09-26 | 2023-11-14 | 海科(嘉兴)电力科技有限公司 | Semiconductor power device |
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| US20050077591A1 (en) * | 2003-08-29 | 2005-04-14 | Kenji Fukuda | Semiconductor device |
| CN101976687A (en) * | 2010-10-21 | 2011-02-16 | 电子科技大学 | Fast recovery metal oxide semiconductor diode with low power consumption |
| CN102064201A (en) * | 2010-10-22 | 2011-05-18 | 深圳市芯威科技有限公司 | Shallow-slot metal oxide semiconductor diode |
| CN102544114A (en) * | 2012-02-29 | 2012-07-04 | 电子科技大学 | Accumulation type grooved-gate diode |
| CN102593154A (en) * | 2012-02-29 | 2012-07-18 | 电子科技大学 | Trench gate diode with P-type buried layer structure |
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- 2012-08-31 CN CN2012103166387A patent/CN102820340A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050077591A1 (en) * | 2003-08-29 | 2005-04-14 | Kenji Fukuda | Semiconductor device |
| CN101976687A (en) * | 2010-10-21 | 2011-02-16 | 电子科技大学 | Fast recovery metal oxide semiconductor diode with low power consumption |
| CN102064201A (en) * | 2010-10-22 | 2011-05-18 | 深圳市芯威科技有限公司 | Shallow-slot metal oxide semiconductor diode |
| CN102544114A (en) * | 2012-02-29 | 2012-07-04 | 电子科技大学 | Accumulation type grooved-gate diode |
| CN102593154A (en) * | 2012-02-29 | 2012-07-18 | 电子科技大学 | Trench gate diode with P-type buried layer structure |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105977302A (en) * | 2016-07-06 | 2016-09-28 | 电子科技大学 | Grooved gate MOS having buried layer structure |
| CN117059654A (en) * | 2023-09-26 | 2023-11-14 | 海科(嘉兴)电力科技有限公司 | Semiconductor power device |
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Application publication date: 20121212 |