CN102801390B - POP noise suppression circuit in D audio frequency amplifier - Google Patents
POP noise suppression circuit in D audio frequency amplifier Download PDFInfo
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- CN102801390B CN102801390B CN201210328268.9A CN201210328268A CN102801390B CN 102801390 B CN102801390 B CN 102801390B CN 201210328268 A CN201210328268 A CN 201210328268A CN 102801390 B CN102801390 B CN 102801390B
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Abstract
The invention discloses a POP noise suppression circuit in a D audio frequency amplifier. The POP noise suppression circuit comprises a logical judgment unit, a switched capacitor amplifier, a comparator unit, a first switch, a second switch, a third switch, a first capacitor and a second capacitor. The noise suppression circuit is simple in structure and easy to implement and can be directly integrated in the applied system chip, an external stopping condenser is not required, the peripheral connection is simplified, the switched capacitor circuit has high controllability, the noise suppression time can be automatically designed so as to meet different occasions, the noise suppression circuit is not influenced by a process or a peripheral circuit and has high accuracy and can work with the protection circuit in the D audio frequency amplifier together, and the functions of short-circuit protection, thermal overload protection and undervoltage protection are realized.
Description
Technical field
The invention belongs to technical field of integrated circuits, be specifically related to a kind of for the POP noise suppression circuit in D audio frequency amplifier.
Background technology
POP noise refers to the noise produced in ubiquitous start and shutdown process in audio system.In audio system, power amplifier drives when loudspeaker or earphone and a bulky capacitor usually will be utilized as capacitance, and there is the electric capacity of power output pipe and load parasitism, need the voltage of electric capacity to charge to common mode electrical level when start, and need the tension discharge to zero in electric capacity when shutdown, when start with shutdown with regard to easy loudspeaker or earphone are impacted and form POP noise like this.In addition when full-bridge exports, even if without the need to capacitance, but because circuit both sides cannot full symmetric, so when starting or turn off, the voltage on both sides may have certain difference, thus produce pop noise, be therefore necessary to provide a kind of noise suppression circuit that effectively can suppress POP noise.
Current H bridge has been considered to effective, H bridge construction is better than half-bridge mode export structure at a lot of aspect of performance, when requiring identical power output, the noise that H bridge construction produces is less compared with half-bridge structure, mainly because the noise of H bridge is cancelled out each other with common-mode signal form, and loud speaker can not be had an impact, namely can not produce transient noise, therefore H bridge construction can play good inhibitory action for Click/Pop noise, and does not need extra operation.But due to the Non-completety symmetry of circuit, H bridge also can produce certain POP noise, need to suppress.
The method of existing suppression POP noise is by realizing chip pin design.Some audio system has a pin (Vbias or Vref etc.) providing reference voltage usually, helps circuit to set up normal working point.But when applying, the usual external bypass electric capacity of this pin is to ground, and in order to filtering noise, capacitance is larger, and effect is more obvious.If system is single power supply, the reference voltage under steady-working state is about V
dD/ 2, when chip powers on, first set up DC point, start capacitor charging until V
dD/ 2, chip normally works, and becomes capacitor discharge during chip power-down.When to the longer i.e. Vbias change of capacitor charging time slowly, the pulse amplitude of Click/Pop noise reduces, pulse stretcher, feels to be exactly that noise reduces to people's ear; Vbias power on and off process slows down, and the time of delay that reference voltage arrives stable state also increases, and plays inhibitory action to noise; Filter capacitor is larger simultaneously, better to the inhibition of noise, but the chip that excessive filter capacitor can make is long for settling time, makes people's ear " for a long time " imperceptible sound, and total harmonic distortion plus noise THD+N also can be made to be deteriorated.
Summary of the invention
The object of the invention is the problems referred to above solving the existence of existing POP noise suppression proposal, propose a kind of for the POP noise suppression circuit in D audio frequency amplifier.
Technical scheme of the present invention is: a kind of for the POP noise suppression circuit in D audio frequency amplifier, specifically comprise: logic judgment unit, switched capacitor amplifier, comparator unit, the first switch, second switch, the 3rd switch, a current source, the first electric capacity and the second electric capacity, wherein
The forward end of one termination switched capacitor amplifier of the first electric capacity, the first end of another termination first switch of the first electric capacity and the first end of second switch, the second end of the first switch is connected to ground through a current source lotus root, the second end ground connection of second switch; One termination switched capacitor amplifier forward end of the second electric capacity and the second end of the 5th switch, second end of another termination switched capacitor amplifier output of the second electric capacity, the 4th switch, the second end of the 3rd switch and the forward end of comparator unit, switched capacitor amplifier negative end ground connection, the equal ground connection of first end of the first end of the 3rd switch, the first end of the 4th switch, the 5th switch, compares buffer negative sense termination reference voltage; Described comparator unit, for comparing switched capacitor amplifier output signal and the size of reference voltage, exports the first clamp signal, the second clamp signal and the 3rd signal; The first clamp signal that comparator unit exports, the second clamp signal are input in the preamplifier in described D audio frequency amplifier;
Described Logic judgment judging unit has four inputs, the guard signal that the 3rd signal of input comparator unit output respectively, switched capacitor amplifier output signal, outside enable signal, described D audio frequency amplifier export;
Described Logic judgment judging unit has four outputs, exports the first switching signal, second switch signal, the 3rd switching signal and gate driving control signal respectively;
The logical relation of four described input signals and four output signals is:
Enable signal when outside is high level, or when guard signal is high level, gate driving control signal is high level, 3rd switching signal is high level, switched capacitor amplifier output signal is low level, the 3rd signal that comparator unit exports is low level, and the first switching signal and second switch signal are the complementary clock signal produced based on described D audio frequency amplifier system clock;
When the enable signal of outside, when guard signal is low level, through the time preset, gate driving control signal and the 3rd switching signal become low level from high level, first clock cycle after saltus step, first switching signal is high level, second switch signal is low level, the logical signal that switched capacitor amplifier exports is low level, the 3rd signal that comparator unit exports is low level, second clock cycle, first switching signal is low level, second switch signal is high level, until switched capacitor amplifier output signal becomes high level, the 3rd signal that comparator unit exports becomes high level, first switching signal is high level, second switch signal is low level,
The first described switching signal connects the control end of the first switch and the control end of the 5th switch for controlling the first switch, the 5th switch, second switch signal connects the control end of second switch and the control end of the 4th switch for controlling second switch, the 4th switch, and the 3rd switching signal connects the control end of the 3rd switch for controlling the 3rd switch.
Beneficial effect of the present invention: the structure of POP noise suppression circuit of the present invention is simple, be easy to realize, this circuit can directly be integrated in applied System on Chip/SoC, do not need the capacitance that chip is additional, simplify peripheral connection, have employed switched-capacitor circuit, there is good controllability, can the length of designed, designed restraint speckle time to be adapted to different application occasion, and be not subject to the impact of technique or peripheral circuit, there is very high accuracy, this circuit can work together with protective circuit in D audio frequency amplifier, realize short-circuit protection simultaneously, the function such as thermal overload protection and under-voltage protection, enrich the function in D audio frequency amplifier.
Accompanying drawing explanation
Fig. 1 is the structural representation of POP noise suppression circuit of the present invention.
Fig. 2 is the structural representation of the D audio frequency amplifier adopting POP noise suppression circuit of the present invention.
Fig. 3 is the structural representation of logic judgment unit in embodiment.
Fig. 4 is the structural representation that in embodiment, comparator unit is shown.
Fig. 5 is that in embodiment, POP noise suppression circuit triggers POP inhibit feature logic timing figure powering on.
Fig. 6 is the logic timing figure of POP noise suppression circuit when protection system in embodiment.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described further.
The structural representation of POP noise suppression circuit of the present invention as shown in Figure 1, specifically comprise: logic judgment unit, switched capacitor amplifier, comparator unit, the first switch sw1, second switch sw2, the 3rd switch sw3, the 4th switch sw4, the 5th switch sw5, a current source, the first electric capacity C1 and the second electric capacity C2, wherein
The forward end of the one termination switched capacitor amplifier of the first electric capacity C1, the first end b of another termination first switch sw1 of the first electric capacity C1 and the first end b of second switch sw2, the second end a of the first switch sw1 is connected to ground through a current source lotus root, the second end ground connection of second switch sw2, the one termination switched capacitor amplifier forward end of the second electric capacity C2 and the second end a of the 5th switch sw5, another termination switched capacitor amplifier output of second electric capacity C2, the second end a of the 4th switch sw4, second end a and the forward end comparing buffer of the 3rd switch sw3, switched capacitor amplifier negative end ground connection, the first end b of the 3rd switch sw3, the first end b of the 4th switch sw4, the equal ground connection of first end b of the 5th switch sw5, relatively buffer negative sense termination reference voltage, comparator unit is for comparing the size of switched capacitor amplifier output signal and reference voltage, export the first clamp signal CP1, second clamp signal CP2 and the 3rd signal COM_OUT, clamp signal CP1, CP2 that comparator unit exports are input in the preamplifier in described D audio frequency amplifier,
Described Logic judgment judging unit has four inputs, the guard signal that the 3rd signal COM_OUT of input comparator unit output respectively, switched capacitor amplifier output signal, outside enable signal, described D audio frequency amplifier export,
Described Logic judgment judging unit has four outputs, exports the first switching signal, second switch signal, the 3rd switching signal and gate driving control signal respectively;
The logical relation of four described input signals and four output signals is:
1, the enable signal when outside is high level, or when guard signal is high level, gate driving control signal is high level, 3rd switching signal is high level, switched capacitor amplifier output signal SC_OUT is low level, comparator unit output signal COM_OUT is low level, and the first switching signal S1 is clock signal, and second switch signal S2 is the clock signal with S1 complementation;
2, when the enable signal of outside, when guard signal is low level, through the time preset, set 30us in the present embodiment, gate driving control signal L_CON and the 3rd switching signal S3 becomes low level from high level, first clock cycle after saltus step, first switching signal S1 is high level, second switch signal S2 is low level, switched capacitor amplifier output signal SC_OUT is low level, comparator unit output signal COM_OUT is low level, second clock cycle, first switching signal S1 is low level, second switch signal S2 is high level, until switched capacitor amplifier output signal SC_OUT becomes high level, comparator unit output signal COM_OUT becomes high level, first switching signal S1 is high level, second switch signal S2 is low level.
Those skilled in the art it should be appreciated that according to above-mentioned logical relation, can design any type of logic judgment unit module.
Here, first switching signal connects the control end of the first switch and the control end of the 5th switch for controlling the first switch, the 5th switch, second switch signal connects the control end of second switch and the control end of the 4th switch for controlling second switch, the 4th switch, and the 3rd switching signal connects the control end of the 3rd switch for controlling the 3rd switch.
Here, the first switch sw1 can be realized by the first NMOS tube, and the drain electrode of the first NMOS tube is held as a of the first switch sw1, and the source electrode of the first NMOS tube is held as the b of the first switch sw1, and the grid of the first NMOS tube is held as the c of the first switch sw1; Second switch sw2 can be realized by the second NMOS tube, and the source electrode of the second NMOS tube is held as a of second switch sw2, and the drain electrode of the second NMOS tube is held as the b of second switch sw2, and the grid of the second NMOS tube is held as the c of second switch sw2; 3rd switch sw3 can be realized by the 3rd NMOS tube, and the drain electrode of the 3rd NMOS tube is held as a of the 3rd switch sw3, and the source electrode of the 3rd NMOS tube is held as the b of the 3rd switch sw3, and the grid of the 3rd NMOS tube is held as the c of the 3rd switch sw3; 4th switch sw4 can be realized by the 4th NMOS tube, and the source electrode of the 4th NMOS tube is held as a of the 4th switch sw4, and the drain electrode of the 4th NMOS tube is held as the b of the 4th switch sw4, and the grid of the 4th NMOS tube is held as the c of the 4th switch sw4; 5th switch sw5 can be realized by the 5th NMOS tube, and the drain electrode of the 5th NMOS tube is held as a of the 5th switch sw5, and the source electrode of the 5th NMOS tube is held as the b of the 5th switch sw5, and the grid of the 5th NMOS tube is held as the c of the 5th switch sw5.
Adopt the D audio frequency amplifier of POP noise suppression circuit of the present invention as shown in Figure 2; comprise: preamplifier, integrator circuit, PWM circuit, raster data model, POP noise suppression circuit, power output grade circuit and protective circuit, also comprise LC filter circuit simultaneously.With reference to Fig. 2, input audio signal is by after the pre-amplification of prestage, error amplification and High frequency filter is carried out with the square-wave signal fed back from output in integrator, be output to PWM circuit afterwards, the square-wave signal that output duty cycle changes with audio signal after sawtooth wave modulation is to gate driver circuit, at gate driver circuit, necessary optimization rear drive output power stage is carried out, by driving acoustic element after filter to square-wave signal.On the other hand; POP noise suppression circuit is outputted to after the working condition of protective circuit detection power output stage; powering on/power down time, POP noise suppression circuit is started working, and first turns off gate driver circuit; when systemic bias is after normal operating state; gate driver circuit is started working, and the signal input part of clamp system, makes not output signal generation simultaneously; after the time delay of 18ms, system starts normal work.
When powering on, POP noise suppression circuit is started working, first the gate driver circuit of D audio frequency amplifier is turned off, when having powered on, the control to gate driver circuit is cancelled after the delay of 30us, POP noise produces the input amplifier of signal clamp system subsequently, make it to enter system without differential input signal, and now modulator bias voltage is arranged on correct level by internal loop, avoid producing POP noise when starting H bridge, after starting 18ms, POP Noise Circuits removes the mute state of input amplifier gradually, and system enters normal operating conditions.
The system configuration that preamplifier in D audio frequency amplifier, integrator, PWM circuit, gate driver circuit and power output stage can adopt those skilled in the art to commonly use, does not therefore elaborate.
Fig. 3 gives a kind of structure of logic judgment unit; its input signal comprises enable signal and guard signal; output signal comprises switching signal S1, S2; for switched-capacitor circuit provides the sequential chart Logic judgment S3 signal whether switching capacity works, and control audio system gate driving control signal L_CON.Specifically comprise: NMOS tube MN6, MN7, a current source IB, an electric capacity C0, an inverter NV1 and logic control subelement, wherein, the drain electrode of MN6, the drain electrode of MN7 and electric capacity C0 one end and inverter NV1 input are connected, and are connected to supply voltage through a current source IB lotus root; The source electrode of MN6, the source electrode of MN7 and the electric capacity C0 other end are connected to earth potential.The grid of MN6 connects guard signal, and the grid of MN7 connects enable signal; Inverter NV1 output is gate driving control signal L_CON, and be linked into Logic judgment subelement, two other input signal of Logic judgment subelement is comparator unit output signal COM_OUT and switched capacitor amplifier output signal SC_OUT, output signal is the first switching signal S1, second switch signal S2, the 3rd switching signal S3.
Logic control subelement is for realizing following logic function:
1, when gate driving control signal is high level, 3rd switching signal S3 is high level, switched capacitor amplifier output signal SC_OUT is low level, comparator unit output signal COM_OUT is low level, first switching signal S1 is clock signal, and second switch signal S2 is the clock signal with S1 complementation.
2, when gate driving control signal L_CON and the 3rd switching signal S3 becomes low level from high level, first clock cycle after saltus step, first switching signal S1 is high level, second switch signal S2 is low level, switched capacitor amplifier output signal SC_OUT is low level, comparator unit output signal COM_OUT is low level, second clock cycle, first switching signal S1 is low level, second switch signal S2 is high level, until switched capacitor amplifier output signal SC_OUT becomes high level, comparator unit output signal COM_OUT becomes high level, first switching signal S1 is high level, second switch signal S2 is low level.
First logic judgment unit judges whether to carry out the action of POP noise suppressed.When there being POP noise, MN6 or MN7 opens, and bias current flows to the branch road of MN6 or MN7, and after inverter, exporting L_CON signal is high level, turns off the gate driver circuit of D class audio frequency system; Determine when integrator starts working together according to L_CON and SC_OUT signal simultaneously, the two can produce signal S3 by multiple logical design, being limited to a certain fixing structure, (logical relation is not wherein: L_CON=" 1 ", S3=" 1 ", opens the action of POP noise suppressed; L_CON=" 0 ", S3=" 1 ", bias current charges to electric capacity C0; L_CON=" 0 ", S3=" 0 ", switching capacity is started working).Same, the frequency that complementary clock produces signal is switching frequency, and production method can with reference to present already present mode.
When before system electrification and enable unlatching, logic judgment unit provides signal L_CON, to the grid electrode drive module of the D class audio frequency amplification system of Fig. 2, when L_CON is high potential, turn off drive circuit, open POP noise suppressing function.In this circuit arrangement, produce high level and have two kinds of situations.When system is enable do not open time, enable signal is high level, and MN7 opens, and makes L_CON be that high potential triggers the action of POP noise suppressed; Another kind of situation; when a chip is powering up; because the charging of each node is too late; make the under-voltage signal (under-voltage signal) in protective circuit effective; MN6 is opened; can trigger L_CON signal equally for high and make the action of system triggers POP noise suppressed, logic judgment unit also can provide required clock signal for switched-capacitor circuit simultaneously.After System recover is normal, MN6, MN7 turn off, and constant-current source charges to electric capacity C0, and L_CON becomes low, and S3 signal becomes low, and switching capacity is started working.
Switched capacitor amplifier, the first switch sw1 constitute switched-capacitor circuit to the 5th switch sw5, electric capacity C1 and electric capacity C2.Switched capacitor amplifier provides time enough to make the internal loop of system set up correct level for system, relatively general delay circuit, the time of switched-capacitor circuit is more accurate, and traditional RC delay circuit, its time constant is subject to the impact of technique and temperature, and the time constant of switched-capacitor circuit is the ratio of two electric capacity.According to the analysis of logic judgment unit, when before system electrification and enable unlatching, L_CON signal is high potential, now produce and start the action of POP noise suppressed, S3 signal is high potential, switching capacity does not now work, by the time System recover is normal, and S3 signal becomes low, and switching capacity is started working, the course of work of S1, S2 control switch electric capacity, S1=' 1 ', S2=' 0 ', bias current charges to electric capacity C1; S1=' 0 ', S2=' 1 ', is stored in Charger transfer in C1 in C2, SC_OUT is increased gradually, outputs to comparator unit.
Fig. 4 gives a kind of structure of comparator unit, specifically comprises: a comparator, a not gate, two buffers, wherein, comparator be input as SC_OUT and reference voltage, export COM_EN signal and be connected to the input of not gate and the input of two buffers.Another input signal of first buffer is reference voltage, exports clamp signal CP1; Another input signal of second buffer is reference voltage, and export clamp signal CP2, the output of not gate is COM_OUT signal.
Comparator makes SC_OUT compare with reference voltage, and comparator is wherein conventional comparator, the simple fireballing structure of usual choice structure, and buffer completes the buffering to comparator output signal, to reduce the impact on preamplifier.
Produce the action of POP noise suppressed when system electrification or enable unlatching, SC_OUT signal is input to comparator unit, compares with reference voltage.This circuit forms primarily of two parts, be respectively comparator and buffering follower, when SC_OUT is less than reference voltage, COM_EN signal makes two buffers start working, COM_OUT output low level, and outputs to logic judgment unit participation logical transition, integrator is worked on, because buffer makes output clamp signal CP1 now and CP2 output reference voltage, in order to the preposition amplifier of clamper, audio signal is made not enter into loop.When SC_OUT is greater than reference voltage, COM_OUT exports high level, and logic judgment unit exports shutdown switch electric capacity S1=' 1 ', S2=' 0 ' turns off integrator, and moves SC_OUT to height rapidly, and it is clamped that CP1 and CP2 cancels output, chip enters normal operating conditions, approximately lasts 18ms.
The defencive function of system is also by POP noise suppression circuit control realization, when guard signal enable effective time (system occur abnormal) time, protective circuit is enable is high level, (now enable signal is low level in MN6 unlatching, MN7 turns off), triggering L_CON signal is high level, turn off logic judgment unit and power tube, when guard signal enable invalid time (System recover is normal), before chip starts to continue normal work, turn off MN6, bias current charges to electric capacity C0, after waiting for the time delay of about 30us, L_CON becomes low, logic judgment unit and power tube normally work.
Fig. 5 is at supply voltage 3.3V, the logic relation picture at 25 DEG C.When just powering on, enter POP noise suppressed pattern, S3 is low level, switching capacity work, SC_OUT voltage raises gradually, compares buffer and exports the preposition amplifier of CP1, CP2 clamper, through about 18ms, SC_OUT is pulled to high level, removes the mute state of preposition amplifier, starts normally to work.
Be illustrated in figure 6 when system is elevated to certain value in temperature; in order to protect power tube to be burnt, circuit can make guard signal export as high, and now POP noise suppression circuit is started working; export gate driver circuit; when the enable output of guard signal is low, system can normally work, before recovery normal operating conditions; after L_OUT maintenance high level is about 30us; release grid electrode drive module, starts task again, coincide with design result.
Those of ordinary skill in the art will appreciate that, embodiment described here is to help reader understanding's principle of the present invention, should be understood to that protection scope of the present invention is not limited to so special statement and embodiment.Those of ordinary skill in the art can make various other various concrete distortion and combination of not departing from essence of the present invention according to these technology enlightenment disclosed by the invention, and these distortion and combination are still in protection scope of the present invention.
Claims (4)
1. for the POP noise suppression circuit in D audio frequency amplifier, specifically comprise: logic judgment unit, switched capacitor amplifier, comparator unit, the first switch, second switch, the 3rd switch, the first electric capacity and the second electric capacity, wherein,
The forward end of one termination switched capacitor amplifier of the first electric capacity, the first end of another termination first switch of the first electric capacity and the first end of second switch, the second end of the first switch is connected to ground through a current source lotus root, the second end ground connection of second switch; One termination switched capacitor amplifier forward end of the second electric capacity and the second end of the 5th switch, second end of another termination switched capacitor amplifier output of the second electric capacity, the 4th switch, the second end of the 3rd switch and the forward end of comparator unit, switched capacitor amplifier negative end ground connection, the equal ground connection of first end of the first end of the 3rd switch, the first end of the 4th switch, the 5th switch, compares buffer negative sense termination reference voltage; Described comparator unit, for comparing switched capacitor amplifier output signal and the size of reference voltage, exports the first clamp signal, the second clamp signal and the 3rd signal; The first clamp signal that comparator unit exports, the second clamp signal are input in the preamplifier in described D audio frequency amplifier;
Described Logic judgment judging unit has four inputs, the guard signal that the 3rd signal of input comparator unit output respectively, switched capacitor amplifier output signal, outside enable signal, described D audio frequency amplifier export;
Described Logic judgment judging unit has four outputs, exports the first switching signal, second switch signal, the 3rd switching signal and gate driving control signal respectively;
The logical relation of four described input signals and four output signals is:
Enable signal when outside is high level, or when guard signal is high level, gate driving control signal is high level, 3rd switching signal is high level, switched capacitor amplifier output signal is low level, the 3rd signal that comparator unit exports is low level, and the first switching signal and second switch signal are the complementary clock signal produced based on described D audio frequency amplifier system clock;
When the enable signal of outside, when guard signal is low level, through the time preset, gate driving control signal and the 3rd switching signal become low level from high level, first clock cycle after saltus step, first switching signal is high level, second switch signal is low level, the logical signal that switched capacitor amplifier exports is low level, the 3rd signal that comparator unit exports is low level, second clock cycle, first switching signal is low level, second switch signal is high level, until switched capacitor amplifier output signal becomes high level, the 3rd signal that comparator unit exports becomes high level, first switching signal is high level, second switch signal is low level,
The first described switching signal connects the control end of the first switch and the control end of the 5th switch for controlling the first switch, the 5th switch, second switch signal connects the control end of second switch and the control end of the 4th switch for controlling second switch, the 4th switch, and the 3rd switching signal connects the control end of the 3rd switch for controlling the 3rd switch.
2. POP noise suppression circuit according to claim 1, is characterized in that,
The first described switch is realized by the first NMOS tube, and the source electrode of the first NMOS tube is as the first end of the first switch, and the drain electrode of the first NMOS tube is as the second end of the first switch, and the grid of the first NMOS tube is as the control end of the first switch;
Or described second switch is realized by the second NMOS tube, the drain electrode of the second NMOS tube is as the first end of second switch, and the source electrode of the second NMOS tube is as the second end of second switch, and the grid of the second NMOS tube is as the control end of second switch;
Or the 3rd switch is realized by the 3rd NMOS tube, the source electrode of the 3rd NMOS tube is as the first end of the 3rd switch, and the drain electrode of the 3rd NMOS tube is as the second end of the 3rd switch, and the grid of the 3rd NMOS tube is as the control end of the 3rd switch;
Or the 4th switch is realized by the 4th NMOS tube, the drain electrode of the 4th NMOS tube is as the first end of the 4th switch, and the source electrode of the 4th NMOS tube is as the second end of the 4th switch, and the grid of the 4th NMOS tube is as the control end of the 4th switch;
Or the 5th switch is realized by the 5th NMOS tube, the source electrode of the 5th NMOS tube is as the first end of the 5th switch, and the drain electrode of the 5th NMOS tube is as the second end of the 5th switch, and the grid of the 5th NMOS tube is as the control end of the 5th switch.
3. POP noise suppression circuit according to claim 1 and 2, it is characterized in that, described logic judgment unit specifically comprises: the 6th NMOS tube, 7th NMOS tube, one current source, one electric capacity, one inverter and logic control subelement, wherein, the drain electrode of the 6th NMOS tube, the drain electrode of the 7th NMOS tube is connected with one end of electric capacity and the input of inverter, and be connected to supply voltage through described current source lotus root, the source electrode of the 6th NMOS tube, the source electrode of the 7th NMOS tube and the other end of electric capacity are connected to earth potential, 6th NMOS tube grid is used for input protection signal as the first input end of logic judgment unit, 7th NMOS tube grid as the second input of logic judgment unit for inputting enable signal, inverter NV1 output exports gate driving control signal, and be input to logic control subelement, two other input signal of logic control subelement is the 3rd signal and the switched capacitor amplifier output signal of comparator unit output, output signal is the first switching signal, second switch signal, the 3rd switching signal,
Described logic control subelement is for realizing following logic function:
When gate driving control signal is high level, 3rd switching signal S3 is high level, switched capacitor amplifier output signal is low level, the 3rd signal that comparator unit exports is low level, first switching signal is clock signal, and second switch signal S2 is the clock signal with the first switching signal complementation;
When gate driving control signal and the 3rd switching signal become low level from high level, first clock cycle after saltus step, first switching signal is high level, second switch signal is low level, switched capacitor amplifier output signal is low level, and the 3rd signal that comparator unit exports is low level; Second clock cycle, the first switching signal is low level, and second switch signal is high level, until switched capacitor amplifier output signal becomes high level, comparator unit output signal becomes high level, and the first switching signal is high level, and second switch signal is low level.
4. POP noise suppression circuit according to claim 3, it is characterized in that, described comparator unit specifically comprises: a comparator, one not gate, two buffers, wherein, the forward end of comparator and negative end are respectively as the forward end of described comparator unit and negative end, the output of comparator is connected to the input of not gate and an input of two buffers, the reference voltage of another input termination outside of the first buffer and the second buffer, first buffer exports the first clamp signal, second buffer exports the second clamp signal, the 3rd signal that the signal of the output of not gate exports as comparator unit.
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| CN103067824A (en) * | 2012-12-25 | 2013-04-24 | 青岛盛嘉信息科技有限公司 | Audio frequency amplifier eliminating starting noise |
| CN108449057A (en) * | 2013-09-12 | 2018-08-24 | 意法半导体研发(深圳)有限公司 | The method and circuit of POP noises are removed in audio frequency apparatus |
| US9503023B2 (en) * | 2015-04-01 | 2016-11-22 | Nxp B.V. | Class-D amplifier |
| CN105119574B (en) * | 2015-08-20 | 2018-03-30 | 深圳创维－Rgb电子有限公司 | D class power amplifiers with POP noise suppresseds |
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| WO2006087870A1 (en) * | 2005-02-17 | 2006-08-24 | Rohm Co., Ltd | Audio signal amplifying circuit and electronic device using the same |
| CN1866728A (en) * | 2005-05-17 | 2006-11-22 | 波速数码科技有限公司 | Digital amplifier, pulse width modulator thereof and method for reducing pop noise for the same |
| CN101005268A (en) * | 2005-12-21 | 2007-07-25 | 国际整流器公司 | Class D amplifier with start-up click noise elemination |
| CN101465619A (en) * | 2007-12-20 | 2009-06-24 | 杭州茂力半导体技术有限公司 | Method and apparatus for restraining D-genus power amplifier noise and D-genus power amplifier with noise suppression |
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| CN102801390A (en) | 2012-11-28 |
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