CN108076417B

CN108076417B - Output stage circuit

Info

Publication number: CN108076417B
Application number: CN201611028140.5A
Authority: CN
Inventors: 杨松辑
Original assignee: Ali Corp
Current assignee: Ali Corp
Priority date: 2016-11-18
Filing date: 2016-11-18
Publication date: 2020-09-01
Anticipated expiration: 2036-11-18
Also published as: US20180145638A1; CN108076417A; US10158332B2

Abstract

The invention is an output stage circuit, comprising: amplifier module, switching circuit and selection circuit. The amplifier module has an output, and the amplifier module converts an input signal to an output signal. The switch circuit is coupled between the output end and the grounding end. The selection circuit includes: a first mode selection unit and a second mode selection unit. The first mode selection unit receives the first control signal and takes the first control signal as the switching signal when the power detection signal is at the first level, so as to selectively turn on the switch circuit. The second mode selection unit is provided with a storage capacitor, and when the power supply detection signal is at a second level, the voltage stored in the storage capacitor is used as a switching signal to conduct the switch circuit, so that the output end of the amplifier module is grounded. Wherein the first level is higher than the second level.

Description

Output stage circuit

[ technical field ] A method for producing a semiconductor device

The present invention relates to an output stage circuit, and more particularly, to an output stage circuit for audio output.

[ background of the invention ]

Many electronic products have a multimedia playing function and therefore have an audio chip. The audio chip outputs audio to the loudspeaker through the output stage circuit. However, when the power supply is suddenly turned off during the shutdown process of the electronic product, Pop Noise (Pop Noise) may occur due to the residual charge of the output stage circuit being output to the speaker. Once a pop occurs, the user's auditory experience will be affected.

Therefore, how to avoid the pop phenomenon generated when the power of the electronic product is turned off is one of the directions of the industry.

[ summary of the invention ]

The invention relates to an output stage circuit which can effectively avoid the sound burst of an audio chip caused by the influence of sudden power failure.

According to one embodiment, an output stage circuit is provided. The output stage circuit comprises an amplifier module, a switch circuit and a selection circuit. The amplifier module has an output end, and the amplifier module converts an input signal into an output signal. The switch circuit is coupled between the output end and the ground end. The selection circuit comprises a first mode selection unit and a second mode selection unit. The first mode selection unit receives the first control signal and takes the first control signal as a switching signal when the power detection signal is at a first level, so as to selectively turn on the switch circuit. The second mode selection unit has a storage capacitor. When the power detection signal is at the second level, the second mode selection unit takes the voltage stored in the storage capacitor as a switching signal to conduct the switch circuit, so that the output end of the amplifier module is grounded. Wherein the first level is higher than the second level.

In order to better appreciate the above and other aspects of the present invention, reference will now be made in detail to the embodiments of the present invention, examples of which are illustrated in the accompanying drawings. However, the scope of the present invention should be determined by the appended claims.

[ description of the drawings ]

Fig. 1 is a schematic diagram of an output stage circuit of an audio chip.

FIG. 2 is a waveform diagram of signals related to an output stage circuit when the electronic device is turned off by using the audio chip shown in FIG. 1.

Fig. 3 is a circuit diagram of an output stage according to an embodiment of the invention.

Fig. 4 is a diagram illustrating waveforms of signals related to an output stage circuit according to an embodiment of the invention.

Fig. 5 is a schematic diagram illustrating an output stage circuit according to an embodiment of the invention, when the power detection signal is at a high level, the selection circuit selects the first mode selection unit to generate the switching signal Ssw.

Fig. 6 is a schematic diagram illustrating an output stage circuit according to an embodiment of the invention, when the power detection signal is at a low level, the selection circuit selects the second mode selection unit to generate the switching signal Ssw.

FIG. 7 is a circuit diagram of an output stage according to another embodiment of the present invention.

FIG. 8 is a circuit diagram of an output stage according to another embodiment of the present invention.

[ notation ] to show

Circle selected C1, C2, C3 audio chip 1

Output stage circuit

10, 30, 50, 60

Amplifier module

11, 31, 51

Switching

circuits

13, 33, 53

Control logic

18, 38, 58 disables signal Vdis

Input signal AUDin output signal AUDout

Loudspeaker 17 input node Nin

Output node Nout switching signal Ssw

Power supply detection signal PALT

Amplifier enable

circuits

361, 362

Enabling

units

361a, 362a and disabling

units

361b, 362b

Selection circuits 35, 45

First

mode selection units

351, 551, 651

Second

mode selection units

352, 552, 652

Sampling node Nsam storage capacitor Csam

Sampling voltage Vsam

First transistors T1, T1', T1 "

Second transistors T2, T2', T2 "

Third transistors T3, T2', T3 "

Second control signal AUDctrl1

Third control signal AUDctrl2

The

multiplexers

46a, 46b, 56a, 56b, 66a, 66b

Amplifier enable signals ENamp1, ENamp2

Power supply detection circuit 59

Amplifiers

511, 512

Fourth transistor T4 'fifth transistor T5'

[ detailed description ] embodiments

Please refer to fig. 1, which is a schematic diagram of an output stage circuit of an audio chip for explaining a cause of pop. The audio chip 1 is connected to a speaker 17. The output stage circuit 10 includes an amplifier module 11 and a switch circuit 13. The amplifier module 11 has an output terminal and converts an input signal AUDin into an output signal AUDout. The output terminal of the amplifier module 11 is coupled to the output node Nout of the output stage circuit 10.

The amplifier module 11 is controlled by an amplifier enable signal ENamp to be in an enable (enable) state or a disable (disable) state. When the amplifier module 11 is enabled, the amplifier module 11 converts (e.g., amplifies) the input signal AUDin at the input node Nin and generates the output signal AUDout at the output node Nout. The amplifier module 11 also has a function of low-frequency filtering the input signal AUDin.

The switch circuit 13 is coupled to the amplifier module 11. The switch circuit 13 is controlled by a switching signal Ssw of a control logic (control logic) circuit 18. When the switching signal Ssw is at a high level, the switch circuit 13 is turned on; when the switching signal Ssw is at a low level, the switch circuit 13 is turned off.

When the switch circuit 13 is turned on, the ground voltage Gnd is transmitted to the output node Nout via the switch circuit 13, and the potential of the output node Nout is set to the ground voltage Gnd. At this time, the speaker 17 does not emit the reproduced audio because the output signal AUDout is the ground voltage Gnd.

When the switch circuit 13 is turned off, the level of the output node Nout is the output signal AUDout generated by the amplifier module 11. At this time, the speaker 17 emits play audio in accordance with the output signal AUDout.

When the audio chip 1 receives a command to shut down or detects a power interruption, the audio decoder (audio decoder) of the audio chip 1 transmits a set of special mute pattern waveforms (mute patterns) to the input node Nin of the output stage circuit 10, thereby informing the output stage circuit 10 that the output node Nout should be adjusted to 0V.

Along with the generation of the mute mode waveform, the switching signal Ssw is raised from a low level to a high level. In conjunction, the switch circuit 13 thus conducts the ground voltage Gnd to the output node Nout, so that the potential of the output node Nout is the ground voltage Gnd. In conjunction with this, the speaker 17 stops emitting the reproduced audio because the potential of the output node Nout is the ground voltage Gnd.

Please refer to fig. 2, which is a waveform diagram of signals related to the output stage circuit 10 of fig. 1 when the electronic device using the audio chip 1 is turned off, for explaining the reason of pop. The voltage waveforms of the power voltage Vdd, the switching signal Ssw, the amplifier enable signal ENamp, and the output node Nout are shown in the top-down rows of the diagram. The change of each signal is described below in chronological order.

During the time t0 and the time t1, the power voltage Vdd is high (e.g., 3.3V), the switch signal Ssw is low, and the voltage level of the output node Nout is the output signal AUDout (circled point C0) generated by the audio decoder in the normal play mode. During this period, the audio decoder originally transmits the input signal AUDin to the output stage circuit 10, and the output stage circuit 10 generates the output signal AUDout at the output node Nout. The speaker 17 will emit a sound during the period corresponding to the circled position C0. Then, the audio decoder will transmit the mute mode waveform to the output stage circuit 10 instead because of receiving the power-off command, and the output stage circuit 10 will output 0V to the output node Nout after receiving the mute mode waveform (circled point C1). Accordingly, the speaker 17 stops emitting sound during the period corresponding to the circled point C1.

On the other hand, because the output stage circuit 10 receives the mute mode waveform, at the time t1, the control logic circuit 18 switches the switching signal Ssw from low level to high level and switches the switch circuit 13 to the on state. In addition, at time t2, the amplifier enable signal ENamp is decreased from high to low to disable the amplifier module 11. Assume that a power snap-off phenomenon occurs from time t3, and the power voltage Vdd gradually decreases from a high level to a low level from time t 3. The sudden power failure may be caused by the power line of the electronic product being disconnected or the power switch of the electronic product being switched off, so that the power voltage Vdd received by the electronic product is interrupted.

After the power supply voltage Vdd starts to fall at the time t3, the switching signal Ssw also starts to fall under the influence of the fall of the power supply voltage Vdd. However, when the voltage of the switching signal Ssw drops too low, the switching circuit 13 cannot be fully turned on.

In addition, during the time t3 and the time t4, the switch circuit 13 is not completely turned on, and therefore the potential of the output node Nout cannot be connected to the ground voltage Gnd. Therefore, the voltage of the output node Nout is not completely equal to the ground voltage Gnd. It will be appreciated that the residual charge of the amplifier module 11 will likely produce a small glitch (circled at C2) at the output node Nout, due to the fact that the voltage at the output node Nout will not be exactly equal to the ground voltage Gnd. The speaker 17 emits pop-noise (pop-noise) due to this surge of the output node Nout. After the time t4, the audio chip 1 completely stops operating because the power voltage Vdd is maintained at a low level. Thereafter, the power voltage Vdd, the switching signal Ssw, the amplifier enable signal ENamp, and the output node Nout are all low.

As can be seen from the above description, in the method of controlling the voltage of the output node Nout by the output stage circuit 10 of the audio chip 1 according to the mute mode waveform, when the power is off due to no warning, such as when the power is ready to be turned off or the power is suddenly removed, the switch 13 cannot be completely turned on due to the low level of the switching signal Ssw changing with the power voltage Vdd, and the speaker 17 may be popped to affect the hearing of the user when the power is turned off or the power is suddenly turned off.

Therefore, the output stage circuit disclosed by the invention further changes the mode of controlling the switch circuit so as to avoid the generation of the popping sound. According to the disclosed concept, a selection circuit is disposed at the front end of the switch circuit. The selection circuit receives the power detection signal PALT that changes in response to a change in the power voltage Vdd (e.g., 3.3V). The selection circuit determines how to generate the switching signal Ssw for controlling the switch circuit according to the level of the power detection signal PALT.

Please refer to fig. 3, which is a schematic diagram of an output stage according to an embodiment of the disclosure. In the figure, the output stage circuit 30 includes an amplifier module 31, a switch circuit 33, amplifier enable

circuits

361 and 362, and a selection circuit 35.

The amplifier module 31 further includes a first stage amplifier 311 located at the previous stage and receiving the input signal AUDin, and a second stage amplifier 312 located at the subsequent stage and generating the output signal AUDout. In actual application, the number of amplifiers included in the amplifier module 31, the connection mode thereof, and the like are not limited. In addition, in practical applications, the number of the amplifier enable

circuits

361 and 362 varies with the number of the amplifiers included in the output stage 31, and is not limited thereto.

The audio chip utilizes the control logic circuit 38 to output the first control signal AUDsw to the selection circuit 35, and respectively output the second control signal AUDctrl1 and the third control signal AUDctrl2 to the amplifier enable

circuits

361 and 362.

The selection circuit 35 determines whether to use the first control signal AUDsw as the switching signal Ssw based on the level of the power detection signal PALT. The switching signal Ssw is used to control whether the switch circuit 33 is turned on or off.

The amplifier enable

circuits

361 and 362 determine whether to use the second control signal AUDctrl1 and the third control signal AUDctrl2 as the amplifier enable signals ENamp1 and ENamp2 according to the level of the power detection signal PALT. The amplifier enable signals ENamp1 and ENamp2 are respectively used to control the first stage amplifier 311 and the second stage amplifier 312 to be enabled or disabled.

According to the disclosure, the power detection signal PALT changes level according to a comparison result of a predetermined threshold voltage Vth and the power voltage Vdd. When the power voltage Vdd is higher than or equal to the predetermined threshold voltage Vth, the power detection signal PALT is at the first level, and the output stage circuit 30 is in the first mode. When the power voltage Vdd is lower than the predetermined threshold voltage Vth, the power detection signal PALT is at the second level, and the output stage circuit 30 is in the second mode. In one embodiment, the predetermined threshold voltage Vth may be set to be a product of the power voltage Vdd and a value less than 1, for example: assume that the predetermined threshold voltage Vth is 0.8 × Vdd.

Alternatively, the level of the power detection signal PALT may be determined by matching with a fault tolerance or a buffer. For example, to prevent the effect of the burst noise, two predetermined threshold voltages, a first predetermined threshold voltage Vth1 and a second predetermined threshold voltage Vth2, may be set. The first predetermined threshold voltage Vth1 is greater than or equal to the second predetermined threshold voltage (Vth1 ≧ Vth 2). For example, assume that the first predetermined threshold voltage Vth1 is 0.8 × Vdd, and the second predetermined threshold voltage Vth2 is 0.7 × Vdd. This can prevent the level of the power voltage Vdd from being interfered by small noise and affecting the determination result of the power detection signal PALT.

For example, assume that the supply voltage Vdd drops from 3.3V to only 2.5V, which is slightly lower than 0.8 Vdd (2.664V), but still higher than 0.7 Vdd (2.331V). At this time, the power detection signal PALT is still maintained at the first level. If the power voltage Vdd continues to decrease even further below the second predetermined threshold voltage Vth2, the power detection signal PALT is shifted from the first level to the second level. According to the disclosure, the second predetermined threshold voltage Vth2 is equivalent to a power voltage that provides the lowest level required by the audio chip to maintain the basic operation.

Please refer to fig. 4, which is a waveform diagram of related signals of the output stage circuit of fig. 3. From top to bottom, the power voltage Vdd, the switching signal Ssw, the amplifier enable signals ENamp1, ENamp2, and the voltage at the output node Nout are shown in the figure.

First, the power voltage Vdd starts to decrease at time t1, and gradually decreases from time t1 to time t3 until time t3 decreases to 0V. The power detect signal PALT is maintained at the first level (e.g., high level) until time t 1. Starting at time t1, the voltage of the power supply detection signal PALT gradually decreases as the power supply voltage Vdd decreases. When the power voltage Vdd drops to less than or equal to the predetermined threshold voltage Vth (e.g., at time t2), the power detection signal PALT transitions from the first level to the second level (e.g., high level to low level).

Before the time t2, the switching signal Ssw is maintained at a low level because the power detection signal PALT is at a high level. Meanwhile, the amplifier enable signals ENamp1 and ENamp2 output high levels to enable the corresponding first stage amplifier 311 and second stage amplifier 312, respectively, due to the power detection signal PALT being high level. Therefore, before time t2, the output stage 30 generates the output signal AUDout at the output node Nout.

From the time t2, the power detection signal PALT is at a low level, and the selection circuit 35 does not use the first control signal AUDsw as the switching signal Ssw, but instead uses a high level as the switching signal Ssw. How the selection circuit 35 generates the high-level switching signal Ssw will be described in the following embodiments. After the time t2, the switch circuit 33 is turned on by the switching signal Ssw with high level. At the same time, the amplifier enable signals ENamp1 and ENamp2 are low level respectively to disable the corresponding first stage amplifier 311 and second stage amplifier 312 because the power detection signal PALT is low level.

In this figure, the time t2 corresponds to a dividing point. The power detection signal PALT transitions to the second level at time t2, at which time the switching signal Ssw transitions from the low level to the high level, and the amplifier enable signals ENamp1, ENamp2 transition from the high level to the low level. Accordingly, when the switching signal Ssw starts to turn on the switch circuit 33 from time t2, the switch circuit 33 turns on the ground voltage Gnd to the output node Nout, so that the potential of the output node Nout is the ground voltage Gnd. At the same time, the amplifier enable signals ENamp1 and ENamp2 also disable the first stage amplifier 311 and the second stage amplifier 312 at the same time. Accordingly, it is further ensured that the operations of the first stage amplifier 311 and the second stage amplifier 312 are synchronized with the switching circuit 33.

For the output node Nout, during the time t2 at the time t0, the switch circuit 33 is turned off, so that the output node Nout generates the output signal AUDout of 0V according to the mute mode waveform (circled point C3). After the time t2, the switch circuit 33 turns on the ground voltage Gnd, so that the potential of the output node Nout becomes the ground voltage Gnd. Therefore, the output signal AUDout from the time t2 is maintained at 0V.

According to the disclosure, the amplifier enable

circuits

361, 362 and the selection circuit 35 can generate different switching signals Ssw and amplifier enable signals ENamp1, ENamp2 according to different levels of the power detection signal PALT. The operation of the amplifier enable

circuits

361 and 362 and the selection circuit 35 when the power detection signal PALT is at the first level (high level) and the second level (low level) will be described below with reference to fig. 5 and 6.

In fig. 5 and 6, the amplifier enable circuit 361 includes: an enable unit 361a, a disable unit 361 b; the amplifier enable circuit 362 includes: an enable unit 362a, a disable unit 362 b; the selection circuit 35 includes a first mode selection unit 351 and a second mode selection unit 352. The first mode selection unit 351 includes a first transistor T1; the second mode selection unit 352 includes: a storage capacitor Csam, a second transistor T2, and a third transistor T3.

In the amplifier enable

circuits

361, 362, the

enable units

361a, 361b are respectively controlled by the second control signal AUDctrl1 transmitted by the control logic circuit 38,The third control signal AUDtrl 2 is used as the amplifier enable signal ENamp1,

The amplifier enable signals ENamp1, ENamp2 are transmitted to the first stage amplifier 311 and the second stage amplifier 312, so that the first stage amplifier 311 and the second stage amplifier 312 operate according to the amplifier enable signals ENamp1, ENamp 2. It should be noted that the first control signal AUDsw, the second control signal AUDctrl1, and the third control signal AUDctrl2 may be high or low, depending on how the control logic circuit 38 outputs the signals.

Fig. 5 is a schematic diagram illustrating the selection circuit 35 in the output stage circuit according to an embodiment of the invention selecting the first mode unit to generate the switching signal Ssw when the power detection signal is at the first level (high level). For ease of illustration, the elements and signals that are not selected are shown in dashed lines.

In one embodiment, when the power detection signal PALT is at the first level, the first transistor T1 is turned on, and the selection circuit 35 generates the switching signal Ssw by using the first mode selection unit 351. At this time, the first mode selection unit 351 uses the first control signal AUDsw as the switching signal Ssw because the first transistor T1 is turned on. At this time, the switching signal Ssw may be at the first level or the second level according to the variation of the first control signal AUDsw. At the same time, the second transistor T2 of the second mode selection unit 352 is turned on, and the third transistor T3 is turned off. In addition, the second transistor T2 can charge the storage capacitor Csam with the power voltage of the first potential voltage V1 (e.g., high), so as to maintain the voltage of the sampling node Nsam at the first potential voltage V1. The first potential voltage V1 must be sufficient to make the switch 33 fully conductive. Since the third transistor T3 is turned off, the first potential voltage V1 of the sampling node Nsam does not affect the switching signal Ssw.

When the power detection signal PALT is at the first level, the amplifier enable

circuits

361 and 362 generate the amplifier enable signals ENamp1 and ENamp2 through the

enable units

361a and 362 a. The amplifier enable signals ENamp1 and ENamp2 are changed according to the second control signal AUDctrl1 and the third control signal AUDctrl 2. Therefore, the amplifier enable signals ENamp1, ENamp2 may be low (L) or high (H).

Fig. 6 illustrates that the output stage circuit 30 selects the disabling

units

361b, 362b and the second mode selection unit 352 when the power detection signal PALT is at the second level. Fig. 6 is a diagram illustrating the selection circuit 35 of the output stage circuit according to an embodiment of the invention selecting the second mode selection unit 352 to generate the switching signal Ssw when the power detection signal PALT is at the second level (low level). For ease of illustration, the elements and signals that are not selected are shown in dashed lines.

When the power supply detection signal PALT is at the second level, the selection circuit 35 generates the switching signal Ssw by using the second mode selection unit 352. At this time, the first transistor T1 is turned off. Therefore, the level of the switching signal Ssw is not affected by the first transistor T2. On the other hand, the second transistor T2 is turned off, and the third transistor T3 is turned on. Because the second transistor T2 stops conducting, the first potential voltage V1 is not transmitted to the sampling node Nsam. Since the third transistor T3 is turned on, the voltage of the sampling node Nsam is transmitted to the switch circuit 33 through the third transistor T3. Accordingly, the switching signal Ssw is high according to the voltage of the sampling node Nsam (the sampling voltage Vsam), and turns on the switch circuit 33 to the ground voltage Gnd.

When the power detection signal PALT is at the second level, the amplifier enable

circuits

361 and 362 generate amplifier enable signals ENamp1 and ENamp2 through the disabling

units

361b and 362 b. At this time, the disabling units 361b, 62b directly use the low-level (e.g., ground voltage Gnd) disabling signal Vdis as the amplifier enabling signals ENamp1, ENamp2, thereby disabling the first stage amplifier 311 and the second stage amplifier 312.

According to the disclosure, the first transistor T1 and the second transistor T2 are transistors having the same type, and the third transistor T3 has a different type from the first two. In addition, the third transistor T3 is not only different in type from the first transistor T1 and the second transistor T2, but also different in on/off status.

As can be seen from the descriptions of fig. 5 and 6, the level of the power detection signal PALT can reflect the characteristics of the power voltage Vdd in real time, and different mode selection units are selected to generate the switching signal Ssw. When the power detection signal PALT is at a high level, the first mode selection unit 351 is used to generate a switching signal Ssw; when the power supply detection signal PALT is at a low level, the switching signal Ssw is generated by the second mode selection unit 352. When the power detection signal PALT is switched from a high level to a low level, the second mode selection unit 352 uses the pre-stored high-level sampling voltage Vsam as the switching signal Ssw, and enables the potential of the output node Nout to be quickly connected to the ground voltage Gnd through the switch circuit 33. Even if the power supply signal Vdd continues to fall, the switching circuit 33 is continuously turned on by using the sampling voltage Vsam as the switching signal Ssw, so that the output node Nout is continuously connected to the ground voltage Gnd. Thus, even though the amplifier module 31 still has residual charges, the residual charges can still be conducted from the output node Nout to the ground so as to avoid the generation of glitch at the output node Nout. Thereby preventing the loudspeaker from producing crackling sound.

The power detection signal PALT may be a power detection signal PALT built in the system for detecting the state of the power voltage Vdd, or may be an additionally designed power detection signal PALT for detecting the state of the power voltage Vdd. The present embodiment can be applied as long as the change of the power supply voltage Vdd can be detected.

Fig. 7 is a circuit diagram illustrating an example of the output stage circuit 30 of fig. 5 and 6 implemented according to the present disclosure. In fig. 7, the amplifier module 51 includes

amplifiers

511 and 512. The amplifier 511 has a positive power terminal coupled to the power supply voltage Vdd and a negative power terminal coupled to the ground voltage Gnd. The non-inverting input of the amplifier 511 is coupled to a reference voltage Vref (e.g., 1.1V), and the inverting input is coupled between the resistors R1 and R2. The amplifier 512 has a positive power terminal coupled to the power supply voltage Vdd and a negative power terminal coupled to the reverse power supply voltage Vneg. The amplifier 512 has a non-inverting input coupled to the reference voltage Vref, an inverting input coupled between the resistors R3 and R4, and an output common mode voltage (Gnd) as the ground voltage. In one embodiment, multiplexer 56a is used to generate amplifier enable signal ENamp1 to enable/disable amplifier 511; and generates an amplifier enable signal ENamp2 to enable/disable amplifier 512 using multiplexer 56 b. The

multiplexers

56a and 56b receive the disable signal Vdis (e.g., 0V) at their two data inputs, and the second control signal AUDctrl1 and the third control signal AUDctrl2 provided from the control logic circuit 58. The data selection terminals of the

multiplexers

56a and 56b receive the power detection signal PALT from the power detection circuit 59.

When the voltages of the power detection signals PALT connected to the data selection terminals of the

multiplexers

56a and 56b are at the first level, the

multiplexers

56a and 56b transmit the second control signal AUDctrl1 and the third control signal AUDctrl2 to the amplifier 511 as the amplifier enable signals ENamp1 and ENamp 2. Therefore, the

amplifiers

511 and 512 operate according to the levels of the amplifier enable signals ENamp1 and ENamp 2. When the voltage of the power detection signal PALT at the data selection terminal is at the second level, the

multiplexers

56a and 56b will transmit the disable signal Vdis of 0V to the

amplifiers

511 and 512 as the amplifier enable signals ENamp1 and ENamp 2. In conjunction,

amplifiers

511, 512 are disabled.

This embodiment assumes that the first mode selection unit 551 includes a first transistor T1'; the second mode selection unit 552 includes a second transistor T2 'and a third transistor T3'. The first transistor T1 ', the second transistor T2 ' are NOMS transistors, and the third transistor T3 ' is a PMOS transistor. The first transistor T1' has a drain coupled to the control logic circuit 58, a gate controlled by the power detection signal PALT, and a source coupled to the switch circuit 53. The drain of the second transistor T2' is coupled to Vdd, the gate receives the power detection signal PALT, and the source is coupled to the sampling node Nsam. The third transistor T3' has a source coupled to the sampling node Nsam, a gate receiving the power detection signal PALT, and a drain coupled to the switch circuit 53. In addition, the source and the base of the third transistor T3' are electrically connected.

When the power detection signal PALT is at the first level, the first transistor T1' is turned on because the gate is at a high level. The first control signal AUDsw received by the drain is transmitted to the source as the switching signal Ssw. On the other hand, the second transistor T2' is turned on because the gate is at a high level, and conducts the drain power voltage Vdd to the source sampling node Nsam. At this time, the storage capacitor Csam will be charged. Further, the third transistor T3' stops being turned on because the gate is at a high level. Therefore, when the power detection signal PALT is at the first level, the third transistor T3' does not affect the level of the switching signal Ssw.

When the power detection signal PALT is at the second level, the first transistor T1 'and the second transistor T2' both stop conducting because the gates are at a low level. On the other hand, the third transistor T3' is turned on because the gate is at a low level, and transmits the source sampling voltage Vsam to the drain as the switching signal Ssw.

Fig. 8 is a circuit diagram illustrating another example of the output stage circuit 30 of fig. 5 and 6 according to the present disclosure. The second mode selection unit 652 of this embodiment additionally uses the fourth transistor T4 ″ and the fifth transistor T5 ″ as compared with fig. 7. In addition, the second transistor T2 ″ and the third transistor T3 ″ of this embodiment are not directly controlled by the power detection signal PALT, but are controlled by the control node Nctrl. The control node Nctrl is further controlled by the power supply detection signal PALT through the fourth transistor T4 ″ and the fifth transistor T5 ″. That is, the second transistor T2 ″ and the third transistor T3 ″ of this embodiment are indirectly controlled by the power detection signal PALT. In this embodiment, the first mode selection unit 651 includes a first transistor T1 "; the second mode selection unit 652 includes a second transistor T2 ", a third transistor T3", a fourth transistor T4 ", and a fifth transistor T5". The first transistor T1 ", the second transistor T2" and the fifth transistor T5 "are PMOS transistors; the third transistor T3 "and the fourth transistor T4" are NMOS transistors. In order to avoid the leakage of the storage capacitor Csam caused by the conduction of the PMOS transistors (T1 ", T2", T5 "), thereby affecting the voltage of the sampling node Nsam. Thus, this embodiment couples the base (bulk) of the PMOS transistors (T1 ', T2 ', T5 ') to the sampling node Nsam.

In the first mode selection unit 651, the first transistor T1 ″ has a source coupled to the control logic circuit 58, a gate coupled to the control node Nctrl, and a drain coupled to the switch circuit 53, and outputs the switching signal Ssw. Whether the first transistor T1 ″ is turned on or not depends on the voltage of the control node Nctrl. The voltage of the control node Nctrl is determined by whether the fifth transistor T5 ″ is turned on.

In the second mode selection unit 652, the source of the second transistor T2 ″ is coupled to the sampling node Nsam, the gate is coupled to the control node Nctrl, and the drain is coupled to Vdd; the third transistor T3 "has a drain coupled to the sampling node Nsam, a gate coupled to the control node Nctrl, and a source coupled to the switch circuit 53. The second mode selection unit 652 outputs Ssw using the source of the third transistor T3 ″; the fourth transistor T4 ″ has a drain coupled to the ground voltage Gnd, a gate coupled to the power detection signal PALT, and a source coupled to the control node Nctrl; and a fifth transistor T5 ″ having a drain coupled to the control node Nctrl, a gate coupled to the power detection signal PALT, and a source coupled to the sampling node Nsam.

In fig. 8, whether the first transistor T1 ", the second transistor T2", and the third transistor T3 "are turned on or off depends on the voltage of the control node Nctrl. Here, the voltage of the control node Nctrl is further influenced by whether the fourth transistor T4 ″ and the fifth transistor T5 ″ are turned on or not.

When the power detection signal PALT is at the first level (e.g., high level), the gates of the fourth transistor T4 ″ and the fifth transistor T5 ″ are at a high level. The fourth transistor T4' is turned on because the gate is high, and the control node Nctrl is set to the ground voltage Gnd. The fifth transistor T5 ″ is turned on because the gate is high. The first transistor T1 ″ has its gate connected to the control node ntrl, so that the ground voltage Gnd is low. At this time, the first transistor T1 ″ is turned on by the low level of the gate, and transmits the first control signal AUDsw from the source to the drain. On the other hand, the gate of the second transistor T2 ″ is connected to the control node Nctrl, and therefore is the low-level ground voltage Gnd. Accordingly, the second transistor T2 ″ is turned on, and the voltage of the sampling node Nsam is maintained at the high level of the power voltage Vdd. Further, the gate of the third transistor T3 ″ is connected to the control node Nctrl, and therefore, is the low-level ground voltage Gnd. Therefore, the third transistor T3 ″ is not turned on.

When the power detection signal PALT is at the second level (e.g., low level), the fourth transistor T4 ″ stops being turned on because the gate is at the low level; the fifth transistor T5 ″ is turned on because the gate is at a low level. Therefore, the charge previously accumulated in the storage capacitor Csam is conducted from the fifth transistor T5 ″ to the control node Nctrl. Therefore, the voltage of the control node Nctrl is high.

When the power detection signal PALT is at the second level, the voltage at the control node Nctrl is at a high level. At this time, the first transistor T1 ″ and the second transistor T2 ″ are turned off due to the high level of the gates. Because the second transistor T2 ″ stops conducting, the voltage at the sampling node Nsam is not affected by the second transistor T2 ″. Further, the gate of the third transistor T3 ″ is connected to the control node Nctrl and is high. Therefore, the third transistor T3 ″ will be turned on and transmit the voltage of the sampling node Nsam (the sampling voltage Vsam) to the source. Therefore, when the power detection signal PALT is at the first level, the second mode selection unit 652 uses the sampling voltage Vsam at the high level as the switching signal Ssw.

Summarizing the operation of the transistors shown in fig. 8, the power detection signal PALT affects whether the fourth transistor T4 ″ and the fifth transistor T5 ″ are turned on or off, and the fourth transistor T4 ″ and the fifth transistor T5 ″ are turned on alternately. Further, whether the fourth transistor T4 ″ and the fifth transistor T5 ″ are turned on or not changes the voltage of the control node Nctrl. Thereafter, the voltage of the control node Nctrl turns on the second transistor T2 ", the third transistor T3" in turn. Although the on/off states of the second transistor T2 ″ and the third transistor T3 ″ of the embodiment are not changed by the level change of the power detection signal PALT. However, the level of the power detection signal PALT still indirectly controls the second transistor T2 ″ and the third transistor T3 ″ to be turned on or off.

As can be understood from the descriptions of fig. 7 and fig. 8, the implementation of the selection circuit is not particularly limited in the present disclosure. Taking the second mode selection unit 352 as an example, as long as the level of the power detection signal PALT is linked with the second transistor T2 and the third transistor T3 in the second mode selection unit 352, the second mode selection unit 352 can charge the storage capacitor Csm when the power detection signal PALT is at the first level; when the power detection signal PALT is at the second level, the sampling voltage Vsam may be provided as the switching signal Ssw.

Therefore, the present disclosure may also be implemented with different types of selection circuits by other applications and design methods. When a selection circuit is capable of maintaining the control mode using the first control signal AUDsw as the switching signal Ssw when the power detection signal PALT is at the first level, and simultaneously charging the storage capacitor Csam to a high level; and, when the power detection signal PALT is at the second level, the storage capacitor Csam is used to provide the high level switching signal Ssw, so that the selection circuit is in accordance with the concept of the present disclosure.

Incidentally, the present disclosure does not necessarily limit the type of the power detection circuit. Therefore, in addition to generating the power supply detection signal PALT by the on-chip reset (power on reset) circuit, it may be generated by a dedicated circuit in addition.

As can be seen from the foregoing description, the selection circuit can change the switching signal Ssw quickly because the power detection signal PALT can accurately and quickly reflect the change of the power voltage Vdd. That is, a switch is made from the generation of the switching signal Ssw by the first mode selecting unit to the generation of the switching signal Ssw by the second mode selecting unit. Once the second mode selection unit is selected for generating the switching signal Ssw, the switching circuit may be turned on by the sampling voltage Vsam provided by the storage capacitor Csam. The switch circuit turns on the ground voltage Gnd and the output node Nout, so that the potential of the output node Nout is the ground voltage Gnd. Since the storage capacitor Csam has pre-stored charges, the switching signal Ssw can continue to be held at the sampling voltage Vsam at a high level. Therefore, the output node Nout can be continuously connected to the grounding terminal when the audio chip is shut down or the power supply voltage is interrupted, so that residual charges in the audio chip are removed from the grounding terminal, and the popping phenomenon can be effectively avoided.

In summary, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention should be determined by the appended claims.

Claims

1. An output stage circuit comprising:

the amplifier module is provided with an output end and converts an input signal into an output signal;

a switch circuit coupled between the output terminal and a ground terminal; and

a selection circuit, coupled to the switch circuit, for generating a switching signal for controlling the switch circuit according to a level of a power detection signal, wherein the level of the power detection signal changes in response to a change in a power voltage, and the selection circuit comprises:

a first mode selection unit for receiving a first control signal; and

a second mode selection unit having a storage capacitor, wherein,

when the power detection signal is at a first level, the first mode selection unit takes the first control signal as the switching signal, and the second mode selection unit charges the storage capacitor to a high level, an

When the power detection signal is at a second level, the second mode selection unit takes the voltage stored in the storage capacitor as the switching signal to turn on the switch circuit, so that the output end of the amplifier module is grounded, wherein the first level is higher than the second level.

2. The output stage circuit of claim 1, wherein the first mode selection unit comprises:

a first transistor controlled by the power detection signal and receiving the first control signal;

when the power detection signal is at the first level, the first transistor is turned on, and a first control signal is output as the switching signal to selectively turn on the switch circuit;

when the power detection signal is at the second level, the first transistor is not conducted.

3. The output stage circuit according to claim 2, wherein the second mode selection unit comprises a second transistor and a third transistor, the second transistor and the third transistor being turned on or off according to the level of the power detection signal;

when the power detection signal is at the first level, the second transistor is turned on and the third transistor is turned off, and a first potential voltage charges the storage capacitor through the second transistor;

when the power detection signal is at the second level, the second transistor is not turned on and the third transistor is turned on, and the third transistor outputs the voltage of the storage capacitor as the switching signal to turn on the switch circuit.

4. The output stage circuit of claim 3,

the first transistor is an N-type transistor, the second transistor is an N-type transistor, the third transistor is a P-type transistor, wherein the gates of the first transistor, the second transistor and the third transistor receive the power detection signal, the storage capacitor is coupled between the second transistor and the third transistor, and the source and the base of the third transistor are electrically connected.

5. The output stage circuit of claim 3,

the first transistor is a P-type transistor, wherein a gate of the first transistor is coupled to a control node, a first end of the first transistor receives the first control signal, and a second end of the first transistor outputs the first control signal as the switching signal when the power detection signal is at the first level;

the second transistor is a P-type transistor, a gate of the second transistor is coupled to the control node, a first end of the second transistor receives the first potential voltage, and a second end of the second transistor is coupled to a sampling node;

the third transistor is an N-type transistor, a gate of the third transistor is coupled to the control node, a first end of the third transistor is coupled to the sampling node, and a second end of the third transistor outputs the switching signal.

6. The output stage circuit of claim 5, wherein the second mode selection unit further comprises:

a fourth transistor, a first terminal of which is grounded, a second terminal of which is coupled to the control node, the fourth transistor being controlled by the power detection signal and being turned on when the power detection signal is at the first level; and

and a fifth transistor coupled between the control node and the sampling node, the fifth transistor being controlled by the power detection signal and being turned on when the power detection signal is at the two level.

7. The output stage of claim 6, wherein the fourth transistor is an N-type transistor, the fifth transistor is a P-type transistor, and the second and fifth transistors have their bases and sources coupled to each other.

8. The output stage of claim 1, wherein a power voltage is supplied to the output stage, and the power detection signal is at the first level when the power voltage is greater than or equal to a first predetermined threshold voltage;

when the power voltage is lower than a second predetermined threshold voltage, the power detection signal is at the second level.

9. The output stage circuit of claim 8, wherein the first predetermined threshold voltage is greater than or equal to the second predetermined threshold voltage.

10. The output stage circuit of claim 1, wherein the amplifier module comprises a first stage amplifier and a second stage amplifier connected in series, the first stage amplifier and the second stage amplifier are controlled by a second control signal and a third control signal respectively, the second stage amplifier is coupled to the switch circuit, and the common mode voltage of the second stage amplifier is a ground voltage;

when the power detection signal is at the second level, the second control signal and the third control signal are simultaneously transited with the first control signal, thereby disabling the first-stage amplifier and the second-stage amplifier.