CN102768964A - 制造半导体部件的方法 - Google Patents

制造半导体部件的方法 Download PDF

Info

Publication number
CN102768964A
CN102768964A CN2012101356989A CN201210135698A CN102768964A CN 102768964 A CN102768964 A CN 102768964A CN 2012101356989 A CN2012101356989 A CN 2012101356989A CN 201210135698 A CN201210135698 A CN 201210135698A CN 102768964 A CN102768964 A CN 102768964A
Authority
CN
China
Prior art keywords
wafer
mask
metal coating
components
parts
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2012101356989A
Other languages
English (en)
Other versions
CN102768964B (zh
Inventor
M.科克
R.埃塞勒
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Danfoss Silicon Power GmbH
Original Assignee
Danfoss Silicon Power GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Danfoss Silicon Power GmbH filed Critical Danfoss Silicon Power GmbH
Publication of CN102768964A publication Critical patent/CN102768964A/zh
Application granted granted Critical
Publication of CN102768964B publication Critical patent/CN102768964B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C4/00—Coating by spraying the coating material in the molten state, e.g. by flame, plasma or electric discharge
    • C23C4/01—Selective coating, e.g. pattern coating, without pre-treatment of the material to be coated
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C4/00—Coating by spraying the coating material in the molten state, e.g. by flame, plasma or electric discharge
    • C23C4/02—Pretreatment of the material to be coated, e.g. for coating on selected surface areas
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C4/00—Coating by spraying the coating material in the molten state, e.g. by flame, plasma or electric discharge
    • C23C4/12—Coating by spraying the coating material in the molten state, e.g. by flame, plasma or electric discharge characterised by the method of spraying
    • C23C4/134—Plasma spraying
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C4/00—Coating by spraying the coating material in the molten state, e.g. by flame, plasma or electric discharge
    • C23C4/18—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/03001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/03002—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for supporting the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0341—Manufacturing methods by blanket deposition of the material of the bonding area in liquid form
    • H01L2224/03418—Spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0343—Manufacturing methods by blanket deposition of the material of the bonding area in solid form
    • H01L2224/03442—Manufacturing methods by blanket deposition of the material of the bonding area in solid form using a powder
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Plasma & Fusion (AREA)
  • Organic Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Materials Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Coating By Spraying Or Casting (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Dicing (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

本发明涉及一种借助下述步骤制造半导体部件的方法：制造晶片（2），将部件（1）的结构施加在晶片（2）上从而形成晶片组件，将金属涂层（5）施加在晶片（2）上，移除部件（1）的非接触区域的金属涂层（5），将围绕层施加在部件（1）的边缘区域上，将晶片（2）布置在由夹持环保持的薄片（4）上，将由薄片（4）承载的晶片组合物（1）的部件彼此分离开，将遮盖的掩模（3）布置在由薄片（4）承载的分离的部件（1）的未被涂布的区域上，将金属涂层（5）施加在由掩模（3）遮盖的分离的部件（1）上，移除掩模（3），以及从薄片（4）移除部件（1）并且进一步处理分离的部件（1）。

Description

制造半导体部件的方法
技术领域
本发明涉及一种借助权利要求1的前序部分的步骤制造半导体部件的方法。
背景技术
这种方法记载在US6603191B2中，其特征在于，借助电沉积施加金属涂层。但是，当将接触层施加到承载部件的晶片上时，由于金属层的电沉积，实际上不可能防止晶片产生翘曲。
发明内容
因此，本发明基于防止当施加接触层时产生翘曲的任务。
根据本发明，这一任务是借助权利要求1的特征解决的，单独一个子权利要求限定本发明的优选实施例。
本发明的其他特征和优势记载在下述说明书中，其中，本发明参照附图进行说明。
附图说明
单独一个附图示出布置在薄片上的晶片，各个部件已经切开，金属涂层借助热喷涂优选纳米粉末沉积而施加至接触区域。
具体实施方式
因此，采用本身公知的方式，本发明提出通过形成所述部件的结构并且将钝化的围绕层施加到它们的边缘区域上而制造该晶片。随后，将该晶片设置在由夹持环保持的薄片上，由该薄片承载的部件彼此分离开，例如通过切穿晶片组件，同时保持薄片的完整性。
然后，覆盖所述部件的不被涂布的区域的掩模被布置在由薄片承载的各个部件上，金属涂层通过喷涂或者优选地借助纳米粉末等离子沉积而施加在掩模上。然后，移除该掩模，部件从薄片移除并且进行进一步处理。
单独一个附图示出通过多个部件1形成的晶片2，所述部件借助例如切开而形成。掩模3遮盖所分离的部件的由薄片4承载的区域。该图进一步示出通过热喷涂或者优选地借助纳米粉末等离子沉积而施加在掩模3和所述部件的接触区域上的金属涂层5。
采用所提到的方法中的借助热喷涂施加金属涂层的特征，防止晶片翘曲。

Claims (2)

1.一种借助下述步骤制造半导体部件的方法：
-制造晶片（2），
-将部件（1）的结构施加在晶片（2）上从而形成晶片组件，
-将金属涂层（5）施加在晶片（2）上，
-移除部件（1）的非接触区域的金属涂层（5），
-将围绕层施加在部件（1）的边缘区域上，
-将晶片（2）布置在由夹持环保持的薄片（4）上，
-将由薄片（4）承载的晶片组合物（1）的部件彼此分离开，
-将遮盖的掩模（3）布置在由薄片（4）承载的分离的部件（1）的未被涂布的区域上，
-将金属涂层（5）施加在由掩模（3）遮盖的分离的部件（1）上，
-移除掩模（3），以及
-从薄片（4）移除部件（1）并且进一步处理分离的部件（1），
其特征在于，借助热喷涂将金属涂层（5）施加在由掩模（3）遮盖的分离部件（1）上。
2.根据权利要求1所述的制造半导体部件的方法，热喷涂借助纳米粉末等离子沉积而进行。
CN201210135698.9A 2011-05-03 2012-05-03 制造半导体部件的方法 Expired - Fee Related CN102768964B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102011100255A DE102011100255B3 (de) 2011-05-03 2011-05-03 Verfahren zum Herstellen eines Halbleiterbauelements
DE102011100255.7 2011-05-03

Publications (2)

Publication Number Publication Date
CN102768964A true CN102768964A (zh) 2012-11-07
CN102768964B CN102768964B (zh) 2016-01-20

Family

ID=45923498

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210135698.9A Expired - Fee Related CN102768964B (zh) 2011-05-03 2012-05-03 制造半导体部件的方法

Country Status (4)

Country Link
US (1) US8802564B2 (zh)
EP (1) EP2521166A1 (zh)
CN (1) CN102768964B (zh)
DE (1) DE102011100255B3 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4224521A1 (de) * 2022-02-07 2023-08-09 Siemens Aktiengesellschaft Halbleiteranordnung mit einem halbleiterelement mit einem durch thermisches spritzen hergestellten kontaktierungselement sowie ein verfahren zur herstellung desselben

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5597110A (en) * 1995-08-25 1997-01-28 Motorola, Inc. Method for forming a solder bump by solder-jetting or the like
US20010012643A1 (en) * 1998-01-18 2001-08-09 Kabushiki Kaisha Toshiba Package having very thin semiconductor chip, multichip module assembled by the package, and method for manufacturing the same
US6603191B2 (en) * 2000-05-18 2003-08-05 Casio Computer Co., Ltd. Semiconductor device and method of manufacturing the same
US20060275949A1 (en) * 2002-03-06 2006-12-07 Farnworth Warren M Semiconductor components and methods of fabrication with circuit side contacts, conductive vias and backside conductors
CN101135033A (zh) * 2006-04-20 2008-03-05 信越化学工业株式会社 导电、耐等离子体的构件
CN101847589A (zh) * 2009-03-28 2010-09-29 丹佛斯硅动力股份有限公司 制造适合高压应用的刚性功率模块的方法
US20100272982A1 (en) * 2008-11-04 2010-10-28 Graeme Dickinson Thermal spray coatings for semiconductor applications

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5851911A (en) * 1996-03-07 1998-12-22 Micron Technology, Inc. Mask repattern process
JP3455948B2 (ja) * 2000-05-19 2003-10-14 カシオ計算機株式会社 半導体装置およびその製造方法
JP3664432B2 (ja) * 2000-05-18 2005-06-29 カシオ計算機株式会社 半導体装置およびその製造方法
DE10109087A1 (de) * 2001-02-24 2002-10-24 Leoni Bordnetz Sys Gmbh & Co Verfahren zum Herstellen eines Formbauteils mit einer integrierten Leiterbahn
JP3574450B1 (ja) * 2003-05-16 2004-10-06 沖電気工業株式会社 半導体装置、及び半導体装置の製造方法
KR100738730B1 (ko) * 2005-03-16 2007-07-12 야마하 가부시키가이샤 반도체 장치의 제조방법 및 반도체 장치
DE102006061435A1 (de) * 2006-12-23 2008-06-26 Leoni Ag Verfahren und Vorrichtung zum Aufspritzen insbesondere einer Leiterbahn, elektrisches Bauteil mit einer Leiterbahn sowie Dosiervorrichtung
US7989266B2 (en) * 2009-06-18 2011-08-02 Aptina Imaging Corporation Methods for separating individual semiconductor devices from a carrier
US8883565B2 (en) * 2011-10-04 2014-11-11 Infineon Technologies Ag Separation of semiconductor devices from a wafer carrier

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5597110A (en) * 1995-08-25 1997-01-28 Motorola, Inc. Method for forming a solder bump by solder-jetting or the like
US20010012643A1 (en) * 1998-01-18 2001-08-09 Kabushiki Kaisha Toshiba Package having very thin semiconductor chip, multichip module assembled by the package, and method for manufacturing the same
US6603191B2 (en) * 2000-05-18 2003-08-05 Casio Computer Co., Ltd. Semiconductor device and method of manufacturing the same
US20060275949A1 (en) * 2002-03-06 2006-12-07 Farnworth Warren M Semiconductor components and methods of fabrication with circuit side contacts, conductive vias and backside conductors
CN101135033A (zh) * 2006-04-20 2008-03-05 信越化学工业株式会社 导电、耐等离子体的构件
US20100272982A1 (en) * 2008-11-04 2010-10-28 Graeme Dickinson Thermal spray coatings for semiconductor applications
CN101847589A (zh) * 2009-03-28 2010-09-29 丹佛斯硅动力股份有限公司 制造适合高压应用的刚性功率模块的方法

Also Published As

Publication number Publication date
CN102768964B (zh) 2016-01-20
US8802564B2 (en) 2014-08-12
US20120282772A1 (en) 2012-11-08
DE102011100255B3 (de) 2012-04-26
EP2521166A1 (de) 2012-11-07

Similar Documents

Publication Publication Date Title
WO2013040423A3 (en) Abrasive article and method of forming
EP2701188A3 (en) A method of singulating semiconductor die from a semiconductor wafer
WO2007036164A8 (en) Semiconductor light-emitting device and method for making same
WO2012140050A3 (de) Verfahren zur herstellung eines licht emittierenden halbleiterbauelements und licht emittierendes halbleiterbauelement
WO2017036841A8 (de) Optoelektronisches halbleiterbauelement und verfahren zu dessen herstellung
WO2010036051A3 (en) Structure and manufacture method for multi-row lead frame and semiconductor package
US10535588B2 (en) Die with metallized sidewall and method of manufacturing
EP2517817A3 (en) Electrode wire for electro-discharge machining and method for manufacturing the same
EP2530709B1 (en) Method of producing a semiconductor wafer
KR20140006973A (ko) 하나 이상의 광전자 반도체 칩의 제조 방법
US8841201B2 (en) Systems and methods for post-bonding wafer edge seal
US20180033694A1 (en) Semiconductor device manufacturing method
EP2993692A3 (en) Semiconductor device comprising a bonding structure including a silver-tin compound and a nickel-tin compound and method of manufacturing the same
TW201129497A (en) silicon substrate having nanostructures and method for producing the same and application thereof
WO2012064636A4 (en) Contact pad and method of manufacturing the same
WO2014056762A3 (de) Verfahren zur herstellung eines optoelektronischen halbleiterbauteils und optoelektronisches halbleiterbauteil
US7811904B2 (en) Method of fabricating a semiconductor device employing electroless plating
CN102768964A (zh) 制造半导体部件的方法
CN104600031A (zh) 用于加工晶片的方法
WO2012091329A3 (ko) 발광소자의 제조방법과 이 방법에 의해 제조된 발광소자
CN107017216B (zh) 半导体装置和制造半导体装置的方法
US9984888B2 (en) Method of fabricating a semiconductor wafer including a through substrate via (TSV) and a stepped support ring on a back side of the wafer
RU2016135416A (ru) Компонент с истираемым покрытием и способ нанесения истираемого покрытия
WO2013177299A3 (en) Three dimensional microelectronic components and fabrication methods for same
US20150035140A1 (en) Wafer support system for 3d packaging

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20160120

CF01 Termination of patent right due to non-payment of annual fee