CN102760403B - A kind of signal interface circuit of LED module and LED display - Google Patents
A kind of signal interface circuit of LED module and LED display Download PDFInfo
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Abstract
The invention discloses a kind of signal interface circuit of LED module, aim to provide the signal interface circuit of the LED module that a kind of wiring is few, cost is low, it comprises input socket, accessory power outlet, crystal oscillator, LVDS interface chip, LED dot matrix and the horizontal drive circuit be connected with described LED dot matrix and column drive circuit, and described LVDS interface chip has: the data difference input end be connected with described input socket; The data difference output terminal be connected with described accessory power outlet; RGB output terminal, LED scan control signal output terminal; For exporting the line scanning control signal output terminal of line scanning control signal; Des/CDR module; Phase-locked clock generation module; RGB data intercepts and control signal generation module; Serializer.The invention also discloses and a kind of there is the LED display of the signal interface circuit of above-mentioned LED module and a kind of LVDS interface chip for LED module.The present invention is used for various LED display.
Description
Technical field
The present invention relates to LED and show field, especially relate to a kind of signal interface circuit of LED module and there is the LED display of this signal interface circuit.
Background technology
In the application of LED display, it is a very important ring that circuit between LED module connects, from the nineties, connection at present between general LED module adopts 16-20 line Technique of Parallel always, its signal comprises shift clock SCLK, latch signal/LATCH, open signal/OE, data R [n:0], G [n:0], B [n:0], optional virtual data X [n:0], line scan signals H [m:0] and ground wire, wherein the group number n of RGB data can be 0-3, i.e. 1-4 group, the number m of line scan signals can be 0-3 or nothing according to the difference of dutycycle, namely be 1/2 in dutycycle, 1/4, 1/8, 0 is respectively during 1/16 dynamic scan, 1, 2, 3, line scan signals is not had when dutycycle is 1 static scanning, ground wire then takies all the other non-signal pins, be at least 1.
Make a concrete analysis of the interface circuit design technology of existing LED module below.
Fig. 4 is a kind of group number of RGB data is 2, dutycycle supports 20 line interface layouts of the dynamic scan LED module of 1/16, comprise 6 position datawire R [1..0], G [1..0], B [1..0], 1 bit shift clock, 1 row latch signal/LATCH, 1 open signal/OE, 4 line scan signals H [3..0], effective data and control signal wire number are 13, and ground wire and vacant number of pins are 7.
Fig. 5 is a dutycycle is 1/8; resolution is the legacy interface design circuit schematic diagram of the dynamic LED module of 32 × 16; in figure, interface circuit comprises 3 cmos buffer driving chip 74HC245; 1 CMOS 74HC138 line decoder, 1 CMOS 74HC123 no signal turn-off protection chip and two 20 P sockets.Wherein: 1 74HC245 is used for the driving that RGB inputs data, points of 2 groups R [], G [], B [] totally 6 output to LED array driving circuit respectively, the data as upper and lower two groups of RGB constant current chip arrays input; 1 74HC245 is used for the driving of control signal, divide 2 groups of SCLK ,/LATCH ,/OE signal totally 6, one group of CT [] output to RGB constant current chip go to control RGB data displacement, latch, open and show with gray scale, the row that/OE also outputs to when CMOS74HC138 goes control lines to switch simultaneously turns off blanking, and another group CT_out outputs to next LED module; 1 74HC245 is used for the driving of line scan signals, divides 2 groups of line scan signals totally 6, and one group exports H [] and carries out row decoding to this module CM OS74HC138, and one group of H_out outputs to next LED module; In input control signal /LATCH also simultaneously access CMOS74HC123 go realize without LED turn-off protection during line scan signals.Chip 74HC245,74HC138 and 74HC123 of this parallel RGB data and control signal interface circuit and employing are for many years popular, are extensively adopted by each company.Secondly, also have minority to adopt the manufacturer of Special Interface Chip, but process remain parallel data, this point does not change.
Due in the signal interface circuit design of existing LED module, each road RGB data and control signal generally all adopt parallel transfer pattern, it needs multi-disc CMOS 74HC245 to make bus driver, also needs row decoding device 74HC138 to make row decoding during dynamic scan.Be such as 1/4 in dutycycle, resolution is in the RGB full-color LED module design of 32 row × 16 row, RGB data has 12, control signal has 5, when transfer rate is 20MHz, need 3 74HC245, a slice 74HC138, and adopt 20P socket and 20 core flat cables, come the buffered-display driver of RGB data and LED sweep signal, decoding and transmission.Although the advantage that this kind of prior art has Uniting that is general and that be beneficial to various LED module, is convenient to buying and produces, but, but there is following defect: 1, this parallel transfer pattern transmit data and control signal reach 17, connecting line is many, casing wiring seem numerous and diverse; 2, the I/O resource of more FPGA is occupied; 3, the few space-time pin of signal is many, seems economical not; 4, the interface chip adopted is more, be unfavorable for the design of low-density LED display, and cost is higher; 5, owing to there is no industry standard, force LED manufacturer to develop various different HUB interface board to adapt to the interface layout of each company different LED module, add cost.
Summary of the invention
There is connecting line is many, wiring is complicated, occupy more FPGA I/O resource and the higher technical matters of cost in order to the signal interface circuit solving prior art LED module in the present invention, provides a kind of signal interface circuit and LED display of LED module.
For solving the problems of the technologies described above, the technical solution used in the present invention is design a kind of signal interface circuit of LED module, comprise LED dot matrix, the horizontal drive circuit be connected with described LED dot matrix and column drive circuit, the signal interface circuit of described LED module also comprises input socket, accessory power outlet, LVDS interface chip and the crystal oscillator for generation of local reference clock, and described LVDS interface chip has:
For receiving the data difference input end of rgb video data, it is connected with described input socket;
For exporting the data difference output terminal of rgb video data, it is connected with described accessory power outlet;
For receiving the local clock input end of local reference clock, it is connected with the output terminal of described crystal oscillator;
Be connected with described column drive circuit and export the RGB output terminal of RGB data to described column drive circuit;
Be connected with described column drive circuit and export the LED scan control signal output terminal of LED scan control signal to described column drive circuit;
Be connected with described horizontal drive circuit and export the line scanning control signal output terminal that line scanning controls signal to described horizontal drive circuit;
The Des/CDR module be connected with data difference input end, it receives the rgb video data of described data difference input end input and therefrom recovers shift clock and align with data bit, then converts the rgb video data that data difference input end inputs to parallel data and exports;
One generates the phase-locked clock generation module of phase-locked clock signal according to local clock;
One input end and described Des/CDR module, the output terminal of phase-locked clock generation module connects, output terminal and described RGB output terminal, the RGB data that LED scan control signal output terminal is connected with line scanning control signal output terminal intercepts and control signal generation module, it receives the parallel data that described Des/CDR module exports, and under the shift clock of described recovery and the effect of described phase-locked clock, complete the decoding of parallel data, buffering, the intercepting of the rgb video data of conversion and corresponding LED module, and export the rgb video data of intercepting respectively, LED scan control signal and line scanning control signal to described RGB output terminal, LED scan control signal output terminal and line scanning control signal output terminal, export rgb video data simultaneously,
One to intercept with described RGB data and serializer that the output terminal of control signal generation module and data difference output terminal connect, described serializer receives described RGB data and intercepts and the rgb video data of control signal generation module output, and converts the rgb video data received to serial data and export data difference output terminal to.
Described LVDS interface chip also comprises:
The intelligence sample module of the described LED module data of one monitoring;
The data back input end of one next LED module data of reception;
The data back output terminal of one output return data;
The one passback Des/CDR module be connected with described data back input end, it receives next LED module data of described data back input end input, and converts parallel data output to;
One is connected with the output terminal of described intelligence sample module, the output terminal that returns Des/CDR module and mixes the hybrid circuit of described LED module data and next LED module data;
The one passback serializer be connected with the output terminal of hybrid circuit, mixed described LED module data become serial data to export data back output terminal to next LED module data transformations by it.
Described LVDS interface chip also comprises one and intercepts with described RGB data the FLASH memory be connected with control signal generation module.
Described crystal oscillator produces local reference clock.
Described input socket is 2P socket.
Described accessory power outlet is 2P socket.
The differential input and output mouth of described LVDS interface chip supports warm connection function.
Described Des/CDR module comprises CDR clock data restorer and Des deserializer.
Containing LED module control signal and module parameter in described rgb video data stream.
Present invention also offers a kind of LED display with the signal interface circuit of above-mentioned LED module.
Present invention also offers a kind of LVDS interface chip for LED module, comprising:
For receiving the data difference input end of rgb video data;
For exporting the data difference output terminal of rgb video data;
For receiving the local clock input end of local reference clock;
For exporting the RGB output terminal of RGB data;
For exporting the LED scan control signal output terminal of LED scan control signal;
For exporting the line scanning control signal output terminal of line scanning control signal;
The Des/CDR module be connected with data difference input end, it receives the rgb video data of described data difference input end input and therefrom recovers shift clock and align with data bit, then converts the rgb video data that data difference input end inputs to parallel data and exports;
One generates the phase-locked clock generation module of phase-locked clock signal according to local reference clock;
One input end and described Des/CDR module, the output terminal of phase-locked clock generation module connects, output terminal and described RGB output terminal, the RGB data that LED scan control signal output terminal is connected with line scanning control signal output terminal intercepts and control signal generation module, it receives the parallel data that described Des/CDR module exports, and under the shift clock of described recovery and the effect of described phase-locked clock, complete the decoding of parallel data, buffering, the intercepting of the rgb video data of conversion and corresponding LED module, and export the rgb video data of intercepting respectively, LED scan control signal and line scanning control signal to described RGB output terminal, LED scan control signal output terminal and line scanning control signal output terminal, export rgb video data simultaneously,
One to intercept with described RGB data and serializer that the output terminal of control signal generation module and data difference output terminal connect, described serializer receives described RGB data and intercepts and the rgb video data of control signal generation module output, and converts the rgb video data received to serial data and export data difference output terminal to.
Described LVDS interface chip also comprises:
The intelligence sample module of one monitoring LED module data;
The data back input end of one next LED module data of reception;
The data back output terminal of one output return data;
The one passback Des/CDR module be connected with described data back input end, it receives next LED module data of described data back input end input, and converts parallel data output to;
One is connected with the output terminal of described intelligence sample module, the output terminal that returns Des/CDR module and mixes the hybrid circuit of described LED module data and next LED module data;
The one passback serializer be connected with the output terminal of hybrid circuit, mixed described LED module data become serial data to export data back output terminal to next LED module data transformations by it
The present invention is by arranging LVDS interface chip, only need 2 signal wires can realize the buffered-display driver of LED module total data and control signal, decoding and transmitting function, connecting line obviously reduces, casing wiring is very simple, and drastically reduce the area the I/O mouth resource taking FPGA, simultaneously, the interface chip adopted is few, be conducive to the design of LED display, and be conducive to the standardization of LED module connection, cost is also lower.
Accompanying drawing explanation
Below in conjunction with embodiment and accompanying drawing, the present invention is described in detail, wherein:
Fig. 1 is LED module logic glue schematic diagram of the present invention;
Fig. 2 is the LED module logic glue schematic diagram of band of the present invention monitoring retransmission function
Fig. 3 is the LVDS interface chip Logic Circuit Design schematic diagram of band of the present invention monitoring retransmission function;
Fig. 4 is existing LED module 20 line interface schematic diagram;
Fig. 5 is existing LED module logic glue schematic diagram.
Embodiment
Make a general survey of modern data communication technology, we are not difficult to find, along with the continuous growth to information flow-rate demand, Traditional parallel interfacing has become the bottleneck improving message transmission rate further.Being mainly used in the serial communication technology of optical fiber communication in the past---SerDes is replacing Traditional parallel bus and is becoming the main flow of high-speed interface technology.
SERDES is the abbreviation of parallel series and staticizer SERializer/DESerializer (serializer/also changes device).There is the SerDes interface of two kinds of fundamental types: synchronous (SS) agreement in source and clock and data recovery (CDR) agreement.The essential difference of this two type how to realize clock control.Source sync cap has one with the clock signal transmitting data; CDR does not have independent clock signal, but clock is embedded in the data.Namely CDR receiver by PGC demodulation at data-signal itself to obtain clock.
Low-voltage differential tranmission techniques is based on Low Voltage Differential Signal LVDS(Low Voltage Differential Signal) tranmission techniques, LVDS interface is also known as RS644 bus interface.LVDS is a kind of little amplitude difference signal technique, and it uses low-down range signal, by pair of parallel PCB cabling or balanced cable transmission data.This transmission standard adopts constant current two line differential driving pattern, and anti-common mold noise interference ability is strong, and electromagnetic radiation is little, can not produce the spiking that ring and signal switching bring, have good EMI characteristic.Also there is the advantages such as data reversal is fast, low in energy consumption.Adopt this technology, as long as ensure that the length of ribbon feeder is enough consistent, and provide good impedance matching to reduce signal reflex at receiving end, the transfer rate of data just can be brought up to more than 800MHz by a pair line, transmission range is then successively decreased with the increase of frequency, can reach tens meters to tens centimetres.Because LVDS has these good characteristics, be widely used in USB interface, PCI Ex, all have employed the data mode of differential type.
SerDes and low-voltage differential tranmission techniques have remarkable performance, and SerDes IP creates more favourable condition with the appearance of the programmable logic device (PLD) with difference transceiver interface with the application of applying as difference tranmission techniques.At present, the companies such as Altera, Xilinx, Actel are all proposed inside and are embedded with the number such as not, and speed is the FPGA device of the SerDes IP kernel of 1.5-3.125G, and this signal standards of LVDS is all supported in the input and output of these FPGA device I/O ports.The employing of high speed serial differential tranmission techniques and the release of support high speed serial differential tranmission techniques device, provide very big convenience for realizing apparatus interconnection at a high speed and setting up large-scale electronic system undoubtedly, thus promoted the technological innovation in the fields such as information processing, video display, network communication and data storing and crossed over progressive.
It is not unique, but has its counterpart, investigate the development history of LED display controller control technology, from digital discrete device to GAL, PAL, arrive small-scale FPGA again until large-scale F PGA, no matter the collection of digital video, conversion, transmission, storage, distribution, or the scan control of LED module, just based on being that core builds with FPGA, and with making the development of FPGA.The data transmission of LED display control system transmitter, although because cost factor not yet adopts inside to be embedded with the high-grade fpga chip of 1.5-3.125G SerDes IP kernel, also have employed SerDes and low-voltage differential tranmission techniques in outside, namely by the I/O mouth of FPGA, by video data and control signal parallel output to SerDes chip.Can predict, the expanding day applied along with HD video and high-resolution video, with the reduction of the cost decline and price of making fpga chip, the fpga chip that inside is embedded with SerDes IP kernel will occupy a tiny space in the control system of LED display.
But, between nearly 20 years, data stream transmitting mechanics of communication between LED module, still stop and being confined to the application of separation of C MOS device and not being developed, connection between module still adopts 20 line flat cables to connect, how wordy the layout connecting line of module is, chip more, volume is bigger than normal, high expensive, seems particularly outstanding when being especially applied to low-density screen, the mixed and disorderly distribution of 20 simultaneously different because of company line signals, also be unfavorable for foundation and the unification of signal standards, be unfavorable for the high-level development and progress of LED display.Based on this, the present invention proposes a kind of the LED module communication chip and the circuit design that adopt SerDes communication and low-voltage differential tranmission techniques, the special chip being provided with LVDS differential serial interface by inside is for the access of LED module data and control signal, its application transport speed, up to the LVDS differential communication signal of hundreds of Mbps to several Gbps, only needs 1 pair of twisted-pair feeder can realize the transmission of total data and control signal between LED module.Utilize inner programmable logic resource simultaneously, complete the intercepting of RGB data, the generation of LED control signal and output.
Refer to Fig. 1, Fig. 2 and Fig. 3, the signal interface circuit of LED module of the present invention comprises: LVDS interface chip, crystal oscillator, input 2P socket and export 2P socket, LED dot matrix, the horizontal drive circuit be connected with described LED dot matrix, the column drive circuit that is connected with described LED dot matrix.Crystal oscillator is for generation of local reference clock.
LVDS interface chip comprises: data difference input end, data difference output terminal, RGB output terminal, LED scan control signal output terminal, line scanning control signal output terminal, Des/CDR module, phase-locked clock generation module, RGB data intercept and control signal generation module, serializer (Ser) and FLASH memory.Wherein:
Data difference input end, for receiving the rgb video data of upper level LED module or scanning monitor, wherein, contains LED module control signal and module parameter in rgb video data.
Data difference output terminal is for exporting the LVDS interface chip of rgb video data to next LED module.
RGB output terminal is connected with described LED array driving circuit, for exporting RGB data to the work of LED array driving circuit driving LED lamp.
Local clock input end is connected with described crystal oscillator, for receiving local reference clock;
LED scan control signal output terminal is connected with described LED array driving circuit, for exporting LED scan control signal to LED array driving circuit.
Line scanning control signal output terminal is connected with the input end of described horizontal drive circuit, controls signal to horizontal drive circuit control lines driving circuit for exporting line scanning.
Des/CDR module is connected with data difference input end, it receives the rgb video data of described data difference input end input and therefrom recovers shift clock and align with data bit, then converts the rgb video data that data difference input end inputs to parallel data and exports.Described Des/CDR module comprises CDR clock data restorer and Des deserializer.
Phase-locked clock generation module generates phase-locked clock signal according to local clock.
RGB data intercepts and control signal generation module, its input end is connected with the output terminal of described Des/CDR module, phase-locked clock generation module, and output terminal is connected with serializer with described RGB output terminal, LED scan control signal output terminal, line scanning control signal output terminal.RGB data intercepting and control signal generation module receive the parallel data that described Des/CDR module exports, and under the shift clock of described recovery and the effect of described phase-locked clock, complete the intercepting of rgb video data of the decoding of parallel data, buffering, conversion and corresponding LED module, and export the rgb video data of intercepting, LED scan control signal and line scanning respectively and control signal to described RGB output terminal, LED scan control signal output terminal and line scanning control signal output terminal, export rgb video data to serializer simultaneously.
Serializer (Ser) intercepts with described RGB data and the output terminal of control signal generation module and data difference output terminal connect.Serializer receives described RGB data and intercepts and the rgb video data of control signal generation module output, and converts the rgb video data received to serial data and export data difference output terminal to.
Whole differential input and output mouths of described LVDS interface chip support warm connection function.
FLASH memory intercepts with described RGB data and is connected with control signal generation module, for storing the parameter of LED module.
Input 2P(bis-pin) socket is connected with data difference input end, in order to receive input data S0_in ±.
Exporting 2P(bis-pin) socket is connected with described data difference output terminal, for exporting S0_out ± to the LVDS interface chip of next LED module.
In order to monitor the information such as short circuit and open circuit, the correction coefficient of LED, the temperature of LED module and voltage of LED, the LVDS differential data input S1_in ± of the signal wire increase dotted portion in interface section and output S1_out ±, for realization monitoring retransmission function, LVDS interface chip increases state detecting, process and retransmission function simultaneously.Namely LVDS interface chip also comprises:
Intelligence sample module, it monitors described LED module data;
Data back input end, its receive next LED module data S1_in ±;
Data back output terminal, its output return data S1_out ±;
Passback Des/CDR module, it is connected with described data back input end, receives the return data of next LED module, and converts parallel data output to;
Hybrid circuit, its output terminal with described intelligence sample module, the output terminal returning Des/CDR module are connected and mix described LED module data and next LED module data;
Passback serializer (Ser), it is connected with the output terminal of hybrid circuit, becomes serial data to export data back output terminal to mixed described LED module data with next LED module data transformations.
After increasing data back output terminal and data back input end, owing to adding input and output socket, so in fig. 2 input 2P socket and output 2P socket are changed into input 4P socket respectively and export 4P socket.
The principle of work of the signal interface circuit of LED module of the present invention is: differential data input S0_in ± receive is from the video of scan control plate or a upper LED module and System Control Data, phase-locked recovery shift clock under the effect of CDR receiver, and align with data bit, again by Des(Deserializes, and change device) 8B/10B decoding, output to RGB data after serioparallel exchange and intercept and scan control signal generator, RGB data intercepts and scan control signal generation module completes the decoding of raw data under the effect of receive clock and local phase-locked clock, buffering, the intercepting of conversion and this LED module RGB [] video data, LED scan control signal CT [] is generated again by the scan control signal circuit for generating that RGB data intercepts and scan control signal generation module is built-in, comprise shift clock SCLK, data latch signal/LATCH, the line scan signals Ho [7..0] of gray scale gate-control signal/EN and decoding, and by parallel port driver output to realize the video display of RGB data, raw data passes through Ser(Serializes simultaneously, serializer) 8B/10B encodes and stringization processes, S0_out ± be connected to next stage LED module is exported through differential data after embedding PLL phase-locked loop clock again.
The parallel output mouth of LVDS signaling interface chip can design like this, display data export R [3..0], G [3..0], B [3..0] totally four groups of RGB data, its output function is by software programming, except supporting the various LED modules of 1-4 group data structure, R [3..0], G [1..0], B [1..0] data structure is adopted to support virtual pixel display; Employing R [0], G [0], B [0] singly organize data structure, and 8 of remaining R [3..1], G [3..1], B [3..1] can be used as the high-order horizontal scanning line of 1/16 dynamic scan; Adopt R [1..0], G [1..0], B [1..0] 2 groups of data structures, remaining R [3..2], G [3..2], B [3..2] can be used as multi-branched LED scan control signal SCLK, data latch signal/LATCH and gray scale gate-control signal/EN and export, and design to facilitate LED module.Fixing line scan signals is then Ho [7..0] totally 8, supports 1/2,1/4,1/8 dynamic scanning displaying and static state display, simultaneously by the dynamic scanning displaying of any dutycycle of programming realization 1/3,1/5,1/6 and 1/7.
The acquisition that intelligence sample module can complete LED module monitor data S [] at the corresponding levels is embedded in interface chip, the Monitoring Data of differential data input S1_in ± receive from next LED module, mixed by the monitor signal of mixing module with module at the corresponding levels after Des unstrings, arrive the Ser stringization coding of input end again, the differential data through input end exports and passes toward upper level LED module or scan control plate.
The FLASH module embedded in interface chip for storing LED module parameter at the corresponding levels, RGB correction data and other useful information, for pixel correction and the Based Intelligent Control of brightness, colourity.
When not adopting passback monitoring function, removing Fig. 5 dotted portion, being lower-cost list to differential lines transfer scheme.
As for the encapsulation of LVDS signaling interface chip, miniature TQFP encapsulation, QFN encapsulation can being adopted, as adopted BGA package, then in the LED module design of four laminates, having more advantage.
The signal interface circuit of LED module of the present invention can be used for various LED display, as monochromatic LED display screen, double-basis LED display, full-color LED display screen etc.
Tool of the present invention has the following advantages:
1, adopt 1 high speed LVDS serial link, only need 2 signal wires, the buffered-display driver of LED module total data and control signal, decoding and transmitting function can be realized.
2, utilize the internal resource of chip to complete the intercepting of the data of LED module and control signal, driving and decoding, support virtual pixel display, the scanning of 1--16 Mobile state or static drive simultaneously.
3, excellent performance, traffic rate can up to 270Mbps to 3.125Gbps, transmitted data amount is large, anti-interference good, reliability is high, LVDS data rate can up to 270Mbps to 3.125Gbps, simultaneously separation of C MOS chip replace by integrated interface chip, its circuit simplifies greatly compared to existing technology.
4, it drastically reduce the area the quantity of signal connecting line between LED module, and make LED box wires design more succinct, cost reduces.
5, the function of output pin can be programmed by user's self-defining, and this brings dirigibility to the design of pcb board.
6, expand 1 LVDS serial return link, there is signal monitoring function, improve the application level of LED display.
7, the I/O mouth significantly reducing scan control plate FPGA exports, and allows to adopt the FPGA of more small package or simpler device, reduce further cost.
8, the standardization effort of LED module connection and communications protocol is conducive to.
The foregoing is only preferred embodiment of the present invention; not in order to limit the present invention; all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement; such as by single into two pairs of differential video inputs etc. are changed to differential video input, all should be included within protection scope of the present invention.
Claims (10)
1. the signal interface circuit of a LED module, comprise LED dot matrix, the horizontal drive circuit be connected with described LED dot matrix and column drive circuit, it is characterized in that: the signal interface circuit of described LED module also comprises input socket, accessory power outlet, LVDS interface chip and the crystal oscillator for generation of local reference clock, and described LVDS interface chip has:
For receiving the data difference input end of rgb video data, it is connected with described input socket;
For exporting the data difference output terminal of rgb video data, it is connected with described accessory power outlet;
For receiving the local clock input end of local reference clock, it is connected with the output terminal of described crystal oscillator;
Be connected with described column drive circuit and export the RGB output terminal of RGB data to described column drive circuit;
Be connected with described column drive circuit and export the LED scan control signal output terminal of LED scan control signal to described column drive circuit;
Be connected with described horizontal drive circuit and export the line scanning control signal output terminal that line scanning controls signal to described horizontal drive circuit;
The Des/CDR module be connected with data difference input end, it receives the rgb video data of described data difference input end input and therefrom recovers shift clock and align with data bit, then converts the rgb video data that data difference input end inputs to parallel data and exports;
One generates the phase-locked clock generation module of phase-locked clock signal according to local reference clock, and it is connected with described local clock input end;
One input end and described Des/CDR module, the output terminal of phase-locked clock generation module connects, output terminal and described RGB output terminal, the RGB data that LED scan control signal output terminal is connected with line scanning control signal output terminal intercepts and control signal generation module, it receives the parallel data that described Des/CDR module exports, and under the shift clock of described recovery and the effect of described phase-locked clock, complete the decoding of parallel data, buffering, the intercepting of the rgb video data of conversion and corresponding LED module, and export the rgb video data of intercepting respectively, LED scan control signal and line scanning control signal to described RGB output terminal, LED scan control signal output terminal and line scanning control signal output terminal, export rgb video data simultaneously,
One to intercept with described RGB data and serializer that the output terminal of control signal generation module and data difference output terminal connect, and described serializer receives described RGB data and intercepts and the output of control signal generation module
described interceptingrgb video data, and will receive
described interceptingrgb video data convert serial data to and export data difference output terminal to.
2. the signal interface circuit of LED module according to claim 1, is characterized in that: described LVDS interface chip also comprises:
The intelligence sample module of the described LED module data of one monitoring;
The data back input end of one next LED module data of reception;
The data back output terminal of one output return data;
The one passback Des/CDR module be connected with described data back input end, it receives next LED module data of described data back input end input, and converts parallel data output to;
One is connected with the output terminal of described intelligence sample module, the output terminal that returns Des/CDR module and mixes the hybrid circuit of described LED module data and next LED module data;
The one passback serializer be connected with the output terminal of hybrid circuit, mixed described LED module data become serial data to export data back output terminal to next LED module data transformations by it.
3. the signal interface circuit of LED module according to claim 1, is characterized in that: described LVDS interface chip also comprises one and intercepts with described RGB data the FLASH memory be connected with control signal generation module.
4. the signal interface circuit of LED module according to claim 1, is characterized in that: described data difference input end and data difference output terminal are hot-plug interface.
5. the signal interface circuit of LED module according to claim 1, is characterized in that: described input socket is 2P socket.
6. the signal interface circuit of LED module according to claim 1, is characterized in that: described accessory power outlet is 2P socket.
7. the signal interface circuit of LED module according to claim 1, is characterized in that: described Des/CDR module comprises CDR clock data restorer and Des deserializer.
8. one kind has the LED display of the signal interface circuit of LED module described in any one of claim 1 to 7.
9., for a LVDS interface chip for LED module, it is characterized in that comprising:
For receiving the data difference input end of rgb video data;
For exporting the data difference output terminal of rgb video data;
For receiving the local clock input end of local reference clock;
For exporting the RGB output terminal of RGB data;
For exporting the LED scan control signal output terminal of LED scan control signal;
For exporting the line scanning control signal output terminal of line scanning control signal;
The Des/CDR module be connected with data difference input end, it receives the rgb video data of described data difference input end input and therefrom recovers shift clock and align with data bit, then converts the rgb video data that data difference input end inputs to parallel data and exports;
One generates the phase-locked clock generation module of phase-locked clock signal according to local reference clock;
Input end and described Des/CDR module, the output terminal of phase-locked clock generation module connects, output terminal and described RGB output terminal, the RGB data that LED scan control signal output terminal is connected with line scanning control signal output terminal intercepts and control signal generation module, it receives the parallel data that described Des/CDR module exports, and under the shift clock of described recovery and the effect of described phase-locked clock, complete the decoding of parallel data, buffering, the intercepting of the rgb video data of conversion and corresponding LED module, and export the rgb video data of intercepting respectively, LED scan control signal and line scanning control signal to described RGB output terminal, LED scan control signal output terminal and line scanning control signal output terminal, export rgb video data simultaneously,
One to intercept with described RGB data and serializer that the output terminal of control signal generation module and data difference output terminal connect, and described serializer receives described RGB data and intercepts and the output of control signal generation module
described interceptingrgb video data, and will receive
described interceptingrgb video data convert serial data to and export data difference output terminal to.
10. the LVDS interface chip for LED module according to claim 9, is characterized in that: described LVDS interface chip also comprises:
The intelligence sample module of one monitoring LED module data;
The data back input end of one next LED module data of reception;
The data back output terminal of one output return data;
The one passback Des/CDR module be connected with described data back input end, it receives next LED module data of described data back input end input, and converts parallel data output to;
One is connected with the output terminal of described intelligence sample module, the output terminal that returns Des/CDR module and mixes the hybrid circuit of described LED module data and next LED module data;
The one passback serializer be connected with the output terminal of hybrid circuit, mixed described LED module data become serial data to export data back output terminal to next LED module data transformations by it.
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| CN103426402A (en) * | 2013-08-09 | 2013-12-04 | 深圳市奥拓电子股份有限公司 | LED (light-emitting diode) display system, display module thereof and data transmission method |
| CN105321465A (en) * | 2015-10-27 | 2016-02-10 | 刘志海 | LED display screen control system based on FPGA module |
| CN106847166B (en) * | 2017-02-14 | 2020-11-27 | 江苏利鼎微系统有限公司 | A scanning method for small-pitch full-color LED display module 128 |
| CN107358908A (en) * | 2017-05-22 | 2017-11-17 | 福建祥云光电科技有限公司 | A kind of P5.75 patterns LED display |
| CN107424557B (en) * | 2017-08-16 | 2023-01-24 | 深圳市德普微电子有限公司 | Single-double-color LED display screen driving circuit |
| WO2020041939A1 (en) * | 2018-08-27 | 2020-03-05 | 西安诺瓦电子科技有限公司 | Display control system |
| CN109616066B (en) * | 2018-12-29 | 2020-12-11 | 惠科股份有限公司 | Signal generating circuit and display device using same |
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