CN109616066B - Signal generating circuit and display device using same - Google Patents
Signal generating circuit and display device using same Download PDFInfo
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- CN109616066B CN109616066B CN201811641522.4A CN201811641522A CN109616066B CN 109616066 B CN109616066 B CN 109616066B CN 201811641522 A CN201811641522 A CN 201811641522A CN 109616066 B CN109616066 B CN 109616066B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
Abstract
The application discloses signal generating circuit and display device who uses thereof, its characterized in that includes: the driving module comprises an input end and a plurality of output ends; a selection module; the input end of the selection module is connected with the output end of the driving module in a one-to-one correspondence manner; and the selection signal input end of the selection module is connected with the output end of the control module in a one-to-one correspondence manner. The output end of the selection module and the input end of the driving module are coupled to a node, the selection module enables a path to be formed between one of the output ends of the driving module and the node according to the selection signal output by the control module, and the preceding stage starting signal is coupled to the node and is superposed with the waveform output by the path to obtain the waveform of the current stage starting signal.
Description
Technical Field
The present application relates to the field of electronic circuits, and more particularly to electronic circuits for display devices.
Background
A TFT-LCD (Thin Film Transistor Liquid Crystal Display) is one of the major types of flat panel displays, and has become an important Display platform in modern IT and video products. The main driving principle of TFT-LCD is that the system main board connects R/G/B compression signal, control signal and power supply with the conductor on PCB board through wire, the data is processed by TCON (Timing Controller) IC on PCB board, and then passes through S-COF (Source-Chip on Film) and G-COF (G-COF on Film) by PCB board
The (Gate-on Film, Gate thin Film driving Chip) is connected to the display region, so that the LCD obtains a desired power supply and signal.
A TCON IC (timing control chip) controls the G-COF to start scanning in the vertical direction, and a line start signal needs to be supplied. In different application situations, different ways of row start signals are required.
Disclosure of Invention
The present application is directed to a signal generating circuit, which can provide various row start signals through setting on a PCB.
The purpose of the application and the technical problem to be solved are realized by adopting the following technical scheme. According to the present application, a signal generating circuit comprises: the driving module comprises an input end and a plurality of output ends; a selection module; the input end of the selection module is connected with the output end of the driving module in a one-to-one correspondence manner; and the selection signal input end of the selection module is connected with the output end of the control module in a one-to-one correspondence manner. The output end of the selection module and the input end of the driving module are coupled to a node P, the selection module enables a path to be formed between one of the output ends of the driving module and the node P according to the selection signal output by the control module, and the preceding stage starting signal is coupled to the node P and is superposed with the voltage waveform output by the path to obtain the current stage starting signal.
In an embodiment of the present application, the driving module is composed of a plurality of flip-flops, including a first flip-flop, a second flip-flop, and a third flip-flop, each of the flip-flops includes an input terminal, an output terminal, and a clock signal input terminal.
In an embodiment of the present application, an output of the first flip-flop is connected to an input of the second flip-flop, and an output of the second flip-flop is connected to an input of the third flip-flop.
In an embodiment of the present application, the clock signal input terminals of the first, second and third flip-flops are coupled to a same clock signal.
In one embodiment of the present application, the first, second and third flip-flops sequentially output high levels for three consecutive clock signal periods after the previous start signal is transmitted to the input terminal of the first flip-flop, and each high level outputs one clock period of the holding clock signal.
In an embodiment of the present application, the selection module is composed of a plurality of switch sets, including a first switch set, a second switch set, and a third switch set, where each switch set is composed of a plurality of switches connected in series, and includes a first switch and a second switch.
In an embodiment of the application, output ends of the first, second, and third flip-flops are used as output ends of the driving module, input ends of the first, second, and third switch groups are used as input ends of the selecting module, and output ends of the first, second, and third flip-flops are respectively connected to input ends of the first, second, and third switch groups in a one-to-one correspondence manner.
In an embodiment of the application, the switches of the first, second and third switch groups are composed of two fets, a source of the first switch of each switch group is used as an input terminal of the switch group, a drain of the second switch is used as an output terminal of the switch group, the drain of the first switch is connected to the source of the second switch to form the switch group, gates of the first switches of the first, second and third switch groups are coupled to a node to be used as a first selection signal input terminal of the selection module, and gates of the first switches of the first, second and third switch groups are coupled to another node to be used as a second selection signal input terminal of the selection module.
In an embodiment of the present application, the first switch and the second switch of the first switch group and the second switch group have different turn-on signals, and the first switch and the second switch of the third switch group have the same turn-on signal.
In an embodiment of the present application, in the selection module, the P-channel conducting fet and the N-channel conducting fet are used as two switches with different conducting signals, and one of the P-channel conducting fet and the N-channel conducting fet is optionally used as a switch with the same conducting signal of the third switch group.
In an embodiment of the application, the control module outputs a plurality of selection signals, including a first selection signal and a second selection signal, where the first and second selection signals are the same or different, and the specific output selection signal is set according to actual needs.
In an embodiment of the present application, a first selection signal output by the control module is output to the first switch of the first, second, and third switch sets, and a second selection signal output by the control module is output to the second switch of the first, second, and third switch sets.
In an embodiment of the present application, the output end of the control module outputs the selection signal to the selection module, and the selection module turns on or off the switch set according to the received selection signal.
In an embodiment of the present application, at most one of the first, second, and third switch sets is in a conducting state during the same time interval.
In an embodiment of the present application, the output terminals of the first, second, and third switch sets are coupled to the same node P as the output terminal of the selection module, the input terminal of the first flip-flop, and the previous start signal.
The purpose of the application and the technical problem to be solved can be further realized by adopting the following technical measures.
Another object of the present application is to provide a display device.
In an embodiment of the present application, a signal generating circuit includes: the driving module comprises an input end and a plurality of output ends; a selection module; the input ends of the selection modules are connected with the output ends of the driving modules in a one-to-one correspondence manner; and the selection signal input end of the selection module is connected with the output ends of the control module in a one-to-one correspondence manner. The output end of the selection module and the input end of the driving module are coupled to a node P, the selection module enables a path to be formed between one of the output ends of the driving module and the node P according to a selection signal output by the control module, and the preceding-stage starting signal is coupled to the node P and is superposed with a voltage waveform output by the path to obtain the current-stage starting signal.
This application can provide multiple row's initial signal through the settlement on the PCB board, improves the commonality of material, reduces the management and control cost.
Drawings
FIG. 1 is a functional block diagram of the present application;
FIG. 2 is a schematic circuit diagram of the present application;
FIG. 3 is a waveform diagram of the present stage start signal STV2 according to an embodiment of the present application;
FIG. 4 is a waveform diagram of the present stage start signal STV2 according to an embodiment of the present application;
fig. 5 is a waveform diagram of the present stage start signal STV2 according to an embodiment of the present application.
Detailed Description
The drawings and description are to be regarded as illustrative in nature, and not as restrictive. In the drawings, elements having similar structures are denoted by the same reference numerals.
In addition, in the description, unless explicitly described to the contrary, the word "comprise" will be understood to mean that the recited components are included, but not to exclude any other components.
To further illustrate the technical means and effects adopted by the present application to achieve the predetermined objects, the following detailed description is provided for a signal generating circuit and a line start signal generating circuit of a display device according to the present application with reference to the accompanying drawings and specific embodiments, and the detailed description thereof follows.
Fig. 1 is a schematic diagram of functional modules of the present application, please refer to fig. 1, in an embodiment of the present application, a circuit is composed of three modules, including: a driving module 10, which includes an input end and three output ends; a selection module 11; the input end of the selection module 11 is correspondingly connected with the output end of the driving module 10; and the control module 12 comprises two output ends, and the selection signal input end of the selection module 11 is connected with the output ends of the control module 12 in a one-to-one correspondence manner.
In an embodiment of the present application, referring to fig. 1, an output terminal of a selection module 11 and an input terminal of the driving module 10 are coupled to a node P, the selection module 11 enables a path to be formed between one of three output terminals of the driving module 10 and the node P according to a selection signal output by the control module 12, a previous start signal STV1 is coupled to the node P, and a waveform of the previous start signal STV1 and a waveform output by the path are superimposed to obtain a current start signal STV 2.
Fig. 2 is a circuit diagram of the present application, please refer to fig. 2, in an embodiment of the present application, the driving module 10 is composed of three D flip-flops, including a first flip-flop 101, a second flip-flop 102 and a third flip-flop 103, each of the three D flip-flops includes an input end D, an output end Q and a clock signal input end C, starting from a rising edge of the flip-flop, a characteristic equation is Q ═ D, when an input signal of the clock signal input end C is at the rising edge, an output level of the output end Q is equal to a level of the input signal of the input end, and a clock signal CLK period is maintained.
In an embodiment of the present application, referring to fig. 2, an output terminal of the first flip-flop 101 is connected to an input terminal of the second flip-flop 102, and an output terminal of the second flip-flop 102 is connected to the third flip-flop 103.
In an embodiment of the present application, referring to fig. 2, the clock signal input terminals of the first flip-flop 101, the second flip-flop 102 and the third flip-flop 103 are connected to the same clock signal CLK.
In an embodiment of the present application, referring to fig. 2, the front-stage start signal STV1 outputs a high level signal sequentially in three consecutive clock signal cycles after the input terminal of the first flip-flop 101 passes through, the first flip-flop 101, the second flip-flop 102, and the third flip-flop 103 output a high level signal sequentially, and each high level output holds one clock cycle of the clock signal.
In an embodiment of the present application, referring to fig. 2, the selection module 11 is composed of three switch sets including a first switch set 117, a second switch set 118, and a third switch set 119, each switch set being composed of two switches including a first switch and a second switch.
In an embodiment of the present application, referring to fig. 1 and fig. 2, a field effect transistor is used as a switch of the selection module 11, the drains of the switches 111, 112, 113 are connected to the sources of the switches 114, 115, 116 to form switch groups 117, 118, 119, the sources of the switches 111, 112, 113 are used as input terminals of the switch groups 117, 118, 119, the drains of the switches 114, 115, 116 are used as output terminals of the switch groups 117, 118, 119, the gates of the switches 111, 112, 113 are coupled to a node as a first selection signal input terminal of the selection module 11, and the gates of the switches 114, 115, 116 are coupled to another node as a second selection signal input terminal of the selection module 11.
In an embodiment of the present application, referring to fig. 2, at most one of the switch sets 117, 118, 119 is in a conducting state during the same time interval.
In an embodiment of the present application, please refer to fig. 1 and fig. 2 simultaneously, the control module 12 outputs two selection signals, including a first selection signal a and a second selection signal B, where the first selection signal a and the second selection signal B may be the same or different, and may be specifically set according to actual requirements.
In an embodiment of the present application, referring to fig. 2, the second switch 114 of the first switch group 117 and the first switch 112 of the second switch group 118 are N-channel conducting fets, and the first switch 111 of the first switch group 117, the second switch 115 of the second switch group 118, and the first switch 113 of the third switch group 119, and the second switch 116 are P-channel conducting fets.
In an embodiment of the present application, referring to fig. 1 and fig. 2, output ends of the first flip-flop 101, the second flip-flop 102, and the third flip-flop 103 are used as output ends of the driving module 10, input ends of the first switch group 117, the second switch group 118, and the third switch group 119 are used as input ends of the selecting module 11, and output ends of the flip- flops 101, 102, and 103 are respectively connected to input ends of the switch groups 117, 118, and 119 in a one-to-one correspondence manner, in an embodiment in which a fet is used as a switch, output ends of the flip- flops 101, 102, and 103 are connected to sources of the fets 111, 112, and 113.
In an embodiment of the present application, please refer to fig. 1 and fig. 2, the output end of the control module 12 transmits the selection signal A, B to the selection module 11, and the selection module 11 respectively turns on or off different switch sets according to the received selection signal.
In an embodiment of the present application, referring to fig. 2, the output terminals of the switch sets 117, 118, and 119 as the output terminals of the selection module 11 are coupled to the same node P as the input terminal of the flip-flop 101 and the previous start signal STV 1.
Fig. 3 is a schematic diagram of waveforms of the present stage start signal STV2 in an embodiment of the present application, referring to fig. 3, in the present embodiment, the switches 111, 113, 115, and 116 are P-channel conductive fets, the switches 112 and 114 are N-channel conductive fets, the select signal A, B is a low level signal, which is respectively input to the gates of the switches 111, 112, and 113 and the gates of the switches 114, 115, and 116, at this time, the switch group 119 is turned on, the switch groups 117 and 118 are turned off, the output terminals of the flip- flops 101, 102, and 103, and the timing waveforms of the previous stage start signal STV1 and the present stage start signal STV2 are as shown in fig. 3, and the waveform of the present stage start signal STV2 is obtained by superimposing the voltage waveforms of the previous stage start signal STV1 and the output terminal of the flip-.
Fig. 4 is a schematic diagram of waveforms of the present stage start signal STV2 in an embodiment of the present application, referring to fig. 4, in the present embodiment, the switches 111, 113, 115, and 116 are P-channel conductive fets, the switches 112 and 114 are N-channel conductive fets, the selection signal A, B is a high level signal and a low level signal, and is respectively input to the gates of the switches 111, 112, and 113 and the gates of the switches 114, 115, and 116, at this time, the switch group 118 is turned on, the switch groups 117 and 119 are turned off, timing waveforms of the output terminals of the flip- flops 101, 102, and 103, the previous stage start signal STV1, and the present stage start signal STV2 are as shown in fig. 4, and the waveform of the present stage start signal STV2 is obtained by superimposing the voltage waveforms of the previous stage start signal STV1 and the voltage waveform of the output terminal.
Fig. 5 is a waveform diagram of the present stage start signal STV2 in an embodiment of the present application, referring to fig. 4, in the present embodiment, the switches 111, 113, 115, and 116 are P-channel conductive fets, the switches 112 and 114 are N-channel conductive fets, the selection signal A, B is a low level signal and a high level signal, and is respectively input to the gates of the switches 111, 112, and 113 and the gates of the switches 114, 115, and 116, at this time, the switch group 117 is turned on and the switch groups 118 and 119 are turned off, timing waveforms of the output terminals of the flip- flops 101, 102, and 103, the previous stage start signal STV1, and the present stage start signal STV2 are as shown in fig. 4, and a waveform of the present stage start signal STV2 is obtained by superimposing the previous stage start signal STV1 and a voltage waveform of the output terminal of the flip-flop 101.
The application can provide various row starting signals through setting on the PCB. Improve the commonality of material, reduce the management and control cost.
The terms "in some embodiments" and "in various embodiments" are used repeatedly. The terms generally do not refer to the same embodiment; it may also refer to the same embodiment. The terms "comprising," "having," and "including" are synonymous, unless the context dictates otherwise.
Although the present application has been described with reference to specific embodiments, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the application, and all changes, substitutions and alterations that fall within the spirit and scope of the application are to be understood as being covered by the following claims.
Claims (9)
1. A signal generating circuit, comprising:
the driving module comprises a dry input end and a plurality of output ends, wherein a plurality of input ends of the driving module are respectively used for inputting a preceding stage starting signal and a clock signal, and the driving module is used for controlling the output ends of the driving module to output signals according to the preceding stage starting signal and the clock signal;
the selection module comprises a plurality of input ends, a plurality of selection signal input ends and a plurality of output ends, and the input ends of the selection module are connected with the output ends of the driving module in a one-to-one correspondence manner;
the control module comprises a plurality of output ends, and the selection signal input ends of the selection module are connected with the output ends of the control module in a one-to-one correspondence manner;
the output end of the selection module is coupled to the input end of the driving module, the selection module enables one of the output ends of the driving module to form a path with the node according to a selection signal output by the control module, and the node superposes the preceding stage start signal and a waveform output by the path to obtain a current stage start signal;
wherein the driving module is composed of a plurality of triggers.
2. The signal generating circuit of claim 1, wherein the driving module comprises a plurality of flip-flops, including a first flip-flop, a second flip-flop, and a third flip-flop, each of the flip-flops having an input, an output, and a clock signal input, the output of the first flip-flop being coupled to the input of the second flip-flop, the output of the second flip-flop being coupled to the input of the third flip-flop.
3. The signal generating circuit as claimed in claim 2, wherein the first, second and third flip-flops sequentially output high levels for three consecutive clock signal periods after the previous stage start signal is applied to the input terminal of the first flip-flop, and each high level output is maintained for one clock period.
4. The signal generating circuit of claim 2, wherein the selecting module comprises a plurality of switch sets including a first switch, a second switch and a third switch, each switch set comprises a plurality of switches including a first switch and a second switch, wherein the conducting signals of the first switch and the second switch of the first switch set and the second switch set are different, and the conducting signals of the first switch and the second switch of the third switch set are the same.
5. The signal generating circuit as claimed in claim 4, wherein the output terminals of the first, second and third flip-flops are used as the output terminals of the driving module, the input terminals of the first, second and third switch groups are used as the input terminals of the selecting module, and the output terminals of the first, second and third flip-flops are respectively connected to the input terminals of the first, second and third switch groups in a one-to-one correspondence.
6. The signal generating circuit of claim 4, wherein the control module outputs a selection signal to the first, second, and third switch sets, wherein the first selection signal is output to a first switch of the first, second, and third switch sets, and the second selection signal is output to a second switch of the first, second, and third switch sets.
7. The signal generating circuit of claim 4, wherein at most one of the first, second, and third switch groups is in a conducting state during a same time interval.
8. The signal generating circuit of claim 1, wherein the control module outputs a plurality of selection signals including a first selection signal and a second selection signal, and the first and second selection signals are the same or different.
9. A display device, comprising:
a signal generating circuit as claimed in any one of claims 1 to 8.
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| CN201811641522.4A CN109616066B (en) | 2018-12-29 | 2018-12-29 | Signal generating circuit and display device using same |
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| CN201811641522.4A CN109616066B (en) | 2018-12-29 | 2018-12-29 | Signal generating circuit and display device using same |
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