CN106652949A - Gate drive circuit and liquid crystal display device - Google Patents
Gate drive circuit and liquid crystal display device Download PDFInfo
- Publication number
- CN106652949A CN106652949A CN201611230875.6A CN201611230875A CN106652949A CN 106652949 A CN106652949 A CN 106652949A CN 201611230875 A CN201611230875 A CN 201611230875A CN 106652949 A CN106652949 A CN 106652949A
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- Prior art keywords
- oxide
- metal
- semiconductor
- goa
- drive
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- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 11
- 239000004065 semiconductor Substances 0.000 claims description 65
- 230000000694 effects Effects 0.000 abstract description 3
- 101100478187 Arabidopsis thaliana MOS4 gene Proteins 0.000 description 4
- 101100461812 Arabidopsis thaliana NUP96 gene Proteins 0.000 description 4
- 102100030393 G-patch domain and KOW motifs-containing protein Human genes 0.000 description 4
- 101150090280 MOS1 gene Proteins 0.000 description 4
- 101100401568 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) MIC10 gene Proteins 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 229910052982 molybdenum disulfide Inorganic materials 0.000 description 4
- 238000012423 maintenance Methods 0.000 description 3
- 102100031699 Choline transporter-like protein 1 Human genes 0.000 description 2
- 102100035954 Choline transporter-like protein 2 Human genes 0.000 description 2
- 102100040862 Dual specificity protein kinase CLK1 Human genes 0.000 description 2
- 101000940912 Homo sapiens Choline transporter-like protein 1 Proteins 0.000 description 2
- 101000948115 Homo sapiens Choline transporter-like protein 2 Proteins 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 102100040844 Dual specificity protein kinase CLK2 Human genes 0.000 description 1
- 102100040856 Dual specificity protein kinase CLK3 Human genes 0.000 description 1
- 102100040858 Dual specificity protein kinase CLK4 Human genes 0.000 description 1
- 101000749294 Homo sapiens Dual specificity protein kinase CLK1 Proteins 0.000 description 1
- 101000749291 Homo sapiens Dual specificity protein kinase CLK2 Proteins 0.000 description 1
- 101000749304 Homo sapiens Dual specificity protein kinase CLK3 Proteins 0.000 description 1
- 101000749298 Homo sapiens Dual specificity protein kinase CLK4 Proteins 0.000 description 1
- 230000035800 maturation Effects 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Liquid Crystal Display Device Control (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention provides a gate drive circuit and a liquid crystal display device. The gate drive circuit comprises a GOA signal drive module, a selecting module and a GOA unit, wherein the GOA signal drive module is used for generating N paths of original drive signals and transmitting the N paths of original drive signals to the selecting module; the selecting module is used for receiving the N paths of original drive signals transmitted by the GOA signal drive module, and processing the N paths of original drive signals, so that M paths of GOA drive signals are obtained, and then the M paths of GOA drive signals are transmitted to the GOA unit, wherein M is greater than N. For the gate drive circuit provided by the invention, after the N paths of original drive signals are processed through the selecting module, the M paths of GOA drive signals are output, M is greater than N, the original drive signals can be reduced under the premise that the drive effect is not influenced, thus hardware configuration of the gate drive circuit is simplified, and the drive cost and panel logic power dissipation are reduced.
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of gate driver circuit and liquid crystal indicator.
Background technology
With the development of flat panel display, high-resolution, high-contrast, high refresh rate, narrow frame, slimming into
For FPD development trend.Liquid crystal display at present is still the main product of FPD.In order to realize the narrow side of liquid crystal panel
Frame, slimming and low cost, the exploitation of gate driver circuit (Gate Driver On Array, abbreviation GOA) and application phase
To maturation.
It is illustrated in figure 18 clocks in prior art and drives GOA circuit frameworks.Wherein GOA unit circuit is as shown in Fig. 2 bag
Include：Pull-up control module a, pull-up module b, drop-down module c, drop-down maintenance module d and drop-down maintenance module e.When G (N-5) is
During high potential, Q (N) is electrically charged and draws high, and now T21 is opened, and G (N) pull-up is exported high potential scanning signal by CLK high potentials,
When G (N+5) is high potential, drop-down module is by G (N) and Q (N) while dragging down, the operating point current potential of drop-down maintenance module is Q
(N) electronegative potential and LC1 (or LC2) high potential, the cycle of wherein LC1 and LC2 is 2 times of frame periods, and dutycycle is 1/2 low frequency letter
Number, the cycle of LC1 and LC2 phases 1/2, GOA control sequentials are as shown in Figure 3.
Simplify GOA circuit drives control signals in order to further, reduce driving cost and Panel Logic power consumption, need one kind badly
Gate driver circuit is realizing above-mentioned target.
The content of the invention
The present invention provides a kind of gate driver circuit and liquid crystal indicator, to solve prior art in GOA circuits drive
Dynamic control signal is more, the technical problem for driving cost larger.
One aspect of the present invention provides a kind of gate driver circuit, including：GOA signal drive modules, selecting module and GOA
Unit, wherein, GOA signals drive module is used to produce the original drive signal in N roads, and sends the original drive signal in N roads to choosing
Module is selected, selecting module is used to receive the original drive signal in N roads of GOA signals drive module transmission, and drive original to N roads is believed
Number processed, to obtain M roads GOA drive signals, then sent M roads GOA drive signals to GOA unit；M is more than N.
Further, GOA signals drive module include for send the first control signal the first control signal generator,
For sending the second control signal generator of the second control signal and original driving for sending the original drive signal in N roads
Signal generator.
Further, selecting module include the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, for exporting
First signal output submodule of GOA drive signals and secondary signal output sub-module, wherein, the grid of the first metal-oxide-semiconductor and
The grid of two metal-oxide-semiconductors is connected with the first control signal generator；The grid of the 3rd metal-oxide-semiconductor and the grid of the 4th metal-oxide-semiconductor with
Second control signal generator is electrically connected；The source electrode of the first metal-oxide-semiconductor, the source electrode of the second metal-oxide-semiconductor, the source electrode of the 3rd metal-oxide-semiconductor and
The source electrode of four metal-oxide-semiconductors is connected with original driving signal generator；First metal-oxide-semiconductor drain electrode and the 4th metal-oxide-semiconductor drain electrode with
First signal output submodule is connected；Second metal-oxide-semiconductor drain electrode and the 3rd metal-oxide-semiconductor drain electrode with secondary signal output sub-module
It is connected.
Further, the value of M is the twice of N values.
Further, original driving signal generator is used to produce the original drive signal in 4 tunnels, the first signal output submodule
4 road GOA drive signals are exported respectively with secondary signal output sub-module.
Further, the first signal output submodule and secondary signal output sub-module are connected respectively with 4 GOA units,
To send 4 road GOA drive signals to connected GOA unit, wherein, each GOA unit receives GOA all the way and drives letter
Number.
Further, the first metal-oxide-semiconductor and the 3rd metal-oxide-semiconductor are p-type metal-oxide-semiconductor, and the second metal-oxide-semiconductor and the 4th metal-oxide-semiconductor are N-type MOS
Pipe.
Another aspect of the present invention provides a kind of liquid crystal indicator, including above-mentioned gate driver circuit, and drives with grid
The display floater of dynamic circuit connection.
Above-mentioned gate driver circuit and liquid crystal indicator, it is defeated after selecting module processes the original drive signal in N roads
Go out M roads GOA drive signals, because M is more than N, can not affect to reduce original drive signal on the premise of driving effect, so as to letter
Change the hardware configuration of gate driver circuit, reduce driving cost and Panel Logic power consumption.
Description of the drawings
Hereinafter the present invention will be described in more detail based on embodiment and refer to the attached drawing.Wherein：
Fig. 1 is that 8 clock of the prior art drives GOA circuit frameworks；
Fig. 2 is GOA unit circuit diagram corresponding with Fig. 1；
Fig. 3 is the control sequential figure of GOA unit corresponding with Fig. 2；
The grid electrode drive circuit structure schematic diagram that Fig. 4 is provided for one embodiment of the invention；
The grid electrode drive circuit structure schematic diagram that Fig. 5 is provided for another embodiment of the present invention；
The grid electrode drive circuit structure schematic diagram that Fig. 6 is provided for further embodiment of this invention；
The sequential chart of each signal that Fig. 7 is produced for the GOA signals drive module that one embodiment of the invention is provided；
The sequential chart of each signal of the selecting module output that Fig. 8 is provided for one embodiment of the invention.
In the accompanying drawings, identical part uses identical reference.Accompanying drawing is not drawn according to actual ratio.
Specific embodiment
Below in conjunction with accompanying drawing, the invention will be further described.
Fig. 4 is refer to, the embodiment of the present invention provides a kind of gate driver circuit, including：GOA signals drive module 1, selection
Module 2 and GOA unit 3.Wherein, GOA signals drive module 1 is used to produce the original drive signal in N roads, and by the original drive in N roads
Dynamic signal sends selecting module 2 to, and selecting module 2 is used to receive the original drive signal in N roads of the transmission of GOA signals drive module 1,
And the original drive signal in N roads is processed, to obtain M roads GOA drive signals, then send M roads GOA drive signals to GOA
Unit 3, M is more than N.Preferably, the value of M for N values twice, i.e. M=2N.
Above-mentioned gate driver circuit, after selecting module 2 processes the original drive signal in N roads, output M road GOA drive
Signal, M is more than N, can not affect to reduce original drive signal on the premise of driving effect, so as to simplify gate driver circuit
Hardware configuration, reduces driving cost and Panel Logic power consumption.
In a specific embodiment of the invention, GOA signals drive module 1 include for send the first control signal the
One control signal generator 11, the second control signal generator 12 for sending the second control signal and for sending N roads
The original driving signal generator 13 of original drive signal.
Refer to Fig. 5, in another specific embodiment of the invention, selecting module 2 include the first metal-oxide-semiconductor MOS1, second
Metal-oxide-semiconductor MOS2, the 3rd metal-oxide-semiconductor MOS3, the 4th metal-oxide-semiconductor MOS4, the first signal output submodule for exporting GOA drive signals
21 and secondary signal output sub-module 22, wherein, the grid of the grid of the first metal-oxide-semiconductor MOS1 and the second metal-oxide-semiconductor MOS2 is with
One control signal generator 11 connects；The grid of the 3rd metal-oxide-semiconductor MOS3 and the grid of the 4th metal-oxide-semiconductor MOS4 are believed with the second control
Number generator 12 is electrically connected；The source electrode of the first metal-oxide-semiconductor MOS1, the source electrode of the second metal-oxide-semiconductor MOS2, the source electrode of the 3rd metal-oxide-semiconductor MOS3
It is connected with original driving signal generator 13 with the source electrode of the 4th metal-oxide-semiconductor MOS4；The drain electrode and the 4th of the first metal-oxide-semiconductor MOS1
The drain electrode of metal-oxide-semiconductor MOS4 is connected with the first signal output submodule 21；The drain electrode of the second metal-oxide-semiconductor MOS2 and the 3rd metal-oxide-semiconductor
The drain electrode of MOS3 is connected with secondary signal output sub-module 22.First metal-oxide-semiconductor and the 3rd metal-oxide-semiconductor are p-type metal-oxide-semiconductor, the 2nd MOS
Pipe and the 4th metal-oxide-semiconductor are N-type metal-oxide-semiconductor.Metal-oxide-semiconductor is insulating properties FET in integrated circuits.
In a specific embodiment of the invention, original driving signal generator 13 is used to produce the original drive signal in 4 tunnels,
First signal output submodule 21 and secondary signal output sub-module 22 export respectively 4 road GOA drive signals.Specifically, as schemed
6th, shown in Fig. 7.Original driving signal generator 13 produces 4 road signals, respectively CLK_a, CLK_b, CLK_c, CLK_d, when the
The first control signal CTL1 that one control signal generator 11 is produced is high potential, the second control signal generator 12 produce the
When two control signals CTL2 are electronegative potential, the first signal output submodule 21 is sequentially output CLK_a, CLK_b, CLK_c, CLK_d
Clock high potential, i.e. signal CLK1, CLK2, CLK3 and CLK4.When the first control that the first control signal generator 11 is produced
Signal CTL1 is electronegative potential, when the second control signal CTL2 that the second control signal generator 12 is produced is high potential, the second letter
Number output sub-module 22 is sequentially output the clock high potential of CLK_a, CLK_b, CLK_c, CLK_d, i.e. signal CLK5, CLK6,
CLK7 and CLK8.Output waveform is as shown in Figure 8.
First signal output submodule 21 and secondary signal output sub-module 22 are connected respectively with 4 GOA units 3, by 4
Road GOA drive signals send connected GOA unit 3 to, wherein, each GOA unit 3 receives GOA drive signals all the way.
Specifically, the first signal output submodule 21 connects respectively 4 different GOA units 3 with secondary signal output sub-module 22, with
Each GOA unit 3 is set to receive GOA drive signals all the way.
The embodiment of the present invention also provides a kind of liquid crystal indicator, including the gate driver circuit in above-described embodiment, with
And the display floater being connected with gate driver circuit.
Although by reference to preferred embodiment, invention has been described, in the situation without departing from the scope of the present invention
Under, various improvement can be carried out to it and part therein can be replaced with equivalent.Especially, as long as there is no structure punching
Prominent, the every technical characteristic being previously mentioned in each embodiment can combine in any way.The invention is not limited in text
Disclosed in specific embodiment, but including all technical schemes for falling within the scope of the appended claims.
Claims (8)
1. a kind of gate driver circuit, it is characterised in that include：GOA signal drive modules, selecting module and GOA unit, its
In, the GOA signals drive module is used to produce the original drive signal in N roads, and sends original drive signal described in N roads to institute
Selecting module is stated, the selecting module is used to receive original drive signal described in the N roads that the GOA signals drive module is transmitted,
And original drive signal described in N roads is processed, to obtain M roads GOA drive signals, then GOA drive signals described in M roads are passed
Give the GOA unit；M is more than N.
2. gate driver circuit according to claim 1, it is characterised in that the GOA signals drive module include for
Send the first control signal generator of the first control signal, the second control signal generator for sending the second control signal
And for sending the original driving signal generator of the original drive signal in N roads.
3. gate driver circuit according to claim 2, it is characterised in that the selecting module include the first metal-oxide-semiconductor, the
Two metal-oxide-semiconductors, the 3rd metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, the first signal output submodule and second for exporting the GOA drive signals
Signal output submodule, wherein, the grid of first metal-oxide-semiconductor is controlled with the grid of second metal-oxide-semiconductor with described first
Signal generator connects；The grid of the 3rd metal-oxide-semiconductor is produced with the grid of the 4th metal-oxide-semiconductor with second control signal
Raw device electrical connection；The source electrode of first metal-oxide-semiconductor, the source electrode of second metal-oxide-semiconductor, the source electrode of the 3rd metal-oxide-semiconductor and described
The source electrode of the 4th metal-oxide-semiconductor is connected with the original driving signal generator；The drain electrode of first metal-oxide-semiconductor and the described 4th
The drain electrode of metal-oxide-semiconductor is connected with the first signal output submodule；The drain electrode of second metal-oxide-semiconductor and the 3rd metal-oxide-semiconductor
Drain electrode be connected with the secondary signal output sub-module.
4. the gate driver circuit according to any one of claim 1-3, it is characterised in that the value of M for N values twice.
5. gate driver circuit according to claim 4, it is characterised in that the original driving signal generator is used to produce
Original drive signal described in raw 4 tunnels, the first signal output submodule and the secondary signal output sub-module export respectively 4
GOA drive signals described in road.
6. gate driver circuit according to claim 5, it is characterised in that the first signal output submodule and described
Secondary signal output sub-module is connected respectively with 4 GOA units, GOA drive signals described in 4 tunnels is sent to and is connected with it
The GOA unit for connecing, wherein, each described GOA unit receives the GOA drive signals all the way.
7. gate driver circuit according to claim 3, it is characterised in that first metal-oxide-semiconductor and the 3rd metal-oxide-semiconductor
For p-type metal-oxide-semiconductor, second metal-oxide-semiconductor and the 4th metal-oxide-semiconductor are N-type metal-oxide-semiconductor.
8. a kind of liquid crystal indicator, it is characterised in that including the gate driver circuit described in any one of claim 1-7, with
And the display floater being connected with the gate driver circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611230875.6A CN106652949B (en) | 2016-12-28 | 2016-12-28 | Gate driving circuit and liquid crystal display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611230875.6A CN106652949B (en) | 2016-12-28 | 2016-12-28 | Gate driving circuit and liquid crystal display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106652949A true CN106652949A (en) | 2017-05-10 |
| CN106652949B CN106652949B (en) | 2019-03-26 |
Family
ID=58831935
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611230875.6A Active CN106652949B (en) | 2016-12-28 | 2016-12-28 | Gate driving circuit and liquid crystal display device |
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| Country | Link |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109616066A (en) * | 2018-12-29 | 2019-04-12 | 惠科股份有限公司 | Signal generating circuit and its display device of application |
| WO2022007105A1 (en) * | 2020-07-09 | 2022-01-13 | 深圳市华星光电半导体显示技术有限公司 | Gate electrode driving design method and apparatus, and electronic device |
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| JPH07287208A (en) * | 1994-04-18 | 1995-10-31 | Sony Corp | Scanning circuit for display device, and plane display device |
| CN102654968A (en) * | 2011-11-25 | 2012-09-05 | 京东方科技集团股份有限公司 | Shift register, grid driver and display device |
| US20130076808A1 (en) * | 2011-09-27 | 2013-03-28 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Liquid crystal display device and driving method thereof |
| CN104835466A (en) * | 2015-05-20 | 2015-08-12 | 京东方科技集团股份有限公司 | Scan driving circuit, array substrate, display device and driving method |
| CN105405406A (en) * | 2015-12-29 | 2016-03-16 | 武汉华星光电技术有限公司 | Gate drive circuit and display using same |
-
2016
- 2016-12-28 CN CN201611230875.6A patent/CN106652949B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07287208A (en) * | 1994-04-18 | 1995-10-31 | Sony Corp | Scanning circuit for display device, and plane display device |
| US20130076808A1 (en) * | 2011-09-27 | 2013-03-28 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Liquid crystal display device and driving method thereof |
| CN102654968A (en) * | 2011-11-25 | 2012-09-05 | 京东方科技集团股份有限公司 | Shift register, grid driver and display device |
| CN104835466A (en) * | 2015-05-20 | 2015-08-12 | 京东方科技集团股份有限公司 | Scan driving circuit, array substrate, display device and driving method |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109616066A (en) * | 2018-12-29 | 2019-04-12 | 惠科股份有限公司 | Signal generating circuit and its display device of application |
| CN109616066B (en) * | 2018-12-29 | 2020-12-11 | 惠科股份有限公司 | Signal generating circuit and display device using same |
| WO2022007105A1 (en) * | 2020-07-09 | 2022-01-13 | 深圳市华星光电半导体显示技术有限公司 | Gate electrode driving design method and apparatus, and electronic device |
| US11734483B2 (en) | 2020-07-09 | 2023-08-22 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Method of driving design on gate electrodes, and device and electronic device thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106652949B (en) | 2019-03-26 |
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Address after: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Patentee after: TCL China Star Optoelectronics Technology Co.,Ltd. Address before: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Patentee before: Shenzhen China Star Optoelectronics Technology Co.,Ltd. |