CN104157252B

CN104157252B - Shifting register, gate driving circuit and display device

Info

Publication number: CN104157252B
Application number: CN201410367798.3A
Authority: CN
Inventors: 张毅; 玄明花; 金泰逵
Original assignee: BOE Technology Group Co Ltd; Ordos Yuansheng Optoelectronics Co Ltd
Current assignee: BOE Technology Group Co Ltd; Ordos Yuansheng Optoelectronics Co Ltd
Priority date: 2014-07-29
Filing date: 2014-07-29
Publication date: 2017-01-18
Anticipated expiration: 2034-07-29
Also published as: CN104157252A

Abstract

The invention discloses a shifting register, a gate driving circuit and a display device. The shifting register provided by the embodiment of the invention comprises an input module, a reset module, a driving module, a first output module and a second output module. The shifting register utilizes a direct-current power supply as the output source for the output signal output by an output signal end; compared with the output source adopting a clock signal as the output signal, the direct current power supply can avoid the problem about the unstable output signal caused by own high-frequency periodic conversion characteristic of the clock signal, and reduce the influence of a circuit load on the output signal, and can further improve the stability and the reliability of the output signal output by the shifting register.

Description

A kind of shift register, gate driver circuit and display device

Technical field

The present invention relates to display technology field, more particularly, to a kind of shift register, gate driver circuit and display device.

Background technology

In TFT thin film transistor monitor, generally pass through gate drive apparatus each thin film transistor (TFT) to pixel region The grid of (tft, thin film transistor) provides gate drive signal.Gate drive apparatus can pass through array processes It is formed on the array base palte of liquid crystal display, i.e. array base palte row cutting (gate driver on array, goa) technique, This integrated technique not only saves cost, and can accomplish the symmetrical design for aesthetic in liquid crystal panel (panel) both sides, with When, also eliminate binding (bonding) region and the fan-out of grid integrated circuits (ic, integrated circuit) (fan-out) wiring space, such that it is able to realize the design of narrow frame；And, this integrated technique may be omitted with grid The bonding technique of scan-line direction, thus improve production capacity and yield.

Existing gate driver circuit is added in liquid crystal after mainly changing the clock signal of input by shift register On the controlling grid scan line of display floater, and clock signal is because of its own high-frequency periodic transformation's characteristic and transmission line Self-resistance, it may occur that signal delay and decay, thus leading to export stable voltage, and then have impact on display floater The normal work of the thin film transistor (TFT) being connected with controlling grid scan line, causes picture to show uneven.

Content of the invention

In view of this, the embodiment of the present invention provides a kind of shift register, gate driver circuit and display device, in order to solve The output voltage certainly being led to by clock signal by the voltage source of the output voltage of shift register in prior art is unstable Problem.

Therefore, a kind of shift register provided in an embodiment of the present invention, comprising: input module, reseting module, drive mould Block, the first output module and the second output module；Wherein,

Described input module, for, under the control of the first clock signal, the input signal at input signal end being supplied to Primary nodal point；

Described drive module, for, under the control of the voltage of described primary nodal point, second clock signal being supplied to Two nodes；And between described input signal end and described primary nodal point during no signal transmission, drag down or draw high described first The voltage of node；

Described reseting module, under the voltage of described primary nodal point and the control of described first clock signal, by The voltage of one DC source is supplied to described secondary nodal point；And under the control of the voltage of described primary nodal point, make described first DC source stops to provide voltage to described secondary nodal point；

Described first output module, under the control of the voltage of described secondary nodal point, by described first DC source Voltage is supplied to output signal end；

Described second output module, under the control of the voltage of described secondary nodal point, by the voltage of the second DC source It is supplied to described output signal end；

Described primary nodal point is located at the wire connecting described input module, described drive module and described reseting module On；Described secondary nodal point is located at and connects described drive module, described reseting module, described first output module and described the On the wire of two output modules；

Described first clock signal and described second clock signal phase are contrary.

In a kind of possible embodiment, in above-mentioned shift register provided in an embodiment of the present invention, described input Module specifically includes: the first transistor；Wherein,

Described the first transistor, its grid is connected with described first clock signal, its source electrode and described input signal end phase Even, its drain electrode is connected with described primary nodal point.

In a kind of possible embodiment, in above-mentioned shift register provided in an embodiment of the present invention, described driving Module specifically includes: transistor seconds and the first electric capacity；Wherein,

Described transistor seconds, its grid is connected with described primary nodal point, and its source electrode is connected with described second clock signal； Its drain electrode is connected with described secondary nodal point；

Described first capacitance connection is between the grid of described transistor seconds and the drain electrode of described transistor seconds.

In a kind of possible embodiment, in above-mentioned shift register provided in an embodiment of the present invention, described reset Module specifically includes: third transistor, the 4th transistor and the 5th transistor；Wherein,

Described third transistor, its grid is connected with described first clock signal, its source electrode and described second DC source phase Even, its drain electrode is connected with the drain electrode of described 4th transistor and the grid of described 5th transistor respectively；

Described 4th transistor, its grid is connected with described primary nodal point, and its source electrode is connected with described first clock signal；

Described 5th transistor, its source electrode is connected with described first DC source, and its drain electrode is connected with described secondary nodal point.

Further, in above-mentioned shift register provided in an embodiment of the present invention, described reseting module also includes: second Electric capacity；Wherein,

Described second capacitance connection is between the grid and the source electrode of described 5th transistor of described 5th transistor.

In a kind of possible embodiment, in above-mentioned shift register provided in an embodiment of the present invention, described second Output module specifically includes: the 6th transistor, the 7th transistor, the 8th transistor and the 3rd electric capacity；Wherein,

Described 6th transistor, its grid is connected with described secondary nodal point, and its source electrode is connected with described second DC source, its Drain electrode is connected with the drain electrode of described 7th transistor and the grid of described 8th transistor；

Described 7th transistor, its grid is connected with described first clock signal, its source electrode and described first DC source phase Even；

Described 8th transistor, its source electrode is connected with described second DC source, and its drain electrode is connected with described output signal end；

Described 3rd capacitance connection is between the grid of described 8th transistor and the drain electrode of described 8th transistor.

Or, in a kind of possible embodiment, in above-mentioned shift register provided in an embodiment of the present invention, described Second output module specifically includes: the 9th transistor and the 4th electric capacity；Wherein,

Described 9th transistor, its grid is connected with described secondary nodal point, and its source electrode is connected with described low-potential direct source, Its drain electrode is connected with described output signal end；

Described 4th capacitance connection is between the grid of described 9th transistor and the drain electrode of described 9th transistor.

In a kind of possible embodiment, in above-mentioned shift register provided in an embodiment of the present invention, described first Output module specifically includes: the tenth transistor, the 11st transistor and the tenth two-transistor；Wherein,

Described tenth transistor, its grid is connected with described secondary nodal point, and its source electrode is connected with described high potential DC source, Its drain electrode is connected with the drain electrode of described 11st transistor and the grid of described tenth two-transistor respectively；

Described 11st transistor, its grid is connected with described first clock signal, its source electrode and described low-potential direct Source is connected；

Described tenth two-transistor, its source electrode is connected with described high potential DC source, and it drains and described output signal end It is connected.

Further, in above-mentioned shift register provided in an embodiment of the present invention, described first output module also includes: 5th electric capacity；Wherein,

Described 5th capacitance connection is between the grid and the source electrode of described tenth two-transistor of described tenth two-transistor.

Or, in a kind of possible embodiment, in above-mentioned shift register provided in an embodiment of the present invention, described First output module specifically includes: the 13rd transistor and the 6th electric capacity, wherein,

Described 13rd transistor, its grid is connected with described secondary nodal point, its source electrode and described high potential DC source It is connected, its drain electrode is connected with described output signal end；

Described 6th capacitance connection is between the grid of described 13rd transistor and the drain electrode of described 13rd transistor.

Further, in above-mentioned shift register provided in an embodiment of the present invention, the first to the tenth two-transistor is p Transistor npn npn, and described first DC source is high potential DC source, described second DC source is low-potential direct source；Or

First to the tenth two-transistor is n-type transistor, and described first DC source is low-potential direct source, and described the Two DC sources are high potential DC source.

Specifically, in above-mentioned shift register provided in an embodiment of the present invention, described 13rd transistor is N-shaped crystal Pipe, and described first DC source is high potential DC source, described second DC source is low-potential direct source；Or

Described 13rd transistor is p-type transistor, and described first DC source is low-potential direct source, and described second is straight Stream source is high potential DC source.

Correspondingly, the embodiment of the present invention additionally provides a kind of gate driver circuit, including multiple present example of series connection Any of the above-described kind of shift register providing；Wherein,

The input signal end of first order shift register connects initial signal end, in addition to first order shift register, its The input signal end of remaining shift register at different levels connects the output signal end of upper level shift register.

Correspondingly, the embodiment of the present invention additionally provides a kind of display device, including above-mentioned provided in an embodiment of the present invention A kind of gate driver circuit.

Above-mentioned shift register provided in an embodiment of the present invention, gate driver circuit and display device, comprising: input mould Block, reseting module, drive module, the first output module and the second output module.This shift register by the use of DC source as The output source of the output signal that output signal end is exported, compares clock signal as the output source of output signal, DC source The output signal that the high-frequency periodic transformation's characteristic being had by oneself by clock signal is led to not only can be avoided unstable Problem, and also the impact to output signal for the line load can be reduced, thus improving the output letter that shift register is exported Number stability and reliability.

Brief description

Fig. 1 is one of structural representation of shift register provided in an embodiment of the present invention；

Fig. 2 a and Fig. 2 b is respectively the circuit timing diagram of shift register provided in an embodiment of the present invention；

Fig. 3 a and Fig. 3 b is respectively the shift register that all transistors provided in an embodiment of the present invention are p-type transistor Concrete structure schematic diagram；

Fig. 4 a and Fig. 4 b is respectively the shift register that all transistors provided in an embodiment of the present invention are n-type transistor Concrete structure schematic diagram；

Fig. 5 a and Fig. 5 b is respectively and provided in an embodiment of the present invention includes p-type transistor and the displacement of n-type transistor is posted The concrete structure schematic diagram of storage；

Fig. 6 is the structural representation of gate driver circuit provided in an embodiment of the present invention.

Specific embodiment

Below in conjunction with the accompanying drawings, to shift register provided in an embodiment of the present invention, gate driver circuit and display device Specific embodiment is described in detail.

A kind of shift register provided in an embodiment of the present invention, as shown in Figure 1, comprising: input module 1, reseting module 2, Drive module 3, the first output module 4 and the second output module 5；Wherein,

Input module 1, for, under the control of the first clock signal ck, the input signal of input signal end input being carried Supply primary nodal point a；

Drive module 3, for, under the control of the voltage of primary nodal point a, second clock signal cb being supplied to second section Point b；And between input signal end input and primary nodal point a during no signal transmission, draw high or drag down the electricity of primary nodal point a Pressure；

Reseting module 2, under the voltage of primary nodal point a and the control of the first clock signal ck, by the first unidirectional current The voltage of source v1 is supplied to secondary nodal point b；And under the control of the voltage of primary nodal point a, so that the first DC source v1 is stopped There is provided voltage to secondary nodal point b；

First output module 4, for, under the control of the voltage of secondary nodal point b, the voltage of the first DC source v1 being provided To output signal end output；

Second output module 5, for, under the control of the voltage of secondary nodal point b, the voltage of the second DC source v2 being provided To output signal end output；

Primary nodal point a is located on the wire connecting input module 1 and drive module 3 and reseting module 2；Secondary nodal point b position On the wire connecting drive module 3 and reseting module 2, the first output module 4 and the second output module 5；

First clock signal ck and second clock signal cb opposite in phase.

Above-mentioned shift register provided in an embodiment of the present invention, above-mentioned shift register provided in an embodiment of the present invention, bag Include: input module, reseting module, drive module, the first output module and the second output module.This shift register utilizes direct current The output source of the output signal that power supply is exported as output signal end, compares clock signal as the output source of output signal, DC source not only can avoid the output signal that the high-frequency periodic transformation's characteristic being had by oneself by clock signal is led to Unstable problem, and also the impact to output signal for the line load can be reduced, thus improve shift register being exported The stability of output signal and reliability.

It should be noted that in above-mentioned shift register provided in an embodiment of the present invention, when the first DC source is high electricity During the DC source of position, the second DC source is then low-potential direct source；When the first DC source is low-potential direct source, the second DC source It is then high potential DC source.

With reference to circuit timing diagram, letter is carried out to the operation principle of above-mentioned shift register provided in an embodiment of the present invention Introduce.

Specifically, the work of above-mentioned shift register provided in an embodiment of the present invention can have three phases, such as Fig. 2 a and Shown in Fig. 2 b, it is respectively as follows: sample phase t1, output stage t2 and reseting stage t3；

In sample phase t1, input signal end input inputs input signal, and input module is in the control of the first clock signal ck Under system, the input signal of input signal end input is supplied to primary nodal point a；Reseting module is in the voltage and of primary nodal point a Under the control of one clock signal ck, the voltage of the first DC source v1 is supplied to secondary nodal point b；Drive module is in primary nodal point Under the control of the voltage of a, second clock signal cb is supplied to secondary nodal point b；Now, the first output module is in secondary nodal point b The control of voltage under, the voltage of the first DC source v1 is supplied to output signal end output；

Output stage t2, between input signal end input and primary nodal point a between no signal transmission；If primary nodal point a Voltage be low-potential voltage in a upper time period, drive module then drags down the voltage of primary nodal point a；If the electricity of primary nodal point a It is pressed in a time period for high-potential voltage, drive module then draws high the voltage of primary nodal point a；And the voltage in primary nodal point a Under control with second clock signal cb, second clock signal cb is supplied to secondary nodal point b；Reseting module is in primary nodal point a The control of voltage under, make the first DC source v1 stop to secondary nodal point b provide voltage；Now, the second output module is Under the control of voltage of two node b, the voltage of the second DC source v2 is supplied to output signal end output；

In reseting stage t3, input module, under the control of the first clock signal ck, makes input signal end input and first Node a is in the conduction state；Reseting module is under the voltage of primary nodal point a and the control of the first clock signal ck, straight by first The voltage of stream power supply v1 is supplied to secondary nodal point b；Now, under the control of the voltage in secondary nodal point b for first output module, by The voltage of one DC source v1 is supplied to output signal end output.

With reference to specific embodiment, the present invention is described in detail.It should be noted that in the present embodiment be in order to Preferably explain the present invention, but do not limit the present invention.

It is preferred that in the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, such as Fig. 3 a to Fig. 5 b Shown, input module specifically includes: the first transistor t1；Wherein,

The first transistor t1, its grid is connected with the first clock signal ck, and its source electrode is connected with input signal end input, Its drain electrode is connected with primary nodal point a.

Further, in the specific implementation, as shown in Figure 3 a and Figure 3 b shows, the first transistor t1 can be p-type transistor, this When, the first transistor t1 conducting when the first clock signal ck is electronegative potential, when the first clock signal ck is high potential first Transistor t1 ends.Or, as shown in figures 4 a and 4b, the first transistor t1 can also be n-type transistor, and here does not limit Fixed.

The above is only the concrete structure illustrating input module in shift register, in the specific implementation, input module Concrete structure be not limited to said structure provided in an embodiment of the present invention, can also be skilled person will appreciate that other knot Structure, here does not limit.

It is preferred that in the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, such as Fig. 3 a to Fig. 5 b Shown, drive module specifically includes: transistor seconds t2 and the first electric capacity c1；Wherein,

Transistor seconds t2, its grid is connected with primary nodal point a, and its source electrode is connected with second clock signal cb；Its drain electrode It is connected with secondary nodal point b；

First electric capacity c1 is connected between the grid of transistor seconds t2 and the drain electrode of transistor seconds t2.Setting first electricity Hold c1, by the boot strap of the first electric capacity c1, drag down or in t2 as shown in Figure 2 b within the t2 time period as shown in Figure 2 a The voltage drawing high primary nodal point a in time period is to keep transistor seconds t2 in the conduction state.

Further, in the specific implementation, as shown in Figure 3 a and Figure 3 b shows, transistor seconds t2 can be p-type transistor, this When, the transistor seconds t2 conducting when the voltage of primary nodal point a is electronegative potential, when the voltage of primary nodal point a is high potential the Two-transistor t2 ends.Or, as shown in figures 4 a and 4b, transistor seconds t2 can also be n-type transistor, and here does not limit Fixed.

The above is only the concrete structure illustrating drive module in shift register, in the specific implementation, drive module Concrete structure be not limited to said structure provided in an embodiment of the present invention, can also be skilled person will appreciate that other knot Structure, here does not limit.

It is preferred that in above-mentioned shift register provided in an embodiment of the present invention, as shown in Fig. 3 a and Fig. 4 a, reseting module 2 specifically may include that third transistor t3, the 4th transistor t4 and the 5th transistor t5；Wherein,

Third transistor t3, its grid is connected with the first clock signal ck, and its source electrode is connected with the second DC source v2, its leakage Pole is connected with the drain electrode of the 4th transistor t4 and the grid of the 5th transistor t5 respectively；

4th transistor t4, its grid is connected with primary nodal point a, and its source electrode is connected with the first clock signal ck；

5th transistor t5, its source electrode is connected with the first DC source v1, and its drain electrode is connected with secondary nodal point b.

Further, in the specific implementation, as shown in Figure 3 a and Figure 3 b shows, third transistor t3, the 4th transistor t4 and Five transistor t5 can be all p-type transistor, now, the third transistor t3 conducting when the first clock signal ck is electronegative potential, The third transistor t3 cut-off when the first clock signal ck is high potential；When the voltage of primary nodal point a is electronegative potential, the 4th is brilliant Body pipe t4 turns on, the 4th transistor t4 cut-off when the voltage of primary nodal point a is high potential；Grid as the 5th transistor t5 Voltage is the 5th transistor t5 conducting during electronegative potential, the 5th transistor when the voltage of the grid of the 5th transistor t5 is high potential T5 ends.Or, as shown in figures 4 a and 4b, third transistor t3, the 4th transistor t4 and the 5th transistor t5 can be all n Transistor npn npn, is not limited thereto.

Further, in above-mentioned shift register provided in an embodiment of the present invention, in order to preferably maintain the 5th crystal The grid voltage of pipe t5, as is shown in figures 3b and 4b, reseting module can also include: the second electric capacity c2；Wherein,

Second electric capacity c2 is connected between grid and the source electrode of the 5th transistor t5 of the 5th transistor t5.

The above is only the concrete structure illustrating reseting module in shift register, in the specific implementation, reseting module Concrete structure be not limited to said structure provided in an embodiment of the present invention, can also be skilled person will appreciate that other knot Structure, here does not limit.

It is preferred that in above-mentioned shift register provided in an embodiment of the present invention, as shown in Fig. 3 a to Fig. 4 b, the second output Module specifically may include that the 6th transistor t6, the 7th transistor t7 and the 8th transistor t8 and the 3rd electric capacity c3；Wherein,

6th transistor t6, its grid is connected with secondary nodal point b, and its source electrode is connected with the second DC source v2, its drain electrode with The drain electrode of the 7th transistor t7 is connected with the grid of the 8th transistor t8；

7th transistor t7, its grid is connected with the first clock signal ck, and its source electrode is connected with the first DC source v1；

8th transistor t8, its source electrode is connected with the second DC source v2, and its drain electrode is connected with output signal end output；

3rd electric capacity c3 is connected between grid and the drain electrode of the 8th transistor t8 of the 8th transistor t8.Specifically, exist In second output module, setting the 3rd electric capacity c3 is for the boot strap by the 3rd electric capacity c3, in t2 as shown in Figure 2 a Between drag down in section or draw high the grid voltage of the 8th transistor t8 to keep the 8th crystal within the t2 time period as shown in Figure 2 b Pipe t8 is in the conduction state.

Further, in the specific implementation, as shown in Figure 3 a and Figure 3 b shows, the 6th transistor t6, the 7th transistor t7 and Eight transistor t8 can be all p-type transistor, now, the 6th transistor t6 conducting when the voltage of secondary nodal point b is electronegative potential, The 6th transistor t6 cut-off when the voltage of secondary nodal point b is high potential；When the first clock signal ck is electronegative potential, the 7th is brilliant Body pipe t7 turns on, the 7th transistor t7 cut-off when the first clock signal ck is high potential；Grid as the 8th transistor t8 Voltage is the 8th transistor t8 conducting during electronegative potential, the 8th transistor when the voltage of the grid of the 8th transistor t8 is high potential T8 ends.Or, as shown in figures 4 a and 4b, the 6th transistor t6, the 7th transistor t7 and the 8th transistor t8 all can also For n-type transistor, it is not limited thereto.

Or, in order to simplify circuit structure, in above-mentioned shift register provided in an embodiment of the present invention, such as Fig. 5 a and figure Shown in 5b, the second output module specifically may include that the 9th transistor t9 and the 4th electric capacity c4；Wherein,

9th transistor t9, its grid is connected with secondary nodal point b, and its source electrode is connected with the second DC source v2, its drain electrode with Output signal end output is connected；

4th electric capacity c4 is connected between grid and the drain electrode of the 9th transistor t9 of the 9th transistor t9.Specifically, exist In second output module, setting the 4th electric capacity c4 is to ensure that the stability of the grid voltage of the 9th transistor t9.

Further, in the specific implementation, as shown in Figure 5 a, the 9th transistor t9 can be p-type transistor.Work as second section The voltage of point b is the 9th transistor t9 conducting during electronegative potential, now, the 9th crystal when the voltage of secondary nodal point b is high potential Pipe t9 ends.Or, as shown in Figure 5 b, the 9th transistor t9 can also be n-type transistor, is not limited thereto.

The above is only the concrete structure illustrating the second output module in shift register, in the specific implementation, second The concrete structure of output module is not limited to said structure provided in an embodiment of the present invention, can also be skilled person will appreciate that Other structures, here do not limit.

Specifically, in the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, such as Fig. 3 a to Fig. 4 b Shown, the first output module specifically may include that the tenth transistor t10, the 11st transistor t11 and the 12nd crystal t12；Its In,

Tenth transistor t10, its grid is connected with secondary nodal point b, and its source electrode is connected with the first DC source v1, its drain electrode point It is not connected with the drain electrode of the 11st transistor t11 and the grid of the tenth two-transistor t12；

11st transistor t11, its grid is connected with the first clock signal ck, and its source electrode is connected with the second DC source v2；

Tenth two-transistor t12, its source electrode is connected with the first DC source v1, and it drains and output signal end output phase Even.

Further, in the specific implementation, as shown in Figure 3 a and Figure 3 b shows, the tenth transistor t10, the 11st transistor t11 Can be all p-type transistor with the 12nd crystal t12, now, the tenth transistor when the voltage of secondary nodal point b is electronegative potential T10 turns on, the tenth transistor t10 cut-off when the voltage of secondary nodal point b is high potential；When the first clock signal ck is electronegative potential When the 11st transistor t11 conducting, when the first clock signal ck be high potential when the 11st transistor t11 cut-off；When the 12nd The voltage of the grid of crystal t12 is the 12nd crystal t12 conducting during electronegative potential, when the voltage of the grid of the 12nd crystal t12 is 12nd crystal t12 cut-off during high potential.Or, as shown in figures 4 a and 4b, the tenth transistor t10, the 11st transistor t11 Can also be all n-type transistor with the 12nd crystal t12, be not limited thereto.

It is preferred that in above-mentioned shift register provided in an embodiment of the present invention, in order to preferably maintain the 12nd crystal The grid voltage of pipe t12, as is shown in figures 3b and 4b, the first output module can also include: the 5th electric capacity c5；Wherein,

5th electric capacity c5 is connected between grid and the source electrode of the tenth two-transistor t12 of the tenth two-transistor t12.

Or, in order to simplify circuit structure, in above-mentioned shift register provided in an embodiment of the present invention, such as Fig. 5 a and figure Shown in 5b, the first output module specifically may include that the 13rd transistor t13 and the 6th electric capacity c6, wherein,

13rd transistor t13, its grid is connected with secondary nodal point b, and its source electrode is connected with the first DC source v1, its leakage Pole is connected with output signal end output；

6th electric capacity c6 is connected between grid and the drain electrode of the 13rd transistor t13 of the 13rd transistor t13.

Specifically, in the first output module, setting the 6th electric capacity c6 is to ensure that the grid of the 13rd transistor t13 The stability of voltage.

Further, in the specific implementation, as shown in Figure 5 a, the 13rd transistor t13 can be n-type transistor, now, The 13rd transistor t13 conducting when the voltage of secondary nodal point b is high potential, when the voltage of secondary nodal point b is electronegative potential the 13 transistor t13 cut-offs.Or, as shown in Figure 5 b, the 13rd transistor t13 can also be p-type transistor, and here does not limit Fixed.

The above is only the concrete structure illustrating the first output module in shift register, in the specific implementation, first The concrete structure of output module is not limited to said structure provided in an embodiment of the present invention, can also be skilled person will appreciate that Other structures, here do not limit.

It is preferred that in above-mentioned shift register provided in an embodiment of the present invention, transistor generally individually adopts phase same material Transistor, in the specific implementation, in order to simplify processing technology, the above-mentioned first to the tenth two-transistor is all using p-type transistor Or n-type transistor.And when the first to the tenth two-transistor is p-type transistor, the first DC source is high potential DC source, the Two DC sources are low-potential direct source；Or when the first to the tenth two-transistor is n-type transistor, the first DC source is low electricity Position DC source, the second DC source is high potential DC source.

The shift register of the structure being the 13rd transistor and the 6th electric capacity for the first output module, as Fig. 5 a institute Show, when the 13rd transistor is n-type transistor, the first DC source is high potential DC source, and the second DC source is that electronegative potential is straight Stream source；Or as shown in Figure 5 b, when the 13rd transistor is p-type transistor, the first DC source is low-potential direct source, and second is straight Stream source is high potential DC source.

It should be noted that the transistor mentioned in the above embodiment of the present invention can be thin film transistor (TFT) (tft, thin Film transistor) or metal oxide semiconductor field effect tube (mos, metal oxide Scmiconductor), here does not limit.In being embodied as, the source electrode of these transistors and drain electrode are according to transistor types And the difference of input signal, its function can exchange, and here does not do concrete differentiation.

To embodiment of the present invention shift register as a example input and output sequential chart shown in separately below by Fig. 2 a and Fig. 2 b Work process be described.High potential signal is represented with 1,0 expression low-potential signal in described below.

Example one:

As a example the structure of the shift register shown in by Fig. 3 b, its work process is described, wherein shown in Fig. 3 b In shift register, all transistors are p-type transistor, and each p-type transistor is ended under high potential effect, makees in electronegative potential Use lower conducting；First DC source is high potential DC source, and the second DC source is low-potential direct source；Corresponding input and output sequential Figure is as shown in Figure 2 a.Specifically, t1, the t2 and t3 three phases in input and output sequential chart as shown in Figure 2 a are chosen.

In t1 stage, input=0, ck=0, cb=1.Due to ck=0, therefore the first transistor t1, third transistor T3, the 7th transistor t7 and the 11st transistor t11 are both turned on；Because the first transistor t1 turns on, input=0, therefore first The current potential of node a is electronegative potential；Because the current potential of primary nodal point a is electronegative potential, the therefore the 4th transistor t4 and transistor seconds T2 turns on, and the second electric capacity c2 is charged；Due to ck=0, the current potential of the therefore the 5th transistor t5 grid is electronegative potential, the 5th Transistor t5 turns on and the voltage of the first DC source is supplied to secondary nodal point b；Because transistor seconds t2 turns on, cb=1, because The second clock signal cb of high potential is supplied to secondary nodal point b, the therefore electricity of secondary nodal point b by the transistor seconds t2 of this conducting Position is high potential, and the first electric capacity c1 is charged；Because the current potential of secondary nodal point b is high potential, the therefore the 6th transistor t6 End with the tenth transistor t10；The current potential of the grid of the 8th transistor t8 is high potential, the 8th transistor cutoff；12nd is brilliant The current potential of the grid of body pipe t12 is electronegative potential, and the 5th electric capacity c5 is charged, the tenth two-transistor t12 conducting by first The voltage of DC source v1 is supplied to output signal end output, and therefore output signal end output exports high potential output signal.

In t2 stage, input=1, ck=1, cb=0.Due to ck=1, therefore the first transistor t1, third transistor T3, the 7th transistor t7 and the 11st transistor t11 are turned off；Due to the first transistor t1 cut-off, the current potential of primary nodal point a is Electronegative potential, the therefore the 4th transistor t4 and transistor seconds t2 conducting；Due to ck=1, the electricity of the therefore the 5th transistor t5 grid Position is high potential, the 5th transistor t5 cut-off, meanwhile, in this stage, the second electric capacity c2 carry out discharging its two ends current potential all For high potential, with the more preferable current potential maintaining the 5th transistor t5 grid as high potential；Due to transistor seconds t2 conducting, cb= 0, the second clock signal cb of electronegative potential is supplied to secondary nodal point b, therefore secondary nodal point b by the therefore transistor seconds t2 of conducting Current potential be electronegative potential；Current potential due to secondary nodal point b is electronegative potential, according to the boot strap of the first electric capacity c1, in order to maintain The voltage difference at the first electric capacity c1 two ends, the therefore current potential of primary nodal point a is dragged down further, to ensure the 4th crystalline substance in this stage Body pipe t4 and transistor seconds t2 conducting；Because the current potential of secondary nodal point b is electronegative potential, the therefore the 6th transistor t6 and the tenth is brilliant Body pipe t10 turns on；The current potential of the grid of the tenth two-transistor t12 is high potential, the tenth two-transistor t12 cut-off, meanwhile, here In stage, the 5th electric capacity c5 carries out discharging makes the current potential at its two ends be all high potential, maintains the tenth two-transistor t12 with more preferable The current potential of grid is high potential；The current potential of the grid of the 8th transistor t8 is electronegative potential, the 8th transistor t8 conducting by second The voltage of DC source v2 is supplied to output signal end output, and therefore output signal end output exports electronegative potential output signal； Simultaneously because the boot strap of the 3rd electric capacity c3, in order to maintain the voltage difference at the 3rd electric capacity c3 two ends, the grid of the 8th transistor t8 The current potential of pole is dragged down further to ensure that the 8th transistor t8 turns in this stage.

In t3 stage, input=1, ck=0, cb=1.Due to ck=0, therefore the first transistor t1, third transistor T3, the 7th transistor t7 and the 11st transistor t11 are both turned on；Because the first transistor t1 turns on, input=1, therefore first The current potential of node a is high potential；Because the current potential of primary nodal point a is high potential, the therefore the 4th transistor t4 and transistor seconds T2 ends；Due to ck=0, the current potential of the therefore the 5th transistor t5 grid is electronegative potential, and the second electric capacity c2 is charged, and the 5th is brilliant The voltage of the first DC source v1 is simultaneously supplied to secondary nodal point b by body pipe t5 conducting, and the therefore current potential of secondary nodal point b is high potential, In this stage, the first electric capacity c1 carry out discharging current potential at its two ends is all high potential, maintains transistor seconds t2 grid with more preferable The current potential of pole is high potential；Because the current potential of secondary nodal point b is high potential, the therefore the 6th transistor t6 and the tenth transistor t10 Cut-off；The current potential of the grid of the 8th transistor t8 is high potential, the 8th transistor cutoff；The grid of the tenth two-transistor t12 Current potential is electronegative potential, and the 5th electric capacity c5 is charged, and the voltage of the first DC source v1 is simultaneously carried by the tenth two-transistor t12 conducting Supply output signal end output, therefore output signal end output export high potential output signal, the 3rd electric capacity in this stage C3 carry out the discharging current potential at its two ends is all high potential, with the more preferable current potential maintaining the 8th transistor t8 grid as high potential.

The output source of the output signal by being exported by the use of DC source as output signal end for the above-mentioned shift register, Compare clock signal as the output source of output signal, DC source not only can avoid the altofrequency having by oneself due to clock signal The unstable problem of the output signal that led to of periodic transformation's characteristic, and also line load can be reduced to output signal Impact, thus improving stability and the reliability of the output signal that shift register is exported.

Specifically, the shift register of structure shown in Fig. 3 a work process make with worked described in examples detailed above one Journey is compared, and in addition to having lacked the effect of the second electric capacity and the 5th electric capacity, other processes are identical, and therefore not to repeat here.

Example two:

As a example the structure of the shift register shown in by Fig. 4 b, its work process is described, wherein shown in Fig. 4 b In shift register, all transistors are n-type transistor, and each n-type transistor is ended under electronegative potential effect, makees in high potential Use lower conducting；First DC source is low-potential direct source, and the second DC source is high potential DC source；Corresponding input and output sequential Figure is as shown in Figure 2 b.Specifically, t1, the t2 and t3 three phases in input and output sequential chart as shown in Figure 2 b are chosen.

In t1 stage, input=1, ck=1, cb=0.Due to ck=1, therefore the first transistor t1, third transistor T3, the 7th transistor t7 and the 11st transistor t11 are both turned on；Because the first transistor t1 turns on, input=1, therefore first The current potential of node a is high potential；Because the current potential of primary nodal point a is high potential, the therefore the 4th transistor t4 and transistor seconds T2 turns on, and the second electric capacity c2 is charged；Due to ck=1, the current potential of the therefore the 5th transistor t5 grid is high potential, the 5th Transistor t5 turns on and the voltage of the first DC source is supplied to secondary nodal point b；Because transistor seconds t2 turns on, cb=0, because The second clock signal cb of electronegative potential is supplied to secondary nodal point b, the therefore electricity of secondary nodal point b by the transistor seconds t2 of this conducting Position is electronegative potential, and the first electric capacity c1 is charged；Because the current potential of secondary nodal point b is electronegative potential, the therefore the 6th transistor t6 End with the tenth transistor t10；The current potential of the grid of the 8th transistor t8 is electronegative potential, the 8th transistor cutoff；12nd is brilliant The current potential of the grid of body pipe t12 is high potential, and the 5th electric capacity c5 is charged, the tenth two-transistor t12 conducting by first The voltage of DC source v1 is supplied to output signal end output, and therefore output signal end output exports electronegative potential output signal.

In t2 stage, input=0, ck=0, cb=1.Due to ck=0, therefore the first transistor t1, third transistor T3, the 7th transistor t7 and the 11st transistor t11 are turned off；Due to the first transistor t1 cut-off, the current potential of primary nodal point a is High potential, the therefore the 4th transistor t4 and transistor seconds t2 conducting；Due to ck=0, the electricity of the therefore the 5th transistor t5 grid Position is electronegative potential, the 5th transistor t5 cut-off, meanwhile, in this stage, the second electric capacity c2 carry out discharging its two ends current potential all For electronegative potential, with the more preferable current potential maintaining the 5th transistor t5 grid as electronegative potential；Due to transistor seconds t2 conducting, cb= 1, the second clock signal cb of high potential is supplied to secondary nodal point b, therefore secondary nodal point b by the therefore transistor seconds t2 of conducting Current potential be high potential；Current potential due to secondary nodal point b is high potential, according to the boot strap of the first electric capacity c1, in order to maintain The voltage difference at the first electric capacity c1 two ends, the therefore current potential of primary nodal point a is further pulled up, to ensure the 4th crystalline substance in this stage Body pipe t4 and transistor seconds t2 conducting；Because the current potential of secondary nodal point b is high potential, the therefore the 6th transistor t6 and the tenth is brilliant Body pipe t10 turns on；The current potential of the grid of the tenth two-transistor t12 is electronegative potential, the tenth two-transistor t12 cut-off, meanwhile, here In stage, the 5th electric capacity c5 carries out discharging makes the current potential at its two ends be all electronegative potential, maintains the tenth two-transistor t12 with more preferable The current potential of grid is electronegative potential；The current potential of the grid of the 8th transistor t8 is high potential, the 8th transistor t8 conducting by second The voltage of DC source v2 is supplied to output signal end output, and therefore output signal end output exports high potential output signal； Simultaneously because the boot strap of the 3rd electric capacity c3, in order to maintain the voltage difference at the 3rd electric capacity c3 two ends, the grid of the 8th transistor t8 The current potential of pole is further pulled up to ensure that the 8th transistor t8 turns in this stage.

In t3 stage, input=0, ck=1, cb=0.Due to ck=1, therefore the first transistor t1 and third transistor T3 is both turned on；Due to the first transistor t1 conducting, input=0, the therefore current potential of primary nodal point a are electronegative potential；Due to first segment The current potential of point a is electronegative potential, the therefore the 4th transistor t4 and transistor seconds t2 cut-off；Due to ck=1, the therefore the 5th transistor The current potential of t5 grid is high potential, and the second electric capacity c2 is charged, and the 5th transistor t5 turns on and the voltage by the first DC source It is supplied to secondary nodal point b, the therefore current potential of secondary nodal point b is electronegative potential, and in this stage, the first electric capacity c1 carries out its two ends of discharging Current potential be all electronegative potential, with the more preferable current potential maintaining transistor seconds t2 grid as electronegative potential；Electricity due to secondary nodal point b Position is electronegative potential, the therefore the 6th transistor t6 and the tenth transistor t10 cut-off；The current potential of the grid of the 8th transistor t8 is low electricity Position, the 8th transistor cutoff；The current potential of the grid of the tenth two-transistor t12 is high potential, and the 5th electric capacity c5 is charged, the The voltage of the first DC source v1 is simultaneously supplied to output signal end output, therefore output signal end by ten two-transistor t12 conductings Output exports electronegative potential output signal, and in this stage, the 3rd electric capacity c3 carry out the discharging current potential at its two ends is all electronegative potential, with The current potential preferably maintaining the 8th transistor t8 grid is electronegative potential.

Specifically, the shift register of structure shown in Fig. 4 a work process make with worked described in examples detailed above two Journey is compared, and in addition to having lacked the effect of the second electric capacity and the 5th electric capacity, other processes are identical, and therefore not to repeat here.

Example three

As a example the structure of the shift register shown in by Fig. 5 a, its work process is described, wherein shown in Fig. 5 a In shift register, except the 13rd transistor is n-type transistor, other transistors are p-type transistor.N-type transistor exists Electronegative potential effect is lower to be ended, and turns under high potential effect；Each p-type transistor is ended under high potential effect, makees in electronegative potential Use lower conducting；First DC source is high potential DC source, and the second DC source is low-potential direct source；Corresponding input and output sequential Figure is as shown in Figure 2 a.Specifically, t1, the t2 and t3 three phases in input and output sequential chart as shown in Figure 2 a are chosen.

In t1 stage, input=0, ck=0, cb=1.Due to ck=0, therefore the first transistor t1 and third transistor T3 is both turned on；Due to the first transistor t1 conducting, input=0, the therefore current potential of primary nodal point a are electronegative potential；Due to first segment The current potential of point a is electronegative potential, the therefore the 4th transistor t4 and transistor seconds t2 conducting, and the second electric capacity c2 is charged；By In ck=0, the current potential of the therefore the 5th transistor t5 grid is electronegative potential, and the 5th transistor t5 turns on and the electricity by the first DC source Pressure is supplied to secondary nodal point b；Due to transistor seconds t2 conducting, the transistor seconds t2 of cb=1, therefore conducting is by high potential Second clock signal cb is supplied to secondary nodal point b, and the therefore current potential of secondary nodal point b is high potential, and the first electric capacity c1 is filled Electricity；Because the current potential of secondary nodal point b is high potential, the therefore the 9th transistor t9 cut-off, the 6th electric capacity c6 is connected with secondary nodal point b One end current potential be high potential, this moment the 6th electric capacity c6 the other end current potential be electronegative potential, the 13rd transistor t13 The voltage of the first DC source v1 is simultaneously supplied to output signal end output, the high electricity of therefore output signal end output output by conducting Position output signal；And, in this stage, because the 13rd transistor t13 turns on, the electricity of the other end of the therefore the 6th electric capacity c6 Position gradually rises, and because electric capacity has the effect that can maintain its both end voltage difference, the therefore the 6th electric capacity c6 and secondary nodal point b is even The current potential of the one end connecing gradually is drawn high with the gradually rising of current potential of the other end, so that the 13rd transistor t13 Grid voltage is further pulled up, and then ensures the stability of the conducting of the 13rd transistor t13 in this stage.

In t2 stage, input=1, ck=1, cb=0.Due to ck=1, therefore the first transistor t1 and third transistor T3 is turned off；Due to the first transistor t1 cut-off, the current potential of primary nodal point a is electronegative potential, the therefore the 4th transistor t4 and second Transistor t2 turns on；Due to ck=1, the current potential of the therefore the 5th transistor t5 grid is high potential, the 5th transistor t5 cut-off, with When, in this stage, the second electric capacity c2 carry out discharging current potential at its two ends is all high potential, maintains the 5th transistor with more preferable The current potential of t5 grid is high potential；Due to transistor seconds t2 conducting, the transistor seconds t2 of cb=0, therefore conducting is by low electricity The second clock signal cb of position is supplied to secondary nodal point b, and the therefore current potential of secondary nodal point b is electronegative potential；Due to secondary nodal point b's Current potential is electronegative potential, according to the boot strap of the first electric capacity c1, in order to maintain the voltage difference at the first electric capacity c1 two ends, to ensure 4th transistor t4 and transistor seconds t2 conducting in this stage；Because the current potential of secondary nodal point b is electronegative potential, the therefore the 13rd Transistor t13 ends, and the current potential of one end that the 4th electric capacity c4 is connected with secondary nodal point b is electronegative potential, in this moment the 4th electric capacity The current potential of the other end of c4 is still the current potential of output signal end output during t1 stage is high potential, and the 9th transistor t9 turns on simultaneously The voltage of the second DC source v2 is supplied to output signal end output, therefore output signal end output output electronegative potential output Signal；And, in this stage, because the 9th transistor t9 turns on, the current potential of the therefore the 4th electric capacity c4 other end is gradually lowered, Because electric capacity has the effect that can maintain its both end voltage difference, one end that the therefore the 4th electric capacity c4 is connected with secondary nodal point b Current potential is gradually dragged down with being gradually lowered of current potential of the other end, so that the grid voltage of the 9th transistor t9 is further Drag down, and then ensure the stability of the 9th transistor t9 conducting in this stage.

In t3 stage, input=1, ck=0, cb=1.Due to ck=0, therefore the first transistor t1 and third transistor T3 is both turned on；Due to the first transistor t1 conducting, input=1, the therefore current potential of primary nodal point a are high potential；Due to first segment The current potential of point a is high potential, the therefore the 4th transistor t4 and transistor seconds t2 cut-off；Due to ck=0, the therefore the 5th transistor The current potential of t5 grid is electronegative potential, and the second electric capacity c2 is charged, and the 5th transistor t5 turns on and the electricity by the first DC source v1 Pressure is supplied to secondary nodal point b, and therefore the current potential of secondary nodal point b is high potential, in this stage, the first electric capacity c1 carry out discharging its two The current potential at end is all high potential, with the more preferable current potential maintaining transistor seconds t2 grid as high potential；Due to secondary nodal point b's Current potential is high potential, the therefore the 9th transistor t9 cut-off, and the current potential of one end that the 6th electric capacity c6 is connected with secondary nodal point b is high electricity Position, when the current potential of the other end of this moment the 6th electric capacity c6 is still t2 stage, the current potential of output signal end output is low electricity Position, the voltage of the first DC source v1 is simultaneously supplied to output signal end output by the 13rd transistor t13 conducting, therefore output letter Number end output output high potential output signal；And, in this stage, because the 13rd transistor t13 turns on, the therefore the 6th The current potential of the other end of electric capacity c6 gradually rises, because electric capacity has an effect that can maintain its both end voltage difference, the therefore the 6th The current potential of one end that electric capacity c6 is connected with secondary nodal point b is gradually drawn high with the gradually rising of current potential of the other end, thus So that the grid voltage of the 13rd transistor t13 is further pulled up, and then ensure the conducting of the 13rd transistor t13 in this stage Stability.

Example four

As a example the structure of the shift register shown in by Fig. 5 b, its work process is described, wherein shown in Fig. 5 b In shift register, except the 13rd transistor is p-type transistor, other transistors are n-type transistor.N-type transistor exists Electronegative potential effect is lower to be ended, and turns under high potential effect；Each p-type transistor is ended under high potential effect, makees in electronegative potential Use lower conducting；First DC source is low-potential direct source, and the second DC source is high potential DC source；Corresponding input and output sequential Figure is as shown in Figure 2 b.Specifically, t1, the t2 and t3 three phases in input and output sequential chart as shown in Figure 2 b are chosen.

In t1 stage, input=1, ck=1, cb=0.Due to ck=1, therefore the first transistor t1 and third transistor T3 is both turned on；Due to the first transistor t1 conducting, input=1, the therefore current potential of primary nodal point a are high potential；Due to first segment The current potential of point a is high potential, the therefore the 4th transistor t4 and transistor seconds t2 conducting, and the second electric capacity c2 is charged；By In ck=1, the current potential of the therefore the 5th transistor t5 grid is high potential, and the 5th transistor t5 turns on and the electricity by the first DC source Pressure is supplied to secondary nodal point b；Due to transistor seconds t2 conducting, the transistor seconds t2 of cb=0, therefore conducting is by electronegative potential Second clock signal cb is supplied to secondary nodal point b, and the therefore current potential of secondary nodal point b is electronegative potential, and the first electric capacity c1 is filled Electricity；Because the current potential of secondary nodal point b is electronegative potential, the therefore the 9th transistor t9 cut-off, the 6th electric capacity c6 is connected with secondary nodal point b One end current potential be electronegative potential, this moment the 6th electric capacity c6 the other end current potential be high potential, the 13rd transistor t13 The voltage of the first DC source v1 is simultaneously supplied to output signal end output by conducting, and therefore output signal end output exports low electricity Position output signal；And, in this stage, because the 13rd transistor t13 turns on, the electricity of the other end of the therefore the 6th electric capacity c6 Position is gradually lowered, and because electric capacity has the effect that can maintain its both end voltage difference, the therefore the 6th electric capacity c6 and secondary nodal point b is even The current potential of the one end connecing gradually is dragged down with being gradually lowered of current potential of the other end, so that the 13rd transistor t13 Grid voltage drags down further, and then ensures the stability of the conducting of the 13rd transistor t13 in this stage.

In t2 stage, input=0, ck=0, cb=1.Due to ck=0, therefore the first transistor t1 and third transistor T3 is turned off；Due to the first transistor t1 cut-off, the current potential of primary nodal point a is high potential, the therefore the 4th transistor t4 and second Transistor t2 turns on；Due to ck=0, the current potential of the therefore the 5th transistor t5 grid is electronegative potential, the 5th transistor t5 cut-off, with When, in this stage, the second electric capacity c2 carry out discharging current potential at its two ends is all electronegative potential, maintains the 5th transistor with more preferable The current potential of t5 grid is electronegative potential；Due to transistor seconds t2 conducting, the transistor seconds t2 of cb=1, therefore conducting will be high electric The second clock signal cb of position is supplied to secondary nodal point b, and the therefore current potential of secondary nodal point b is high potential；Due to secondary nodal point b's Current potential is high potential, according to the boot strap of the first electric capacity c1, in order to maintain the voltage difference at the first electric capacity c1 two ends, therefore first The current potential of node a is further pulled up, to ensure the 4th transistor t4 and transistor seconds t2 conducting in this stage；Due to The current potential of one node a is high potential, the therefore the 4th transistor t4 and transistor seconds t2 conducting；Due to ck=0, the therefore the 5th is brilliant The current potential of body pipe t5 grid is electronegative potential, the 5th transistor t5 cut-off；Due to transistor seconds t2 conducting, cb=1, therefore turn on Transistor seconds t2 the second clock signal cb of high potential is supplied to secondary nodal point b, therefore the current potential of secondary nodal point b is height Current potential；Because the current potential of secondary nodal point b is high potential, the therefore the 13rd transistor t13 cut-off, the 4th electric capacity c4 and secondary nodal point The current potential of one end that b connects is high potential, the output letter when the current potential of the other end of this moment the 4th electric capacity c4 is still t1 stage The current potential of number end output is electronegative potential, and the voltage of the second DC source v2 is simultaneously supplied to output signal by the 9th transistor t9 conducting End output, therefore output signal end output export high potential output signal；And, in this stage, due to the 9th crystal Pipe t9 turns on, and the current potential of the therefore the 4th electric capacity c4 other end gradually rises, and its both end voltage can be maintained poor because electric capacity has Effect, the current potential of one end that the therefore the 4th electric capacity c4 is connected with secondary nodal point b with the other end gradually rising of current potential and Gradually drawn high, so that the grid voltage of the 9th transistor t9 is further pulled up, and then ensured the 9th transistor in this stage The stability of t9 conducting.

In t3 stage, input=0, ck=1, cb=0.Due to ck=1, therefore the first transistor t1 and third transistor T3 is both turned on；Due to the first transistor t1 conducting, input=0, the therefore current potential of primary nodal point a are electronegative potential；Due to first segment The current potential of point a is electronegative potential, the therefore the 4th transistor t4 and transistor seconds t2 cut-off；Due to ck=1, the therefore the 5th transistor The current potential of t5 grid is high potential, and the second electric capacity c2 is charged, and the 5th transistor t5 turns on and the voltage by the first DC source It is supplied to secondary nodal point b, the therefore current potential of secondary nodal point b is electronegative potential, and in this stage, the first electric capacity c1 carries out its two ends of discharging Current potential be all electronegative potential, with the more preferable current potential maintaining transistor seconds t2 grid as electronegative potential；Electricity due to secondary nodal point b Position is electronegative potential, the therefore the 9th transistor t9 cut-off, and the current potential of one end that the 6th electric capacity c6 is connected with secondary nodal point b is low electricity Position, when the current potential of the other end of this moment the 6th electric capacity c6 is still t2 stage, the current potential of output signal end output is high electric Position, the voltage of the first DC source v1 is simultaneously supplied to output signal end output by the 13rd transistor t13 conducting, therefore output letter Number end output output electronegative potential output signal；And, in this stage, because the 13rd transistor t13 turns on, the therefore the 6th The current potential of the other end of electric capacity c6 is gradually lowered, because electric capacity has an effect that can maintain its both end voltage difference, the therefore the 6th The current potential of one end that electric capacity c6 is connected with secondary nodal point b is gradually dragged down with being gradually lowered of current potential of the other end, thus So that the grid voltage of the 13rd transistor t13 is dragged down further, and then ensure the conducting of the 13rd transistor t13 in this stage Stability.

Based on same inventive concept, the embodiment of the present invention additionally provides a kind of gate driver circuit, as shown in fig. 6, including Series connection multiple shift registers: sr (1), sr (2) ... sr (n) ... sr (n-1), sr (n) (common n shift register, 1≤n≤ N), the input signal end input of first order shift register sr (1) connects initial signal end stv, except first order shift register Outside sr (1), the input signal end input of remaining shift register sr (n) at different levels connects upper level shift register sr (n-1) Output signal end output_n-1.Gate driver circuit sequentially exports the output signal end of shift registers sr (n) at different levels The output signal of output_n output.

Further, in above-mentioned gate driver circuit provided in an embodiment of the present invention, the first clock signal ck, second when Clock signal cb, low-potential direct source vl and high potential DC source vh all input in shift registers at different levels.

Specifically, post by above-mentioned displacement with the present invention for the concrete structure of each shift register in above-mentioned gate driver circuit Storage all same in function and structure, repeats no more in place of repetition.

Based on same inventive concept, the embodiment of the present invention additionally provides a kind of display device, including above-mentioned raster data model Circuit, provides scanning signal by this gate driver circuit for each grid line on array base palte in display device, it is embodied as Can be found in the description of above-mentioned gate driver circuit, something in common repeats no more.

A kind of shift register provided in an embodiment of the present invention, gate driver circuit and display device, the embodiment of the present invention The above-mentioned shift register providing, comprising: input module, reseting module, drive module, the first output module and the second output mould Block.The output source of the output signal that this shift register is exported by the use of DC source as output signal end, compares clock letter Number as output signal output source, DC source not only can avoid the high-frequency periodicity having by oneself due to clock signal to become Change the unstable problem of the output signal that characteristic led to, and also the impact to output signal for the line load can be reduced, from And improve stability and the reliability of the output signal that shift register is exported.

Obviously, those skilled in the art can carry out the various changes and modification essence without deviating from the present invention to the present invention God and scope.So, if these modifications of the present invention and modification belong to the scope of the claims in the present invention and its equivalent technologies Within, then the present invention is also intended to comprise these changes and modification.

Claims

1. a kind of shift register is it is characterised in that include: input module, reseting module, drive module, the first output module With the second output module；Wherein,

Described input module, for, under the control of the first clock signal, the input signal at input signal end being supplied to first Node；

Described drive module, for, under the control of the voltage of described primary nodal point, second clock signal being supplied to second section Point；And between described input signal end and described primary nodal point during no signal transmission, drag down or draw high described primary nodal point Voltage；

Described reseting module is under the voltage of described primary nodal point and the control of described first clock signal, straight by first The voltage in stream source is supplied to described secondary nodal point；And under the control of the voltage of described primary nodal point, make described first direct current Source stops to provide voltage to described secondary nodal point；

Described first output module, under the control of the voltage of described secondary nodal point, by the voltage of described first DC source It is supplied to output signal end；

Described second output module, for, under the control of the voltage of described secondary nodal point, the voltage of the second DC source being provided To described output signal end；

Described primary nodal point is located on the wire connecting described input module, described drive module and described reseting module；Institute State secondary nodal point and be located at and connect described drive module, described reseting module, described first output module and described second output On the wire of module；

Described first clock signal and described second clock signal phase are contrary；

Described first output module specifically includes: the tenth transistor, the 11st transistor and the tenth two-transistor；Wherein, described Tenth transistor, its grid is connected with described secondary nodal point, and its source electrode is connected with described first DC source, its drain electrode respectively with institute The drain electrode stating the 11st transistor is connected with the grid of described tenth two-transistor；Described 11st transistor, its grid and institute State the first clock signal to be connected, its source electrode is connected with described second DC source；Described tenth two-transistor, its source electrode and described the One DC source is connected, and its drain electrode is connected with described output signal end.

2. shift register as claimed in claim 1 is it is characterised in that described input module specifically includes: the first transistor； Wherein,

Described the first transistor, its grid is connected with described first clock signal, and its source electrode is connected with described input signal end, its Drain electrode is connected with described primary nodal point.

3. shift register as claimed in claim 1 is it is characterised in that described drive module specifically includes: transistor seconds With the first electric capacity；Wherein,

Described transistor seconds, its grid is connected with described primary nodal point, and its source electrode is connected with described second clock signal；Its leakage Pole is connected with described secondary nodal point；

4. shift register as claimed in claim 1 is it is characterised in that described reseting module specifically includes: third transistor, 4th transistor and the 5th transistor；Wherein,

Described third transistor, its grid is connected with described first clock signal, and its source electrode is connected with described second DC source, its Drain electrode is connected with the drain electrode of described 4th transistor and the grid of described 5th transistor respectively；

5. shift register as claimed in claim 4 is it is characterised in that described reseting module also includes: the second electric capacity；Its In,

6. shift register as claimed in claim 1 is it is characterised in that described second output module specifically includes: the 6th is brilliant Body pipe, the 7th transistor, the 8th transistor and the 3rd electric capacity；Wherein,

Described 6th transistor, its grid is connected with described secondary nodal point, and its source electrode is connected with described second DC source, its drain electrode The grid of the drain electrode with described 7th transistor and described 8th transistor is connected；

Described 7th transistor, its grid is connected with described first clock signal, and its source electrode is connected with described first DC source；

7. shift register as claimed in claim 1 is it is characterised in that described second output module specifically includes: the 9th is brilliant Body pipe and the 4th electric capacity；Wherein,

Described 9th transistor, its grid is connected with described secondary nodal point, and its source electrode is connected with low-potential direct source, its drain electrode with Described output signal end is connected；

8. shift register as claimed in claim 1 is it is characterised in that described first output module also includes: the 5th electric capacity； Wherein,

9. the shift register as described in any one of claim 2-8 it is characterised in that:

All of transistor is p-type transistor, and described first DC source is high potential DC source, and described second DC source is Low-potential direct source；Or

All of transistor is n-type transistor, and described first DC source is low-potential direct source, and described second DC source is High potential DC source.

10. a kind of gate driver circuit is it is characterised in that include the shifting as described in multiple any one as claim 1-9 of series connection Bit register；Wherein,

The input signal end of first order shift register connects initial signal end, and in addition to first order shift register, remaining is each The input signal end of level shift register connects the output signal end of upper level shift register.

A kind of 11. display devices are it is characterised in that include gate driver circuit as claimed in claim 10.