JPH07287208A - Scanning circuit for display device, and plane display device - Google Patents

Abstract

PURPOSE:To provide the scanning circuit for the display device, and the plane display device which can decrease the number of input terminals of a display panel and simplify an external driving device. CONSTITUTION:Pulse signals VST and HST, and HCK1 and HCK2 are outputted from the external driving device 11 to a display part 10, and a VCK generating circuit 13 generates driving pulse signals VCK1 and VCK2. A horizontal shift register 4 scans signal lines S1-Sn on the basis of the driving pulse signals HCK1 and HCK2 from the external driving device 11 and a vertical shift register 2 scans gate lines G1-Gn on the basis of driving pulse signals VCK1 and VCK2 generated by a VCK generating circuit 13. For this scanning, pixels arranged in a matrix between the gate lines and signal lines are specified.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scanning circuit for a display device and a flat panel display device, and more particularly to a scanning circuit for a display device and a flat panel display device in which external terminals are reduced.

[0002]

2. Description of the Related Art For example, a display device such as a liquid crystal display device (LCD) has a number of gate lines corresponding to the number of scanning lines and signal lines arranged so as to be substantially orthogonal to the gate lines. However, pixels are formed at the intersections of these gate lines and signal lines. Therefore, the pixels are arranged in a matrix. A vertical shift register is connected to the gate line so that the gate line can be sequentially scanned.
In addition, a horizontal shift register is connected to the signal line,
It is possible to sequentially scan the signal lines. Then, the pixel is specified by the scanned gate line and signal line.

The scanning of the gate line by the vertical shift register uses a pulse signal VST for determining the scanning start timing of the gate line and drive pulse signals VCK1, VCK2 for sequentially specifying the gate line to be scanned. Is based on. The scanning of the signal line by the horizontal shift register is based on a pulse signal HST for determining the scanning start timing of the signal line and drive pulse signals HCK1 and HCK2 for sequentially specifying the signal lines to be scanned. Done. As the LCD panel, a type (scanning circuit integrated type) having a built-in scanning circuit for a display device, which includes a vertical shift register and a horizontal shift register,
There are different types. Recently, the scanning circuit integrated type L
CD panels are the mainstream.

Here, VCK2 is a signal obtained by inverting VCK1 and is used to ensure the scanning of the gate line by the vertical shift register. Similarly, HCK2
Is a signal obtained by inverting HCK1 and is used to ensure the scanning of the gate line by the horizontal shift register. Thus, in addition to VCK1 and HCK1,
A driving method using VCK2 and HCK2 is called a two-phase driving method.

In such an LCD panel integrated with a display circuit using the two-phase drive system, as shown in FIG. 9, for example, an external drive circuit 5 provided outside the LCD panel 1 is used.
Pulse signals HST, HCK1, HC generated in
LCD panel 1 with K2, VST, VCK1 and VCK2
Input via the external terminal of. Pulse signals HST and HCK input via the external terminals of the LCD panel 1.
1, HCK2 are input to the horizontal shift register 4, and the pulse signals VST, VCK1, VCK2 are input to the vertical shift register 2.

[0006]

However, as shown in FIG. 9, pulse signals HST, HCK1, HCK2 and VS are generated.
In the configuration in which T, VCK1 and VCK2 are generated in the external drive circuit 5, the external drive circuit 5 causes the LCD panel 1 to
It is necessary to transmit at least 6 signals, and the LCD panel 1 needs to be provided with at least 6 input terminals corresponding to the number of the signals. Therefore, there is a problem that the number of input terminals increases and the number of inspection steps for each input terminal increases. In addition, since the number of input terminals of the LCD panel 1 increases as described above, the number of wirings connected to the input terminals also increases. Therefore, there is also a problem that the degree of freedom in laying out the input terminal and the wiring is low.

Further, since the external drive circuit 5 generates at least 6 signals, there is a problem that the circuit structure is complicated. Further, since the LCD panel 1 has a large number of input terminals, there is a problem that it is easily affected by disturbance such as static electricity.

The present invention has been made in view of the above-mentioned problems of the prior art, and reduces the number of input terminals of the display panel, simplifies the external driving device, improves the degree of freedom of layout of input terminals and the like, and affects the influence of disturbance. An object of the present invention is to provide a scanning circuit for a display device and a flat-panel display device that can be reduced.

[0009]

In the scanning circuit for a display device of the present invention, a horizontal scanning pulse signal is input from an external device,
Horizontal scanning means for sequentially scanning the signal line based on the horizontal scanning pulse signal, vertical scanning pulse signal generating means for generating a vertical scanning pulse signal from the horizontal scanning pulse signal, and vertical scanning pulse signal generating means Vertical scanning means for sequentially scanning a gate line orthogonal to the signal line based on the generated vertical scanning pulse signal.

Further, in the flat panel display device of the present invention, a number of gate lines corresponding to the number of scanning lines and a video signal corresponding to the number of scanning lines are input in synchronization with the scanning of the gate lines, and the gate lines are supplied to the gate lines. Display means having signal lines arranged so as to be substantially orthogonal to each other and pixels formed at intersections of these gate lines and signal lines; and a horizontal scanning pulse signal inputted from an external device to carry out the horizontal scanning. Horizontal scanning means for sequentially scanning the signal lines of the display means based on pulse signals, vertical scanning pulse signal generating means for generating vertical scanning pulse signals from the horizontal scanning pulse signals, and vertical scanning pulse signal generating means. A vertical scanning unit that sequentially scans the gate lines of the display unit based on a vertical scanning pulse signal generated by is formed integrally with the drive substrate.

Further, in the flat panel display device according to the present invention, the vertical scanning pulse signal generating means is a common potential generating means for generating a common potential applied to a common electrode facing a pixel electrode to which a video input signal is applied. It can also be integrally built in the substrate on which is formed.

[0012]

In the scanning circuit for a display device and the flat display device of the present invention, the horizontal scanning pulse signal is generated in the external device, and the horizontal scanning pulse signal is output to the horizontal scanning means and the vertical scanning pulse signal generating means. The vertical scanning pulse signal generating means generates a vertical scanning pulse signal according to the horizontal scanning pulse signal input from the external device, and outputs the vertical scanning pulse signal to the vertical scanning means. That is, the vertical scanning pulse signal is generated based on the horizontal scanning pulse signal.

The vertical scanning means sequentially scans the gate lines of the display section based on the vertical scanning pulse signals input from the vertical scanning pulse signal generating means. On the other hand, the horizontal scanning means sequentially scans the signal lines of the display means based on the horizontal scanning pulse signal inputted from the horizontal scanning pulse signal generating means. In the flat panel display device of the present invention, the display means, the horizontal scanning means, the vertical scanning means, and the vertical scanning pulse signal generating means are integrally formed on a drive substrate that constitutes the flat panel display device, and the vertical scanning pulse signal is displayed on the flat panel. It is generated by the internal circuit of the device. As a result, it is not necessary to input the vertical scanning pulse signal from the external device to the flat panel display device, and the number of input terminals of the flat panel display device can be reduced.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A flat display device using a scanning circuit for a display device according to an embodiment of the present invention will be described in detail below with reference to the drawings. In the embodiments described below, a liquid crystal display device (LCD) is illustrated as a flat display device. However, the present invention is applicable to all display devices that perform scanning using horizontal scanning means and vertical scanning means, in addition to the LCD. It can be applied similarly. First, the first embodiment will be described. FIG. 1 is an equivalent circuit diagram of an essential part of an LCD using the display device scanning circuit according to the present embodiment.

As shown in FIG. 1, an external drive device 11 is provided outside the LCD 9. External drive device 11
Are pulse signals VST, HST and drive pulse signal H
The four signals CK1 and HCK2 are output to the LCD 9, and the drive pulse signals VCK1 and VCK2 are not output to the LCD 9. The LCD 9 includes a display unit 10, a vertical shift register 2,
The horizontal shift register 4 and the VCK generation circuit 13 are integrally formed on an active matrix substrate as a drive substrate. The vertical shift register 2 and the horizontal shift register 4 are VCK1, VCK2 and HCK, respectively.
The display unit 10 is scanned by the two-phase drive method using the 1 and HCK2. Here, VCK2 is a signal obtained by inverting VCK1, and HCK2 is a signal obtained by inverting HCK1. Thus, the reason why VCK2 and HCK2 are used is to ensure the reliability of scanning of the display unit 10. In this embodiment,
The drive pulse signals VCK1 and VCK2 are generated by the VCK generation circuit 13 incorporated in the LCD 9.

First, the display unit 10 shown in FIG. 1 will be described. The display unit 10 is provided on the active matrix substrate.
The number of gate lines G1, G2 ... Gn corresponding to the number of scanning lines,
Signal lines S1, S2 ... Sn arranged substantially orthogonal to the gate lines are formed. Gate line G1,
The number of G2 ... Gn is, for example, 625 when the video signal is the NTSC system, and is one half of 625 because one image (one frame) is displayed in two fields.
It is 62.5 or more. The gate lines G1, G2 ... G
It is sufficient that n and the signal lines S1, S2 ... Sn are substantially orthogonal to each other as a whole. Microscopically, the signal lines S1, S2 ...
Sn or the gate lines G1, G2 ... Gn may meander. For example, in the delta arrangement, the signal lines S1,
S2 ... Sn meanders.

The gate lines G1, G2 ... Gn and the signal lines S1,
An intersection point with S2 ... Sn corresponds to one pixel, and a switch element 12 composed of, for example, a thin film transistor (TFT) and a capacitor element 8 are formed in this portion. A counter substrate on which a common electrode is formed via a liquid crystal layer is arranged on the active matrix substrate. as a result,
As shown in FIG. 1, the liquid crystal 6 for each pixel is connected in parallel to the capacitive element 8. By selectively applying a voltage to the liquid crystal 6 for each pixel, the molecular arrangement of the liquid crystal part is partially changed for each pixel, and an image can be displayed.

A signal voltage Vsig as shown in FIG. 8 is applied to the signal lines S1, S2, ... Sn. The signal voltage Vsig is displaced with the common potential Vcom applied to the common electrode as the center potential so that an electric field inverted in a predetermined cycle, for example, one field cycle is generated in the liquid crystal 6. The reason for reversing the electric field generated in the liquid crystal 6 is to protect the liquid crystal. That is, if an electric field in the same direction is always applied to the liquid crystal 6, the liquid crystal 6 may be electrolyzed and deteriorated, and this is for preventing this.

The common potential Vcom is supplied from the external driving device 11 via the supply line 17, or may be generated inside the LCD 9 as described in the second embodiment.

A vertical shift register 2 as a vertical scanning means is connected to the gate lines G1, G2 ... Gn so that the gate lines G1, G2 ... Gn can be sequentially scanned. Further, the signal lines S1, S2 ... Sn are connected to the video input lines 14R, 14G, 14 via the scanning switch 16.
It is connected to B. Video input lines 14R, 14G, 14B
The video signal is input from the signal lines to the signal lines S1, S2 ... Sn. In this embodiment, three types of input lines for R, G, and B are used as the video input lines, but a single-line input line can be used when a color image is not required. The scanning of the gate lines G1, G2, ... Gn by the vertical shift register 2 is performed by the drive pulse signal V
The levels of the gate lines G1, G2, G3 ... Gn are sequentially changed to a low level as shown in FIG. 5 according to the scanning signal generated based on CK1. Here, when the gate line becomes low level, all the switch elements 12 connected to the gate line are opened.

The scanning switch 16 is connected to a horizontal shift register 4 as a horizontal scanning means through an output logic circuit, and the scanning switch 16 is sequentially opened according to a scanning signal from the horizontal shift register 4 to open a gate. Line G1,
G2 ... Gn in synchronism with the scanning of the video signal,
S2 ... Send to Sn.

As described above, in order to drive the display section 10 based on the scanning signals from the vertical shift register 2 and the horizontal shift register 4, the driving signals (HST, HCK1,
HCK2, VST, VCK1, VCK2) must be input respectively.

In this embodiment, as described above, these drive signals (HST, HCK1, HCK2, VST, VCK) are used.
1, VCK2), pulse signals HST, VST and drive pulse signals HCK1, HCK2
Drive pulse signals VCK1, VCK2
Is generated in the VCK generation circuit 13 built in the LCD 9.

Therefore, the external driving device 11 is configured so that the pulse signals HST, VST and the driving pulse signals HCK1, HCK are generated.
2 is output to the LCD 9 and the drive pulse signals VCK1 and VC are output.
It is not necessary to output K2 to LCD9. As a result, LC
It is not necessary to provide an input terminal for inputting the drive pulse signals VCK1 and VCK2 in D9, and the number of input terminals can be reduced.

In the LCD 9, the pulse signal HST and the drive pulse signal HC input from the external drive device 11 are input.
K1 and HCK2 are supplied to the horizontal shift register 4, and the pulse signal VST input from the external drive device 11 is VCK.
It is supplied to the generation circuit 13 and the vertical shift register 2.

In the LCD 9, the horizontal shift register 4 outputs the pulse signal HOUT to the VCK generation circuit 13. The pulse signal HOUT is a signal synchronized with the pulse signal HST, and is output at the timing when a high-level pulse used for scanning the signal line Sn of the drive pulse signal HCK1 is output. Here, the signal line Sn is scanned last when the signal lines S1 to Sn are sequentially scanned in the horizontal scanning. In this embodiment, the drive pulse signals VCK1 and VCK2 are generated based on the pulse signal HOUT naturally generated in the horizontal shift register 4, as described later.

The VCK generation circuit 13 is connected to the external drive unit 11.
Drive pulse signal VST based on the pulse signal VST input from the horizontal shift register 4 and HOUT input from the horizontal shift register 4.
CK1 and VCK2 are generated to drive these drive pulse signals V
CK1 and VCK2 are output to the vertical shift register 2.

As described above, in this embodiment, the drive pulse signals VCK1 and VCK2 are the VCK built in the LCD 9.
It is generated in the generation circuit 13.

FIG. 2 is a diagram for explaining an example of the VCK generation circuit 13. As shown in FIG. 2, the VCK generation circuit 13 is realized by using, for example, a D flip-flop FP. In this case, the pulse signals HOUT and RESET are applied to the clock terminal CLK of the D flip-flop FP.
Input pulse signal VST to the terminal, and D terminal and ￣ (inversion)
Connect with the Q terminal. At this time, the output of the Q terminal is the drive pulse signal VCK1, and the output of the Q terminal is the drive pulse signal VCK1.
It becomes CK2.

Another example of the circuit used as the VCK generation circuit 13 will be described below. 3 is a circuit diagram of the VCK generation circuit 13, FIG. 4A is an equivalent circuit diagram of the VCK generation circuit 13 shown in FIG. 3 when φ is at a low level, and FIG.
(B) is an equivalent circuit diagram of the VCK generation circuit 13 shown in FIG. 3 when φ is at a high level.

As shown in FIG. 3, the VCK generation circuit 13
Are NOT gates 20 to 28, NOR gate 29, NA
It is composed of an ND gate 30 and switches SW1 to SW4. In the VCK generation circuit 13, the pulse signal VST is
It is input to one input terminal of the NAND gate 30 having two inputs and one output, and is also input to the other input terminal of the NAND gate 30 through the NOT gates 25, 26 and 27 in sequence. The output terminal of the NAND gate 30 is the NOT gate 28.
Of the NOR gate 29, and the output terminal of the NOT gate 28 is connected to one input terminal of the NOR gate 29 having two inputs and one output. The output terminal of the NOR gate 29 is connected to the input terminal of the NOT gate 22 via the switch SW2, and the NO terminal is sequentially connected via the switches SW2 and SW1.
It is also connected to the output terminal of the T gate 24. The output terminal of the NOT gate 22 is the other input terminal of the NOR gate 29, the input terminal of the NOT gate 23 via the switch SW3, and the NOT terminal via the switches SW3 and SW4.
Each of them is connected to the output terminal of the gate 24. NO
The output terminal of the T gate 23 is connected to the input terminal of the NOT gate 24. Here, the signal output from the NOT gate 23 becomes the drive pulse signal VCK1,
The signal output from the gate 24 is the drive pulse signal VCK
It becomes 2.

The switches SW1 to SW4 are composed of transistors, and are rendered conductive or non-conductive based on the control signal φ and the control signal φ (inversion) φ obtained by inverting φ. Switches SW1, SW4
Becomes non-conductive when the control signal φ is low level, and becomes conductive when the control signal φ is high level. On the other hand, the switches SW2 and SW3 are rendered non-conductive when the control signal φ is at high level, and are rendered conductive when the control signal φ is at low level. Therefore, when the control signal φ is low level, the VCK generation circuit 13 shown in FIG.
The equivalent circuit is as shown in. On the other hand, when the control signal φ is at the high level, the VCK generation circuit 13 shown in FIG. 2 becomes an equivalent circuit as shown in FIG. 4 (B).

The control signal φ is a pulse signal HO
The control signal φ is an output signal of the NOT gate 20 according to the UT, and the control signal φ is an output signal of the NOT gate 21 according to the pulse signal HOUT.

The operation of the VCK generation circuit 13 will be described. FIG. 6 is a timing chart for explaining the operation of the VCK generation circuit 13. In FIG. 6, the signal S
A, SB, SC, SD, SE, SG are VCK respectively
When the generation circuit 13 is operating, points A, B, and
The waveforms are C, D, E, F, and G. VCK generation circuit 13
Then, the pulse signal VST changes to the NOT gates 25, 26, 2
7, the NAND gate 30 is delayed by a predetermined time.
The pulse signal VST that has not been delayed is input to the other input terminal of the NAND gate 30 while being input to one of the input terminals. Then, the NAND gate 30 calculates the negation of the logical product of the delayed pulse signal VST and the undelayed pulse signal VST, and the signal corresponding to the negative of the logical product is inverted by the NOT gate 28, The inverted signal is output to one input terminal of the NOR gate 29 as the pulse signal RESET.
At this time, the pulse signal RESET is the pulse signal VST.
6 has a waveform shown in FIG. 6 including a high-level pulse having a pulse width which is synchronized with the high-level pulse included in the pulse width.

On the other hand, the pulse signal HOUT has a waveform as shown in FIG. 6, the control signal φ has the same waveform as the pulse signal HOUT, and the control signal φ
Has a waveform obtained by inverting the pulse signal HOUT.

The VCK generation circuit 13 has a pulse signal RES.
It operates as follows based on ET and control signals φ and φ. As shown in FIG. 6, the pulse signal RES
When ET rises from a low level to a high level, a low level signal SD as shown in FIG. 6 appears at point D, which is the output point of the NOR gate 29, in synchronization with the rise. At this time, the pulse signal HOUT is at a low level, and the VCK generation circuit 13 is in the low level.
Substantially corresponds to the switch SW2, as shown in FIG.
A circuit in which SW3 is conductive and switches SW1 and SW4 are non-conductive forms a circuit. Pulse signal RES
The ET outputs a high level pulse at a timing immediately before the start of scanning for a new field.

After that, when the pulse signal RESET falls from the high level to the low level, the pulse signal RESET
T keeps low level until just before starting scanning of the next field. While the pulse signal HOUT is at low level, the signal SD is at low level, so SB is at low level, signals SC and SE are at high level, and signal SF (V
CK1) becomes low level, and signals SG (VCK2) and SA become high level.

After that, when the pulse signal HOUT rises from the low level to the high level, in the VCK generation circuit 13, the switches SW2 and SW3 are in the non-conducting state and the switches SW1 and SW4 are in the conducting state, as shown in FIG. 4B. A circuit that is in a state. Since the points A and B become conductive in synchronization with the rising of the pulse signal HOUT, the signal SB rises from the low level to the high level of the signal SA. At the same time, the signal SC falls from high level to low level and the signal SD rises. At this time, the levels of the signals SA, SE, SF, SG do not change. Then, while the pulse signal HOUT is at the high level,
The signals SA to SG maintain the level after the rise of HOUT.

After that, when the pulse signal HOUT falls from the high level to the low level, the VCK generation circuit 13 constitutes the circuit shown in FIG. 4 (A). Pulse signal HOUT
Since the point C and the point E are brought into conduction in synchronization with the fall of the signal, the signal SE falls to the low level of the signal SC. In response to the fall of the signal SE, the signal S
F rises, signal SG falls, and signal SA also falls.

Thereafter, the signals SA, SB, SC, SD, S
E, SF (VCK1) and SG (VCK2) repeat the above-mentioned changes according to the pulse signal HOUT,
A waveform as shown in FIG. 6 is obtained.

As described above, according to the VCK generation circuit 13, the drive pulse signals VCK1 and VC are generated based on the pulse signal HOUT supplied from the horizontal shift register 4 and the pulse signal VST supplied from the external drive device 11.
K2 can be generated. The VCK generation circuit 13
Since the LCD 9 is built in together with the vertical shift register 2 and the horizontal shift register 4, the external drive device 11
Drive pulse signal H among the signals output from LCD to LCD 9
There is no need to output CK1 and HCK2.

As a result, since at least two input terminals of the LCD 9 can be reduced, the inspection items of the input terminals at the time of inspection can be reduced, and the inspection time can be shortened. Further, since the number of input terminals of the LCD panel 1 can be reduced in this way, the number of wirings connected to the input terminals can also be reduced. Therefore, the degree of freedom in laying out the input terminal and the wiring can be increased. Further, as a result of reducing the number of input terminals of the LCD 9, the influence of disturbance such as static electricity can be reduced, and the reliability of the operation of the scanning circuit can be improved. Further, the external drive device 11 does not need to generate the drive pulse signals VCK1 and VCK2, and the configuration of the external drive device 11 can be simplified.

The second embodiment will be described. The flat display device and the scanning circuit for a display device of this embodiment supply the common potential Vcom to the common electrode connected to one end of the liquid crystal 6 and the capacitive element 8 as compared with the first embodiment described above. The common potential generating circuit of is also different in that it is incorporated in the LCD panel, and the others are common. That is, in this embodiment, the common potential Vcom is generated inside the LCD 9 without being input from the external driving device 11 shown in FIG. As shown in FIG. 7, the display device scanning circuit of the present embodiment has a common potential generating circuit 39 built in the LCD 9, and the common potential generating circuit 39 generates the common potential Vcom. The common potential Vcom generated in the common potential generation circuit 39 is supplied to the common electrode connected to one end of the liquid crystal 6 and the capacitive element 8 via the supply line 15 shown by the dotted line.

The common potential generating circuit 39 will be described in detail. As shown in FIG. 7, the common potential generating circuit 39
A resistor 40 and thin film transistors (TFTs) 41 to 45 such as nMOS transistors are connected in series between the dd supply line and the Vss supply line, and T is connected in parallel with this.
The FTs 46 and 47 are connected in series. Here, Vdd is about 12 to about 15V. The TFTs 41 to 45 and 47 are
The drain and the gate are connected to each other. TFT4
The gate of 6 is connected to the drain of the TFT 41. The connection point between the source of the TFT 46 and the drain of the TFT 47 is connected to the common electrode via the supply line 15 shown by the dotted line, and the potential at the connection point becomes the common potential Vcom.

In the common potential generation circuit 39, the TFTs 41 to
The TFT 45 has a voltage drop of about 1.0 to about 1.2 V between its gate and source, and a predetermined potential corresponding to the voltage drop is a connection point between the drain of the TFT 41 and the resistor 40. Occurs at the gate of. The potential generated at the gate of the TFT 46 in this manner causes the TFT 4
A potential slightly lower than about 6.0 V is generated at the source of 6,
The potential becomes the common potential Vcom.

Resistance value of resistance 40, resistance 40 and V
The number of TFTs connected between the ss supply line is
The potential of the source of 46 is determined to be slightly lower than about 6.0V.

Thus, in the common potential generation circuit 39,
By accumulating the voltage drop between the gate and the source of the TFTs 41 to 45, the common potential Vcom required for the source of the TFT 46 is generated. As described above, by generating the common potential Vcom using the TFTs, when the potentials of the Vss supply line and the Vdd supply line vary, these TFTs suppress the variation of the common potential Vcom due to the variation of the potential. Act as you do. As a result, the common potential generation circuit 39 can generate a stable common potential Vcom.

Since the common potential generating circuit 39 for generating the common potential Vcom is built in the LCD 9, it is not necessary to provide an input terminal for providing the common voltage Vcom from the outside. As a result, compared to the case of the first embodiment, L
The input terminals of CD9 can be further reduced.

Further, according to the display device scanning circuit of this embodiment, since the common potential Vcom is generated inside the LCD 9, the center potential of the signal voltage Vsig and the common potential Vcom.
It is possible to properly prevent a gap from occurring with com. That is, according to the present embodiment, compared to the case where the external drive device 11 generates the common potential Vcom, the common potential Vco is
The wiring distance from the generation point of m to the common electrode can be shortened, and the voltage drop of the common potential Vcom due to the wiring resistance can be reduced. As a result, it is easy to design the potential of the common potential Vcom to approach the potential at the time of generation, that is, the central potential of the signal voltage Vsig.

In the above-mentioned embodiment, the case of using the two-phase driving method is illustrated, but the driving method may be the single-phase driving method. In this case, the vertical shift register 2 and the horizontal shift register 4 respectively have VCK.
1 and HCK1 are input, and pulse signals VST and HS are input.
Three signals of T and the drive pulse signal HCK1 are transmitted from the external drive device 11 to the LCD 9. In another embodiment, a single-phase signal is sent from the external drive device 11 to the LCD 9
Alternatively, the signal may be generated by the two-phase driving method inside the LCD 9.

In the above-described embodiment, the VCK generation circuit 13 drives the drive pulse signals VCK1 and VCK based on the pulse signal HOUT generated by the horizontal shift register 4.
2 is generated, but the VCK generation circuit 13 uses the external drive device 1
The drive pulse signals VCK1 and VCK2 may be generated based on the pulse signal HST input from 1. This is because the pulse signal HST and the pulse signal HOUT are substantially the same.

[0052]

As described above, according to the display device scanning circuit of the present invention, it is not necessary to transmit a vertical scanning pulse signal from the external device to the display device scanning circuit, and the external device scanning circuit can be used. The number of signals sent to the circuit can be reduced. Therefore, it is not necessary to provide an input terminal for inputting a vertical scanning pulse signal in the display device scanning circuit of the present invention, and the number of input terminals of the display device scanning circuit can be reduced.
Further, according to the flat panel display device of the present invention, it is not necessary to input the vertical scanning pulse signal from the external device to the flat panel display device, and the number of signals transmitted from the external device to the flat panel display device can be reduced. Therefore, it is not necessary to provide an input terminal for inputting the vertical scanning pulse signal in the flat display device of the present invention, and the number of input terminals of the flat display device can be reduced. According to the scanning circuit for a display device and the flat display device of the present invention, as a result of reducing the number of input terminals, the number of wirings connected to the input terminals can be reduced, and the degree of freedom in laying out the wirings and the input terminals can be increased. You can Further, according to the scanning circuit for a display device and the flat panel display device of the present invention, the number of input terminals can be reduced, so that the number of inspection items at the time of inspection can be reduced and the inspection time can be shortened and shortened. Further, according to the scanning circuit for a display device and the flat display device of the present invention, the number of input terminals can be reduced, and as a result, the influence of disturbance such as static electricity can be reduced. Further, according to the scanning circuit for a display device and the flat display device of the present invention, it is not necessary to generate the vertical scanning pulse signal in the external device, and the configuration of the external device can be simplified.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram of a main part of an LCD using a scanning circuit for a display device according to a first embodiment of the present invention.

FIG. 2 is a diagram for explaining a D flip-flop as an example of the VCK generation circuit shown in FIG.

FIG. 3 is a circuit diagram for explaining another example of the VCK generation circuit.

FIG. 4A shows V shown in FIG. 3 when φ is at a low level.
An equivalent circuit diagram of the CK generation circuit, (B) is an equivalent circuit diagram of the VCK generation circuit shown in FIG. 3 when φ is high level.

FIG. 5 is a timing chart for explaining a relationship between a pulse signal VST, a drive pulse signal VCK1 and a scanning signal applied to a gate line.

FIG. 6 is a timing chart for explaining the operation of the VCK generation circuit.

FIG. 7 is a main part equalization circuit diagram of an LCD using a scanning circuit for a display device according to a second embodiment of the present invention.

FIG. 8 is a signal waveform diagram for explaining a relationship between a signal voltage Vsig applied to signal lines S1, S2, ... Sn and a common potential Vcom.

FIG. 9 is a diagram for explaining a conventional scanning circuit for a display device.

[Explanation of symbols]

 1 ... LCD panel 2 ... Vertical shift register 4 ... Horizontal shift register 5, 11 ... External drive device 6 ... Liquid crystal 8 ... Capacitance element 9 ... LCD 10 ... Display Part 12 ... Switch element 13 ... VCK generation circuit 16 ... Scan switch 39 ... Common potential generation circuit

Claims (2)

[Claims] 1. A horizontal scanning unit which receives a horizontal scanning pulse signal from an external device and sequentially scans a signal line based on the horizontal scanning pulse signal, and a vertical scanning unit which generates a vertical scanning pulse signal from the horizontal scanning pulse signal. Scanning for display device having scan pulse signal generating means and vertical scanning means for sequentially scanning gate lines orthogonal to the signal lines based on the vertical scanning pulse signals generated by the vertical scanning pulse signal generating means circuit. 2. A number of gate lines corresponding to the number of scanning lines and a video signal corresponding to the number of scanning lines are input in synchronization with the scanning of the gate lines and arranged so as to be substantially orthogonal to the gate lines. And a display unit having a pixel formed at an intersection of the gate line and the signal line, and a horizontal scanning pulse signal from an external device, and the display unit based on the horizontal scanning pulse signal. Horizontal scanning means for sequentially scanning the signal lines, vertical scanning pulse signal generating means for generating a vertical scanning pulse signal from the horizontal scanning pulse signal, and vertical scanning pulse signal generated by the vertical scanning pulse signal generating means. And a vertical scanning means for sequentially scanning the gate line of the display means based on the above, integrally formed on a drive substrate.