CN102759861A - Photoetching modifying method for integrated circuit manufacture - Google Patents
Photoetching modifying method for integrated circuit manufacture Download PDFInfo
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- CN102759861A CN102759861A CN2011101081619A CN201110108161A CN102759861A CN 102759861 A CN102759861 A CN 102759861A CN 2011101081619 A CN2011101081619 A CN 2011101081619A CN 201110108161 A CN201110108161 A CN 201110108161A CN 102759861 A CN102759861 A CN 102759861A
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Abstract
The invention provides a photoetching modifying method for integrated circuit manufacture. The method includes: determining an optimal optical proximity correction model, a photoetching target, and sub-resolution assist feature parameters according to a design picture of an original layout; decomposing the design picture of the original layout on the basis of criterion of minimum pitch and minimum spacing; placing a sub-resolution assist feature and applying optical proximity correction to the mask pattern picture obtained by decomposing; examining optical rules and mask error enhancement factors; and evaluating examining results. By the method, the problem that tiny gabs exist at corners and connections of decomposed pictures in existing picture decomposing methods is solved, line width deviation, line end retraction and corner rounding of obtained pictures after DPT (delay picture transmission) can be well controlled, final picture quality transferred to each material layer of a silicon wafer can be guaranteed, and performance of an IC (integrated circuit) is improved.
Description
Technical field
The present invention relates to improve in the integrated circuit manufacturing method of photoetching, in particular to the original layout design figure decomposition method of the double-pattern technology that is used for the 32nm manufacturing process.
Background technology
Photoetching is the important process that integrated circuit (IC) is made, and the main task of photoetching process is the transfer of figure on the silicon face layers of material that realizes on the mask.In order to satisfy the requirement that the VLSI (very large scale integrated circuits) characteristic dimension is constantly dwindled, the projection lithography technology has obtained developing rapidly, is the core of photoetching technique and improve photoetching resolution.Photoetching resolution is meant the minimum feature size that can make public at silicon chip surface through litho machine, and promptly minimum distinguishable half-section is apart from (HP
Min), it satisfies Rayleigh equation:
HP
min＝k
1*λ/NA (1)
Wherein: k
1-technological parameter the factor; The wavelength of λ-exposure light source; The numerical aperture of NA-etching system lens.
For the 193nm water logging of routine there was not photoetching technique, technology was limited to k at present
1>=0.25 graph exposure, under the condition of NA value≤1.35, minimum distinguishable half-section is apart from being limited to HP
Min>=36nm can not satisfy the needs of 32nm manufacturing process.A kind of way that addresses the above problem is to use extreme ultraviolet lithography (EUV), and it can be reduced to 13.4nm with the λ value, is the needs that can satisfy 32nm even 18nm manufacturing process under 0.25 the condition in the NA value; Another kind of way is still to use the 193nm immersion photolithography, and it adopts the third generation to immerse liquid (refractive index RI＞1.8) and has the more photoresist and the lens material of high index of refraction, so that the NA value brings up to 1.55, thereby satisfies the needs of 32nm manufacturing process.Yet,,, can in the process that IC makes, not use in a short time no matter be third generation lens material or EUV relevant device from the consideration of manufacturing cost and correlation technique factor.
In order to satisfy the requirement that integrated circuit feature size is constantly dwindled under the Moore's Law, adopt double-pattern technology (DPT) only to need existing photoetching infrastructure is carried out very little change, just can realize the more photoetching technique of minor node.Can increase the complexity of technology and the problem of the invisible cost increase that production efficiency decline brings although DPT is faced with double exposure, than other technology, it is still the desirable solution that satisfies 32nm manufacturing process needs.
In the implementation process of double-pattern technology, matter of utmost importance is the resolution problem of original layout design figure, has loose HP through being decomposed into figure two
MinSpirte, evaded k
1Restriction.Existing decomposition method is according to the minimum pitch criterion of actual process decision the original layout design figure to be decomposed, and promptly pitch is decomposed (pitch split), and so-called pitch is meant the live width of original layout design pattern line and the spacing sum between the lines.After according to the method the figure of dense distribution and stepped figure being decomposed; Between figure turning and connecting portion, produce the very little gap of spacing; Optical near-correction (OPC) is afterwards because the adjustment of technological parameter (exposure dose, imaging focal length, mask error or the like); Spacing requirement when two block graphicses joint can not be satisfied in the gap that these spacings are very little; Cause the characteristic dimension (CD) of figure to depart from setting value, i.e. live width deviation, and significantly line end retraction and turning sphering phenomenon.CD does not reach standard or distortion occurs, and technology (FEOL) can influence the transistor electrical property in preceding road, like close current I
OffWith threshold voltage V
t, even make transistor nonfunctional; Can cause the rising of contact resistance etc. at postchannel process (BEOL).
Therefore, need a kind of new design configuration decomposition method, solve CD effectively and do not reach standard and the problem that distortion occurs, improve the DPT quality of gained figure afterwards further.
Summary of the invention
To the deficiency of prior art, the invention provides a kind of method that integrated circuit manufacturing is improved photoetching that is used for, comprising:, establish optimum optical near-correction model, lithographic object, auxiliary figure with low resolution parameter according to the design configuration of original layout; Decompose the design configuration of said original layout based on minimum pitch and minimum spacing criterion; Mask pattern to decomposition obtains is placed auxiliary figure with low resolution and applied optics near-correction; The check of mask error enhancer is carried out in the inspection of operation optical rules simultaneously under the certain process tolerance; Aforementioned assay is estimated.
In the method for the invention, said minimum pitch is the minimum value of spacing sum between lines live width and the lines of the original layout design figure of actual process decision under the manufacturing process node; Said minimum spacing is the minimum value of spacing between the lines line end of the original layout design figure of actual process decision under the manufacturing process node, is set at 1/2nd of said minimum pitch; The spacing of decomposing the mask pattern lines line end that obtains is greater than said minimum spacing.
In the method for the invention, the said step that aforementioned assay is estimated comprises: if the gained figure meets the figure degree of accuracy constrained parameters of setting after the double-pattern technical finesse, then carry out the manufacturing of mask; If the gained figure does not meet the figure degree of accuracy constrained parameters of setting after the double-pattern technical finesse, then optimize minimum pitch and minimum spacing decomposition criteria, decompose the design configuration of said original layout again; If the gained figure does not meet the figure degree of accuracy constrained parameters of setting after the double-pattern technical finesse, then design the design configuration of said original layout again.
In the method for the invention, the figure degree of accuracy constrained parameters of setting comprise characteristic dimension deviation, line end retraction deviation or MEEF allowed band.
In the method for the invention, decompose the cutting that figure relates to pattern line, follow following principle during cutting: cleavage is preferentially chosen the position between the extension of pattern line, narrow/wide line intersection or narrow line and ground connection pressure welding; The junction is fully overlapping when cleavage is reserved crossover region assurance figure joint.
In the method for the invention, said certain process tolerance comprises imaging focal length and illumination dose.
According to the present invention; Can avoid adopting existing figure decomposition method to decompose the slight gap that between figure turning and connecting portion, exists after the figure; Control DPT live width deviation, line end retraction and the turning sphering phenomenon of gained figure afterwards well; Guarantee finally to transfer to the quality of the figure on the silicon chip layers of material, improve the performance of IC.
Description of drawings
Attached drawings of the present invention is used to understand the present invention at this as a part of the present invention.Embodiments of the invention and description thereof have been shown in the accompanying drawing, have been used for explaining principle of the present invention.
In the accompanying drawing:
Figure 1A is the original layout of the embodiment of the invention;
Figure 1B is the synoptic diagram that the design configuration among Figure 1A 101 is decomposed according to existing pitch decomposition method;
Fig. 1 C decomposes the synoptic diagram of checking the pattern line profile that obtains to the decomposable process of figure shown in Figure 1B;
Fig. 1 D is the synoptic diagram that the design configuration among Figure 1A 101 is decomposed according to the original layout design figure decomposition method that the present invention proposes;
Fig. 1 E decomposes the synoptic diagram of checking the pattern line profile that obtains to figure decomposable process shown in Fig. 1 D;
Fig. 2 is the process flow diagram that the decomposition of original layout design figure is optimized based on minimum pitch and minimum spacing criterion that the present invention proposes;
Fig. 3 A is the synoptic diagram that the figure among Figure 1A 102 is decomposed according to the original layout design figure decomposition method that the present invention proposes;
Fig. 3 B decomposes the synoptic diagram of checking the pattern line profile that obtains to figure decomposable process shown in Fig. 3 A;
Fig. 4 implements the process flow diagram that the original layout design figure decomposes according to the method that the present invention proposes.
Embodiment
In the description hereinafter, a large amount of concrete details have been provided so that more thorough understanding of the invention is provided.Yet, it is obvious to the skilled person that the present invention can need not one or more these details and be able to enforcement.In other example,, describe for technical characterictics more well known in the art for fear of obscuring with the present invention.
In order thoroughly to understand the present invention, will in following description, detailed steps be proposed so that explanation the present invention be how effectively to control double-pattern technology (DPT) handle after the lines form of gained figure.Obviously, execution of the present invention is not limited to the specific details that the technician had the knack of of semiconductor applications.Preferred embodiment of the present invention is described in detail as follows, yet except these were described in detail, the present invention can also have other embodiments.
Shown in Figure 1A, be random logic cell layout for the 32nm node design and manufacture technology that adopts double-pattern technology (DPT), wherein dark part is the Poly layer, comprises figure 101 and figure 102.The minimum pitch of initial designs (pitch) is 90nm, and minimal characteristic live width (CD) is 32nm, and minimum spacing (space) is 58nm.
For figure 101, the 193nm water logging there is not photoetching technique (NA=1.2, k under the 32nm node manufacturing process
1=0.4) minimum pitch of decision is 130nm, need the design configuration of original layout be decomposed.According to existing pitch decomposition method; Pitch between the pattern line after the decomposition should be greater than 130nm; Lines 3 in the figure 101 break off at the middle corners place, are decomposed into two lines 3a and 3b, and figure 101 is decomposed into two mask patterns 103 and 104; Shown in Figure 1B: mask pattern 103 comprises lines 3a and lines 5 and lines 1, and mask pattern 104 comprises lines 3b and lines 4 and lines 2.In the mask pattern 103, the line end of lines 5 is near the turning of lines 3a, and the turning line end of lines 3a is very short; In the mask pattern 104, the turning of lines 4 produces the very little gap of spacing near the turning line end of lines 3b between the above-mentioned position of figure, and promptly the spacing between the pattern line line end is very little.
Above-mentioned figure decomposable process is decomposed the pattern line profile that obtains of check shown in Fig. 1 C; Wherein figure (a) is that (through process window) carries out the pattern line profile that optical rules inspection (ORC) obtains under the certain process tolerance, and figure (b) carries out the pattern line profile that mask error enhancer (MEEF) check obtains.Because the spacing between the pattern line line end after decomposing is very little; Optical near-correction (OPC) can not satisfy the spacing requirement that figure engages afterwards; Tangible live width deviation, line end retraction and turning sphering phenomenon appear in the lines of gained figure after causing making public, and the alignment precision when lines 3a engages with lines 3b simultaneously also can variation.
In order to solve the technical matters of above-mentioned appearance better; The present invention adopts improved design configuration decomposition method; This method is introduced the notion of minimum spacing and is combined with the minimum pitch criterion of actual process decision the original layout design figure is decomposed, and the spacing of the pattern line line end after the decomposition should be greater than minimum spacing, and this minimum spacing needs set according to the virtual rating of actual process; Usually be set at 1/2nd of minimum pitch, promptly the minimum spacing of embodiment is 65nm.Thus, figure 101 is decomposed into mask pattern 105 and 106 two parts of mask pattern, and shown in Fig. 1 D: mask pattern 105 comprises lines 1, lines 4 and lines 5; Mask pattern 106 comprises lines 2 and lines 3; Lines 3 are not disconnected; Any part of lines 3 is not combined in one group of mask pattern with lines 4 or lines 5, thereby avoids occurring the too small too short problem of turning line end with lines of spacing between the pattern line line end.
Above-mentioned figure decomposable process is decomposed the pattern line profile that obtains of check shown in Fig. 1 E; Wherein figure (a) is that (through process window) carries out the pattern line profile that optical rules inspection (ORC) obtains under the certain process tolerance, and figure (b) carries out the pattern line profile that mask error enhancer (MEEF) check obtains.The pattern line form is well controlled, and the live width deviation is very little, does not have line end retraction and turning sphering phenomenon basically.
Compare with existing pitch decomposition method; The design configuration decomposition method that the present invention proposes is not single decomposing according to the design configuration of the pitch between the pattern line to original layout; After the original layout design figure being decomposed according to the minimum pitch criterion; If the spacing between the pattern line line end is less than minimum spacing, these figures can not be placed in one group of mask pattern so; Need be according to the Capability Requirement of actual process adjustment minimum pitch criterion, the spacing that makes the pattern line line end after the decomposition is greater than minimum spacing.For figure 101, minimum spacing is set at 65nm, and lines 3 can not be placed in one group of mask pattern with lines 4 and lines 5; Can adopt radical pitch decomposition criteria, promptly the 193nm water logging there is not the minimum pitch of photoetching technique decision to be adjusted into 115nm (NA=1.35, k under the 32nm node manufacturing process
1=0.4), the pitch between the pattern line after the decomposition should be greater than 115nm, and the spacing between the pattern line line end should be greater than 65nm.Than single method of the design configuration of original layout being decomposed according to the minimum pitch criterion; The figure decomposition criteria that the present invention adopts has littler pitch; Thereby make between the figure of dense distribution and after figure decomposes, have bigger spacing; Width requirement when satisfying that figure combines after the OPC is effectively controlled the lines form of gained figure after the DPT.
For this reason, the present invention proposes the flow process that the decomposition of the design configuration of original layout is optimized based on minimum pitch and minimum spacing criterion, as shown in Figure 2.To the design configuration of original layout, establish optimum optical near-correction (OPC) model, lithographic object, SRAF (auxiliary figure with low resolution) parameter; Set a pitch criterion in conjunction with minimum pitch and minimum spacing the design configuration of original layout is decomposed, the spacing of the pattern line line end after the decomposition is greater than minimum spacing; Mask pattern to after decomposing is placed SRAF and applied optics near-correction (OPC); (through process window under the certain process tolerance; Comprise imaging focal length focus and illumination dose dose) move ORC (optical rules inspection) with control live width deviation; Reduce line end retraction and turning sphering phenomenon, carry out MEEF (mask error enhancer) check simultaneously; Figure degree of accuracy constrained parameters according to setting are analyzed the assay of ORC and MEEF, if meet, then carry out the manufacturing of mask; If do not meet; Then combine minimum pitch and minimum spacing to reset a pitch criterion and decompose original layout (promptly decomposing original layout again); Carry out above-mentioned check meets the figure degree of accuracy of setting up to the gained figure requirement then; Can not meet the demands if decompose original layout again, then design original layout again to satisfy the requirement of the figure degree of accuracy of setting.
Shown in Fig. 3 A, according to the design configuration decomposition method that the present invention proposes, the figure 102 in the embodiment original layout is decomposed into mask pattern 107 and 108 two parts of mask pattern.
Figure degree of accuracy constrained parameters according to setting decompose check to the figure decomposable process; The figure degree of accuracy constrained parameters of setting are: gate features dimensional discrepancy ± 2nm; Interconnection layer characteristic dimension deviation ± 5nm, line end retraction deviation-5 ~+10nm, mask error enhancer MEEF < 4.The pattern line profile that obtains after the check is shown in Fig. 3 B; Wherein figure (a) is (imaging focal length focus ± 75nm under the certain process tolerance; Illumination dose dose ± 4%) carries out the pattern line profile that optical rules inspection (ORC) obtains; The lines form is well controlled, and characteristic dimension deviation and line end retraction deviation all satisfy the requirement of the figure degree of accuracy of setting; Figure (b) carries out the pattern line profile that mask error enhancer (MEEF) check obtains, and MEEF satisfies the requirement of the constrained parameters of setting; Figure (c) is based on alignment precision (overlay) analysis that negative focussing plane (negative focus) and excessive illumination (over dose) are carried out, and the phenomenon that attenuates or rupture does not appear in pattern line.
According to the method that the combination minimum pitch and the minimum spacing criterion of the present invention's proposition are decomposed the original layout design figure, the lines of figure 101 are not cut among the embodiment; Having cutting among the embodiment between the lines 1 of figure 102 and the lines 2, simultaneously for other embodiment, is necessary to the polygon cutting of the complicated form such as lines 3.There is the very little gap of spacing between the pattern line after decompose; Cause the DPT form variation of gained pattern line afterwards, the present invention is directed to cutting lines polygon and propose following governing principle: cleavage is preferentially chosen the position between the extension of pattern line, narrow/wide line intersection or narrow line and ground connection pressure welding; The junction is fully overlapping when cleavage is reserved crossover region assurance figure joint; Avoid producing short and small fault block and turning line end after the cutting.
As shown in Figure 4, be to implement the process flow diagram that the original layout design figure decomposes according to the method that the present invention proposes, be used to schematically illustrate the flow process of entire method.
In step 401,, establish optimum optical near-correction model, lithographic object, auxiliary figure with low resolution parameter according to the design configuration of original layout;
In step 402, decompose the design configuration of original layout based on minimum pitch and minimum spacing criterion;
In step 403, the mask pattern that decomposition obtains is placed auxiliary figure with low resolution and applied optics near-correction;
In step 404, carry out the optical rules inspection, carry out the check of mask error enhancer simultaneously;
In step 405, aforementioned assay is estimated.
The present invention is illustrated through the foregoing description, but should be understood that, the foregoing description just is used for for example and illustrative purposes, but not is intended to the present invention is limited in the described scope of embodiments.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to the foregoing description, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by appended claims book and equivalent scope thereof.
Claims (13)
1. one kind is used for the method that integrated circuit manufacturing is improved photoetching, it is characterized in that, comprising:
According to the design configuration of original layout, establish optimum optical near-correction model, lithographic object, auxiliary figure with low resolution parameter;
Decompose the design configuration of said original layout based on minimum pitch and minimum spacing criterion;
Mask pattern to decomposition obtains is placed auxiliary figure with low resolution and applied optics near-correction;
The check of mask error enhancer is carried out in the inspection of operation optical rules simultaneously under the certain process tolerance;
Aforementioned assay is estimated.
2. method according to claim 1 is characterized in that, said minimum pitch is the minimum value of spacing sum between lines live width and the lines of the original layout design figure of actual process decision under the manufacturing process node.
3. method according to claim 1 is characterized in that, said minimum spacing is the minimum value of spacing between the lines line end of the original layout design figure of actual process decision under the manufacturing process node.
4. method according to claim 1 is characterized in that said minimum spacing is set at 1/2nd of said minimum pitch.
5. method according to claim 1 is characterized in that, the spacing of decomposing the mask pattern lines line end that obtains is greater than said minimum spacing.
6. method according to claim 1 is characterized in that, the said step that aforementioned assay is estimated comprises: if the gained figure meets the figure degree of accuracy constrained parameters of setting after the double-pattern technical finesse, then carry out the manufacturing of mask.
7. method according to claim 1; It is characterized in that; The said step that aforementioned assay is estimated comprises: if the gained figure does not meet the figure degree of accuracy constrained parameters of setting after the double-pattern technical finesse; Then optimize minimum pitch and minimum spacing decomposition criteria, decompose the design configuration of said original layout again.
8. method according to claim 1; It is characterized in that; The said step that aforementioned assay is estimated comprises: if the gained figure does not meet the figure degree of accuracy constrained parameters of setting after the double-pattern technical finesse, then design the design configuration of said original layout again.
9. according to claim 6,7 or 8 described methods, it is characterized in that the figure degree of accuracy constrained parameters that set comprise characteristic dimension deviation, line end retraction deviation or MEEF allowed band.
10. method according to claim 1 is characterized in that said decomposition figure comprises the cutting of pattern line.
11. method according to claim 10 is characterized in that, cleavage is preferentially chosen the position between the extension of pattern line, narrow/wide line intersection or narrow line and ground connection pressure welding.
12. method according to claim 10 is characterized in that, the junction is fully overlapping when cleavage is reserved crossover region assurance figure joint.
13. method according to claim 1 is characterized in that, said certain process tolerance comprises imaging focal length and illumination dose.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103869598A (en) * | 2014-03-24 | 2014-06-18 | 上海华力微电子有限公司 | Optical proximity effect correction method for ion injection layer |
| CN103984200A (en) * | 2014-05-20 | 2014-08-13 | 上海华力微电子有限公司 | Design method of auxiliary graph as well as production method and photoetching method of test map |
| CN104346490A (en) * | 2013-08-09 | 2015-02-11 | 复旦大学 | Graph pattern decomposition method adopting triple patterning photoetching technology |
| CN104749872A (en) * | 2013-12-27 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Method for forming mask template graph |
| CN104820766A (en) * | 2015-05-27 | 2015-08-05 | 中国科学院微电子研究所 | Double layout design method and system |
| CN107065430A (en) * | 2017-03-10 | 2017-08-18 | 上海集成电路研发中心有限公司 | A kind of rule-based Sub-resolution assist features adding method |
| WO2020154979A1 (en) * | 2019-01-30 | 2020-08-06 | 深圳晶源信息技术有限公司 | Photolithography mask optimization method and apparatus for pattern and image joint optimization, and electronic device |
| CN112542375A (en) * | 2020-12-01 | 2021-03-23 | 泉芯集成电路制造(济南)有限公司 | Method and device for improving line width uniformity of photomask graph |
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Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104346490A (en) * | 2013-08-09 | 2015-02-11 | 复旦大学 | Graph pattern decomposition method adopting triple patterning photoetching technology |
| CN104749872B (en) * | 2013-12-27 | 2019-07-02 | 中芯国际集成电路制造(上海)有限公司 | The method for forming mask plate figure |
| CN104749872A (en) * | 2013-12-27 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Method for forming mask template graph |
| CN103869598A (en) * | 2014-03-24 | 2014-06-18 | 上海华力微电子有限公司 | Optical proximity effect correction method for ion injection layer |
| CN103869598B (en) * | 2014-03-24 | 2017-05-10 | 上海华力微电子有限公司 | Optical proximity effect correction method for ion injection layer |
| CN103984200A (en) * | 2014-05-20 | 2014-08-13 | 上海华力微电子有限公司 | Design method of auxiliary graph as well as production method and photoetching method of test map |
| CN103984200B (en) * | 2014-05-20 | 2017-07-25 | 上海华力微电子有限公司 | The design method of secondary graphics, the preparation method for testing domain, photolithography method |
| CN104820766B (en) * | 2015-05-27 | 2017-08-25 | 中国科学院微电子研究所 | A kind of design method and system of dual domain |
| CN104820766A (en) * | 2015-05-27 | 2015-08-05 | 中国科学院微电子研究所 | Double layout design method and system |
| CN107065430A (en) * | 2017-03-10 | 2017-08-18 | 上海集成电路研发中心有限公司 | A kind of rule-based Sub-resolution assist features adding method |
| WO2020154979A1 (en) * | 2019-01-30 | 2020-08-06 | 深圳晶源信息技术有限公司 | Photolithography mask optimization method and apparatus for pattern and image joint optimization, and electronic device |
| CN111507059A (en) * | 2019-01-30 | 2020-08-07 | 深圳晶源信息技术有限公司 | Photoetching mask optimization method and device for joint optimization of graphic images and electronic equipment |
| US11281839B2 (en) | 2019-01-30 | 2022-03-22 | Shenzhen Jingyuan Information Technology Co., Ltd | Method, apparatus and electronic device for photolithographic mask optimization of joint optimization of pattern and image |
| CN111507059B (en) * | 2019-01-30 | 2023-09-19 | 深圳晶源信息技术有限公司 | Graphic and image joint optimization photoetching mask optimization method and device and electronic equipment |
| CN112542375A (en) * | 2020-12-01 | 2021-03-23 | 泉芯集成电路制造(济南)有限公司 | Method and device for improving line width uniformity of photomask graph |
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