CN102754186B - 利用多个曝光和阻挡掩模方式减少设计规则违反的半导体器件制造 - Google Patents

利用多个曝光和阻挡掩模方式减少设计规则违反的半导体器件制造 Download PDF

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Publication number
CN102754186B
CN102754186B CN201080050771.1A CN201080050771A CN102754186B CN 102754186 B CN102754186 B CN 102754186B CN 201080050771 A CN201080050771 A CN 201080050771A CN 102754186 B CN102754186 B CN 102754186B
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China
Prior art keywords
pattern
photoresist
mask
semiconductor device
pin
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CN201080050771.1A
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English (en)
Chinese (zh)
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CN102754186A (zh
Inventor
理查德·舒尔茨
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H10P76/2041—Photolithographic processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/0698—Local interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning

Landscapes

  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Semiconductor Memories (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Electron Beam Exposure (AREA)
CN201080050771.1A 2009-11-12 2010-11-09 利用多个曝光和阻挡掩模方式减少设计规则违反的半导体器件制造 Active CN102754186B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/617,429 2009-11-12
US12/617,429 US8304172B2 (en) 2009-11-12 2009-11-12 Semiconductor device fabrication using a multiple exposure and block mask approach to reduce design rule violations
PCT/US2010/055977 WO2011059961A2 (en) 2009-11-12 2010-11-09 Semiconductor device fabrication using a multiple exposure and block mask approach to reduce design rule violations

Publications (2)

Publication Number Publication Date
CN102754186A CN102754186A (zh) 2012-10-24
CN102754186B true CN102754186B (zh) 2016-04-13

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN201080050771.1A Active CN102754186B (zh) 2009-11-12 2010-11-09 利用多个曝光和阻挡掩模方式减少设计规则违反的半导体器件制造

Country Status (6)

Country Link
US (1) US8304172B2 (https=)
EP (1) EP2499660B1 (https=)
JP (1) JP5493009B2 (https=)
KR (1) KR101551416B1 (https=)
CN (1) CN102754186B (https=)
WO (1) WO2011059961A2 (https=)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8739095B2 (en) * 2010-03-08 2014-05-27 Cadence Design Systems, Inc. Method, system, and program product for interactive checking for double pattern lithography violations
KR101948222B1 (ko) * 2012-06-15 2019-02-14 에스케이하이닉스 주식회사 홀 패터닝을 위한 마스크패턴 및 그를 이용한 반도체장치 제조 방법
US10283437B2 (en) * 2012-11-27 2019-05-07 Advanced Micro Devices, Inc. Metal density distribution for double pattern lithography
US9236300B2 (en) * 2012-11-30 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Contact plugs in SRAM cells and the method of forming the same
JP6437452B2 (ja) 2013-01-14 2018-12-12 インサイト・ホールディングス・コーポレイションＩｎｃｙｔｅ Ｈｏｌｄｉｎｇｓ Ｃｏｒｐｏｒａｔｉｏｎ Ｐｉｍキナーゼ阻害剤として有用な二環式芳香族カルボキサミド化合物
US8910090B2 (en) * 2013-02-27 2014-12-09 Globalfoundries Inc. Methods involving pattern matching to identify and resolve potential non-double-patterning-compliant patterns in double patterning applications
CN105830211A (zh) * 2013-12-17 2016-08-03 德克萨斯仪器股份有限公司 使用光刻-冷冻-光刻-蚀刻工艺的细长接触件
US9472653B2 (en) * 2014-11-26 2016-10-18 Samsung Electronics Co., Ltd. Method for fabricating semiconductor device
US10430544B2 (en) * 2016-09-02 2019-10-01 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-patterning graph reduction and checking flow method
US11764062B2 (en) * 2017-11-13 2023-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor structure
US12400871B2 (en) * 2020-02-20 2025-08-26 International Business Machines Corporation Metal lines with low via-to-via spacing
CN116819906B (zh) * 2023-08-25 2023-11-28 深圳国微福芯技术有限公司 设计规则检查方法、光学临近修正方法
CN117153677B (zh) * 2023-10-27 2024-03-01 合肥晶合集成电路股份有限公司 一种半导体结构的制造方法

Family Cites Families (14)

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Publication number Priority date Publication date Assignee Title
US6204187B1 (en) * 1999-01-06 2001-03-20 Infineon Technologies North America, Corp. Contact and deep trench patterning
TW436933B (en) * 1999-12-30 2001-05-28 Taiwan Semiconductor Mfg Method for defining a pattern
JP2002182363A (ja) * 2000-12-12 2002-06-26 Matsushita Electric Ind Co Ltd マスク及びパターン形成方法
JP2004247606A (ja) * 2003-02-14 2004-09-02 Fujitsu Ltd フォトマスク、半導体装置及びその製造方法
JP2005259991A (ja) * 2004-03-11 2005-09-22 Sony Corp パターン形成方法
JP2006294942A (ja) * 2005-04-12 2006-10-26 Toshiba Corp 半導体装置およびその製造方法
KR100642886B1 (ko) * 2005-06-27 2006-11-03 주식회사 하이닉스반도체 반도체 소자의 미세패턴 형성방법
US20070231748A1 (en) 2006-03-29 2007-10-04 Swaminathan Sivakumar Patterning trenches in a photoresist layer with tight end-to-end separation
US20070231743A1 (en) 2006-03-31 2007-10-04 Richard Selinfreund Optical media device with minipulatable read capability
JP2008153373A (ja) * 2006-12-15 2008-07-03 Toshiba Corp 半導体装置の製造方法
US7759235B2 (en) * 2007-06-07 2010-07-20 Infineon Technologies Ag Semiconductor device manufacturing methods
KR20090050699A (ko) * 2007-11-16 2009-05-20 주식회사 동부하이텍 미세 패턴 제조 방법 및 반도체 소자의 제조 방법
KR100944348B1 (ko) * 2008-05-16 2010-03-02 주식회사 하이닉스반도체 반도체 소자의 형성 방법
JP5319247B2 (ja) * 2008-11-14 2013-10-16 株式会社東芝 半導体装置の製造方法

Also Published As

Publication number Publication date
EP2499660B1 (en) 2019-10-02
WO2011059961A2 (en) 2011-05-19
KR20120099428A (ko) 2012-09-10
US8304172B2 (en) 2012-11-06
EP2499660A2 (en) 2012-09-19
US20110111348A1 (en) 2011-05-12
KR101551416B1 (ko) 2015-09-08
WO2011059961A3 (en) 2012-04-05
CN102754186A (zh) 2012-10-24
JP5493009B2 (ja) 2014-05-14
JP2013511153A (ja) 2013-03-28

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