CN102739177A - Self-test digital AGC (automatic gain control) method and circuit - Google Patents
Self-test digital AGC (automatic gain control) method and circuit Download PDFInfo
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- CN102739177A CN102739177A CN2012102467565A CN201210246756A CN102739177A CN 102739177 A CN102739177 A CN 102739177A CN 2012102467565 A CN2012102467565 A CN 2012102467565A CN 201210246756 A CN201210246756 A CN 201210246756A CN 102739177 A CN102739177 A CN 102739177A
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Abstract
The invention discloses a self-test digital AGC (automatic gain control) method and a circuit. The self-test digital automatic gain control method comprises the following steps of: generating pulse after enabling an AGC input signal to pass through a delay unit circuit and a pulse generation circuit, triggering the corresponding register through the pulses to sample the AGC input signal; gradually delaying the AGC input signal to obtain corresponding pulse signals; controlling a gain calculation process by utilizing a main clock to generate a control circuit and feeding back AGC output signal to a VGA (variable gain amplifier) circuit. The circuit comprises a delay unit circuit, a pulse generation circuit, a register circuit and a control circuit, wherein the register circuit consists of a first register, a combined logic unit and a second register, and the AGC input signal passes through the delay unit circuit and the pulse generation circuit to generate the pulse for triggering and sampling. According to the self-test digital AGC method and the circuit disclosed by the invention, the amplitude of the AGC input signal can be quickly calculated and is quickly fed back to the VGA circuit, the dependency on the frequency of a clock signal is largely reduced and the like.
Description
Technical field
The present invention relates to a kind of automatic gain control (automatic gain control is called for short AGC) method and circuit, particularly a kind of from detecting digital auto gain control method and circuit.
Background technology
Automatic gain control (AGC) circuit is a functional unit indispensable in the wireless communication system, and its effect is that amplitude adjusted with input signal is in the accommodation of late-class circuit.As shown in Figure 1, the digital AGC circuit usually with variable gain amplifier (variable gain amplifier is called for short VGA) circuit, an A-D converter (Analog-to-Digital Converter is called for short ADC) circuit composition cyclic system.The function of digital AGC circuit is to calculate the AGC input signal amplitude of (signal of ADC output just is called for short MAG or MAG signal), and compares with the amplitude window of prior setting, thereby output feedback signal is given VGA.
Traditional digital AGC circuit implementation is the clock signal through being several times as much as the MAG signal (being called for short CLK) sample (be like the CLK frequency MAG frequency about 4 times) often; Thereby in a period of time (like 512 clock cycle) obtain the clock periodicity M that the MAG signal is in high level; To go out the amplitude of MAG signal be M/512 in approximate calculation so, is limited by the CLK frequency so find out the digital AGC circuit easily; It is longer that another defective is that traditional realization method reaches signal stabilization time.
Summary of the invention
The objective of the invention is to realize calculating fast the amplitude of AGC input signal, and realize gain controlling, thereby reach feedback fast and make VGA finally be stable at the effect of desired value, to overcome the deficiency of prior art in the background technology through the digital AGC circuit.
In order to realize goal of the invention of the present invention, realize through adopting following technical scheme:
A kind of from detecting digital auto gain control method, may further comprise the steps:
The first step is passed through delay unit circuit and pulse generation circuit production burst CLK_1 ﹑ CLK_2 ﹑ with the AGC input signal ... CLK_N, through these pulses go to trigger corresponding register Re_1, Re_2 ... The Re_N AGC input signal of sampling; If the analogue signal amplitude of input is less than reference level, the AGC input signal is a low level always, does not promptly have pulse to generate, and so corresponding trigger is output as 0;
In second step, the delay step by step through to the AGC input signal obtains corresponding pulse signal, postpones the structures shape by delay unit circuit;
In the 3rd step, the computational process with the master clock ride gain generates control circuit, to VGA circuit feedback AGC output signal.
Especially; Described delay cell and pulse generation unit mainly are to be made up of numeric door, and need satisfied concern n * d≤Ratio * T, and wherein n is the number of delay cell and pulse generation unit; D is the transmission delay of delay cell; T is the cycle of AGC input signal, and Ratio accounts for the percentage of signal period for the high level pulsewidth, wherein 0＜Ratio≤1.
Especially, be provided with window in the digital AGC circuit, wherein window is provided with high value of window and window low value, and when the N value was worth greater than window is high, digital AGC circuit feedback reduced AGC output signal, and VGA output is progressively reduced; When N value during less than the window low value, digital AGC circuit feedback increases AGC output signal, and VGA output is progressively increased; When the N value fell between, digital AGC circuit feedback kept AGC output signal, made VGA output signal keep stable.
A kind of from detecting the digital Auto Gain control circuit; Comprise delay unit circuit, pulse generation circuit, register circuit, control circuit; Wherein register circuit is made up of register one, combinatorial logic unit, register two; The Q end of register one and the D end of register two are connected through combinatorial logic unit, and the Q end of register two is connected to control circuit; AGC input signal one tunnel connects the D end of register one; Another road of AGC input signal is through delay unit circuit and pulse generation circuit production burst; Remove to trigger the corresponding register one AGC input signal of sampling through these pulses; Be transferred to register two through combinatorial logic unit; While master clock signal trigger register two, the signal of gained register two is transferred to control circuit, again by control circuit output AGC output signal.
Especially; Said delay unit circuit is made up of N delay cell; Said pulse generation circuit by N pulse generation unit form, said register circuit is made up of N group register one, combinatorial logic unit, register two; The AGC input signal is through delay unit circuit and pulse generation circuit production burst CLK_1 ﹑ CLK_2 ﹑ ... CLK_N; Through these pulses go to trigger corresponding register one Re1_1, Re1_2 ... The Re1_N AGC input signal of sampling; Through combinatorial logic unit be transferred to corresponding register two Re2_1, Re2_2 ... Re2_N, simultaneously master clock signal trigger register two Re2_1, Re2_2 ... Re2_N, the signal of gained register two is transferred to control circuit.
Especially, said delay unit circuit is made up of the clocked inverter series connection.
Beneficial effect of the present invention is:
The first, can calculate the amplitude of AGC input signal fast, and feed back to the VGA circuit fast.Sampling clock with the AGC input signal of the AGC input signal of 10M (clock cycle is 100ns) and 40M (clock cycle is 25ns) is explained; The range value that traditional implementation method is calculated an AGC input signal need 12.8us (with 512 clock cycle be a sampling period); But use method of the present invention; 50ns (being 0.05us) just can calculate the range value of AGC input signal; That is to say that finally reaching the AGC input signal stablizes the needed time and have only 1us or several us, and this signal amplitude in conventional method is not calculated all.
The second, the dependence to clock signal frequency reduces greatly, method of the present invention show if clock frequency be not more than 2 times of frequency analog signal can;
Three, also can calculate the range value of AGC input signal more accurately through method of the present invention, even duty ratio;
Four, can revise corresponding delay circuit according to signal frequency, have stronger flexibility;
Five, can adopt a kind of delay to the signal value in certain frequency range, have certain versatility, all adopt the delay of 1ns such as the following signal of 10M.
Description of drawings
Fig. 1 is prior art and the cyclic system structural representation that the present invention is based on;
Fig. 2 is the digital Auto Gain control circuit structural representation that the present invention relates to;
Fig. 3 is the waveform sketch map of impulse sampling ADC output signal in the digital Auto Gain control circuit that the present invention relates to.
Wherein, the symbol description of Fig. 1 to Fig. 3 is following:
1, VGA circuit, 2, adc circuit, 3, the digital AGC circuit, 31, combinatorial logic unit, 32, control circuit; 41, the delay between adjacent two pulses; MAG, AGC input signal, AGC_OUT [4:0], AGC export signal, Main_CLK, master clock signal, R_High, the high value of window; R_Low, window low value, DL, delay cell, PL, pulse generation unit, Re1, register one; Re2, register two, CLK_, pulse, CLK, clock signal; M, clock periodicity, AS, analog signal, Ref, reference level.
Embodiment
Like Fig. 1, Fig. 2, shown in Figure 3, the waveform sketch map of impulse sampling ADC output signal in the digital Auto Gain control circuit that be respectively the cyclic system structural representation that the present invention is based on, the digital Auto Gain control circuit structural representation that relates to, relates to.
As shown in Figure 1, at first analog signal AS converts digital signal AGC input signal MAG to by adc circuit 2 through VGA circuit 1, calculates the amplitude of AGC input signal MAG again through digital AGC circuit 3, and finally feeds back to VGA circuit 1 and come the amplitude of accommodation.
A kind of from detecting digital auto gain control method, may further comprise the steps:
The first step is passed through delay unit circuit and pulse generation circuit production burst CLK_1 ﹑ CLK_2 ﹑ with AGC input signal MAG ... CLK_N, through these pulses go to trigger corresponding register Re_1, Re_2 ... The Re_N AGC input signal MAG that samples; If the analog signal AS amplitude of input is less than reference level Ref, AGC input signal MAG is a low level always, does not promptly have pulse to generate, and so corresponding trigger is output as 0; Just in this case, digital AGC circuit 3 value that feeds back to VGA circuit 1 is similar to the very little situation of AGC input signal MAG amplitude.
In second step, the delay step by step through to AGC input signal MAG obtains corresponding pulse signal, postpones the structures shape by delay unit circuit;
The 3rd step with the computational process of master clock signal Main_CLK ride gain, generated control circuit 32, to VGA circuit 1 feedback AGC output signal AGC_OUT [4:0].Method for designing through cross clock domain; Computational process with master clock signal Main_CLK ride gain; AGC input signal MAG is smaller to the dependence of clock frequency like this, and in the present invention, clock frequency is the same with the MAG frequency or can operate as normal less than the MAG frequency; If clock frequency is higher than the MAG frequency, then can utilize conventional means that clock is carried out frequency division.
Described delay cell DL and pulse generation unit PL are made up of numeric door; And need to satisfy and concern n * d≤Ratio * T; Wherein n is the number of delay cell DL and pulse generation unit PL, and d is the transmission delay of delay cell DL, and T is the cycle of AGC input signal MAG; Ratio accounts for the percentage of signal period for the high level pulsewidth, wherein 0＜Ratio≤1.
For example the analog signal AS frequency of input is 10M, and the frequency of AGC input signal MAG is 20M so, and its cycle is T=50ns; The propagation delay time d=1ns of delay cell DL; Suppose Ratio=0.6, n=30 (50*0.6/1) that is to say 30 DL of needs and PL so; Explain simultaneously a MAG cycle detection to the pulsewidth of high level and if the high level pulsewidth surpasses 30ns, can think that the amplitude of this signal is very big 0 to 30ns.
According to top method; If N-1 pulse detection is high level to AGC input signal MAG; If N pulse detection is low level to AGC input signal MAG; Can calculate that so a MAG cycle (50ns) high level pulsewidth is N-1 ns, the input value that is to say control circuit 32 is N-1.
Be provided with window in the control circuit 32 in the digital AGC circuit 3; Wherein window is provided with high value R_High of window and window low value R_Low; When the input value N of control circuit is worth R_High greater than window is high; Digital AGC circuit 3 feedbacks reduce signal, and just the value of AGC output signal AGC_OUT [4:0] is reducing, thereby VGA output is progressively reduced; When N value during less than window low value R_Low, digital AGC circuit 3 feedbacks increase signals, and just the value of AGC output signal AGC_OUT [4:0] is increasing, thereby VGA output is progressively increased; When the N value falls between, digital AGC circuit 3 feedback inhibit signals, i.e. AGC output signal AGC_OUT [4:0] value remains unchanged, and finally makes VGA output signal keep stable.
A kind of from detecting the digital Auto Gain control circuit; Comprise delay unit circuit, pulse generation circuit, register circuit, control circuit 32; Wherein register circuit is made up of register one Re1, combinatorial logic unit 31, register two Re2; The Q end of register one Re1 and the D end of register two Re2 are connected through combinatorial logic unit 31, and the Q end of register two Re2 is connected to control circuit 32; AGC input signal MAG one tunnel connects the D end of register one Re1; Another road of AGC input signal MAG is through delay unit circuit and pulse generation circuit production burst CLK_; Remove to trigger the corresponding register one Re1 AGC input signal MAG that samples through these pulses CLK_; Be transferred to register two Re2 through combinatorial logic unit 31; While master clock signal Main_CLK trigger register two Re2, the signal of gained register two Re2 is transferred to control circuit 32, again by control circuit 32 output AGC output signal AGC_OUT [4:0].
Said delay unit circuit is made up of N delay cell DL; Said pulse generation circuit by N pulse generation unit PL form, said register circuit is made up of N group register one Re1, combinatorial logic unit 31, register two Re2; AGC input signal MAG is through delay unit circuit and pulse generation circuit production burst CLK_1 ﹑ CLK_2 ﹑ ... CLK_N; Through these pulses CLK_1 ﹑ CLK_2 ﹑ ... CLK_N go to trigger corresponding register one Re1_1, Re1_2 ... The Re1_N AGC input signal MAG that samples; Through combinatorial logic unit 31 be transferred to corresponding register two Re2_1, Re2_2 ... Re2_N; Simultaneously master clock signal Main_CLK trigger register two Re2_1, Re2_2 ... Re2_N, the signal of gained register two is transferred to control circuit 32.
Said delay unit circuit is made up of the clocked inverter series connection.Because these clocked inverters are to PVT (Process ﹑ Voltage ﹑ Temperature; Established technology, voltage, temperature) influence is not too responsive; The transition time (being bound-time) is balance relatively; And their driving force is stronger, usually in the digital circuit they all to be used for clock trees comprehensive.
Above delay unit circuit be based under the situation that digital AGC circuit 3 works in representative condition (Typical); If cause digital AGC circuit 3 to work under the situation of the poorest condition (worst case) because extraneous PVT changes; The delay of circuit has some increases so, but not too large for the medium and low frequency effect of signals.The analog signal AS of 10M for example; The cycle of MAG is 50ns; The window that we select is 10～20, that is to say if digital AGC circuit 3 works in when delay circuit is 1ns under the situation of Typical, and AGC input signal MAG high level is kept the stable time should (time be 10～20ns) 20%～40%; Under the worst case situation is 1.5ns, and AGC input signal MAG high level is kept the stable time should (time be 20～30ns) 30%～60%.
In addition; From the angle that circuit is realized,, utilize the modular design flow process of digital integrated circuit through above preparation; Very short from the comprehensive cycle that laying out pattern connects up to the rear end of front end verilog code; Be easy to realize that because the scale of this circuit is smaller, the main flow eda tool is easy to reach designing requirement.
Claims (6)
1. one kind is detected digital auto gain control method certainly, it is characterized in that: may further comprise the steps:
The first step; AGC input signal (MAG) is passed through delay unit circuit and pulse generation circuit production burst CLK_1 ﹑ CLK_2 ﹑ ... CLK_N, through these pulses go to trigger corresponding register Re_1, Re_2 ... The Re_N AGC input signal (MAG) of sampling; If analog signal (AS) amplitude of input is less than reference level (Ref), AGC input signal (MAG) is a low level always, does not promptly have pulse to generate, and so corresponding trigger is output as 0;
In second step, the delay step by step through to AGC input signal (MAG) obtains corresponding pulse signal, postpones the structures shape by delay unit circuit;
The 3rd step with the computational process of master clock signal (Main_CLK) ride gain, generated control circuit (32), to VGA circuit (1) feedback AGC output signal (AGC_OUT [4:0]).
2. as claimed in claim 1 from detecting digital auto gain control method; It is characterized in that: described delay cell (DL) and pulse generation unit (PL) mainly are to be made up of numeric door; And need to satisfy and concern n * d≤Ratio * T; Wherein n is the number of delay cell (DL) and pulse generation unit (PL), and d is the transmission delay of delay cell (DL), and T is the cycle of AGC input signal (MAG); Ratio accounts for the percentage of signal period for the high level pulsewidth, wherein 0＜Ratio≤1.
3. as claimed in claim 1 from detecting digital auto gain control method; It is characterized in that: the digital AGC circuit is provided with window in (3); Wherein window is provided with high value (R_High) of window and window low value (R_Low); When the N value was worth (R_High) greater than window is high, digital AGC circuit (3) feedback reduced AGC output signal (AGC_OUT [4:0]), and VGA output is progressively reduced; When N value during less than window low value (R_Low), digital AGC circuit (3) feedback increases AGC output signal (AGC_OUT [4:0]), and VGA output is progressively increased; When the N value fell between, digital AGC circuit (3) feedback kept AGC output signal (AGC_OUT [4:0]), made VGA output signal keep stable.
4. one kind is detected the digital Auto Gain control circuit certainly; It is characterized in that: comprise delay unit circuit, pulse generation circuit, register circuit, control circuit (32); Wherein register circuit is made up of register one (Re1), combinatorial logic unit (31), register two (Re2); The Q end of register one (Re1) and the D end of register two (Re2) are connected through combinatorial logic unit (31), and the Q end of register two (Re2) is connected to control circuit (32); AGC input signal (MAG) one tunnel connects the D end of register one (Re1); Another road of AGC input signal (MAG) is through delay unit circuit and pulse generation circuit production burst (CLK_); Remove to trigger corresponding register one (Re1) the AGC input signal (MAG) of sampling through these pulses (CLK_); Be transferred to register two (Re2) through combinatorial logic unit (31); While master clock signal (Main_CLK) trigger register two (Re2); The signal of gained register two (Re2) is transferred to control circuit (32), again by control circuit (32) output AGC output signal (AGC_OUT [4:0]).
5. as claimed in claim 4 from detecting the digital Auto Gain control circuit; It is characterized in that: said delay unit circuit is made up of N delay cell (DL); Said pulse generation circuit by N pulse generation unit (PL) form, said register circuit is made up of N group register one (Re1), combinatorial logic unit (31), register two (Re2); AGC input signal (MAG) is through delay unit circuit and pulse generation circuit production burst CLK_1 ﹑ CLK_2 ﹑ ... CLK_N; Through these pulses CLK_1 ﹑ CLK_2 ﹑ ... CLK_N go to trigger corresponding register one Re1_1, Re1_2 ... The Re1_N AGC input signal (MAG) of sampling; Through combinatorial logic unit (31) be transferred to corresponding register two Re2_1, Re2_2 ... Re2_N; Simultaneously master clock signal (Main_CLK) trigger register two Re2_1, Re2_2 ... Re2_N, the signal of gained register two are transferred to control circuit (32).
6. like claim 4 or 5 described from detecting the digital Auto Gain control circuit, it is characterized in that: said delay unit circuit is made up of the clocked inverter series connection.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108845312A (en) * | 2018-06-04 | 2018-11-20 | 陕西长岭电子科技有限责任公司 | The high method of survey based on pulse regime radio altimeter |
| CN111130477A (en) * | 2019-12-06 | 2020-05-08 | 上海交通大学 | Level trigger type automatic regulating gain amplifying circuit |
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| CN202663363U (en) * | 2012-07-17 | 2013-01-09 | 中科芯集成电路股份有限公司 | Self-test automatic digital gain control circuit |
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| CN1725633A (en) * | 2004-07-23 | 2006-01-25 | 三洋电机株式会社 | Automatic level control circuit with improved recovery action |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108845312A (en) * | 2018-06-04 | 2018-11-20 | 陕西长岭电子科技有限责任公司 | The high method of survey based on pulse regime radio altimeter |
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| CN111130477A (en) * | 2019-12-06 | 2020-05-08 | 上海交通大学 | Level trigger type automatic regulating gain amplifying circuit |
| CN111130477B (en) * | 2019-12-06 | 2023-04-25 | 上海交通大学 | Level-triggered automatic gain-adjusting amplifying circuit |
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Application publication date: 20121017 |