CN102694542A - Method, device and chip for isolating signal - Google Patents
Method, device and chip for isolating signal Download PDFInfo
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- CN102694542A CN102694542A CN2012101416509A CN201210141650A CN102694542A CN 102694542 A CN102694542 A CN 102694542A CN 2012101416509 A CN2012101416509 A CN 2012101416509A CN 201210141650 A CN201210141650 A CN 201210141650A CN 102694542 A CN102694542 A CN 102694542A
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Abstract
The embodiment of the invention discloses a method, a device and a chip for isolating a signal. The method comprises the steps of: detecting a voltage of a main power supply supplying power for a main power supply domain, and generating a reset signal when it is detected that the voltage of the main power supply is in a predetermined voltage band; generating a first level signal according to the reset signal; controlling an isolation device according to the first level signal to isolate a signal of the main power supply domain, thereby preventing the signal of the main power supply domain from entering a spare power supply domain. According to the technical scheme of the invention, power down of a main power supply can be discovered in time, and an isolation device is controlled to isolate a signal of the main power supply domain, thereby preventing the signal of the main power supply domain from entering a spare power supply domain, and avoiding influence on a signal of the spare power supply domain.
Description
Technical field
The present invention relates to the chip design art field, relate in particular to signal isolation method, device and chip.
Background technology
When carrying out chip design, adopt the multi-power domain design usually, so that realize specific circuit function, for example; In the SOC(system on a chip) of safety chip (SoC, System on Chip) two power domain can be set, wherein the power domain by the main power source power supply is called the main power source territory; Generally comprise conventional chip logic, for example, central processing unit (CPU; Central Processing Unit), flash memory (Flash), read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory) etc.; Power domain by the stand-by power supply power supply is called the stand-by power supply territory, generally includes nonvolatile random access memory bank (NVRAM, Non-Volatile Random Access Memory) etc.; Main power source is a power-up state under the normal condition, and stand-by power supply is a power-down state, and when the power down of main power source accident; Stand-by power supply just becomes power-up state, and at this moment stand-by power supply supplies power only for the stand-by power supply territory, thereby after the main power source power down; Can give the NVRAM in the stand-by power supply territory power supply by stand-by power supply, make NVRAM still can keep data, to prolong data hold time.
In the SoC design of above-mentioned safety chip; Though through main power source territory and stand-by power supply territory are set; Can after the main power source power down, give the power supply of stand-by power supply territory by stand-by power supply, but after the main power source power down; The signal in main power source territory still can get into the stand-by power supply territory, thereby the signal in stand-by power supply territory is exerted an influence.
Summary of the invention
Signal isolation method, device and chip are provided in the embodiment of the invention, in order to solve exist in the prior art after the main power source power down, the signal in main power source territory still can get into the stand-by power supply territory, thus the problem that the signal in stand-by power supply territory is exerted an influence.
For addressing the above problem, the technical scheme that the embodiment of the invention provides is following:
A kind of signal isolation method, this method comprises: the main power voltage to for main power source territory power supply detects, and when detecting said main power voltage when being in the predeterminated voltage section, produces reset signal; According to said reset signal, produce first level signal; Control the signal that isolating device is isolated said main power source territory according to said first level signal, so that the signal in said main power source territory can't get into said stand-by power supply territory.
A kind of signal isolating device comprises: voltage detection unit, be used for the main power voltage for main power source territory power supply is detected, and when detecting said main power voltage when being in the predeterminated voltage section, produce reset signal; The first signal generation unit is used for the reset signal according to said voltage detection unit generation, produces first level signal; Isolated location, the signal that first level signal control isolating device that is used for producing according to the said first signal generation unit is isolated said main power source territory is so that the signal in said main power source territory can't get into said stand-by power supply territory.
A kind of chip comprises: voltage detector VD, and said VD detects the main power voltage for main power source territory power supply, when detecting said main power voltage when being in the predeterminated voltage section, produces reset signal; Signal isolation circuit, the output of said VD is connected with the input of said signal isolation circuit, and said signal isolation circuit produces a level signal according to the reset signal that said VD produces; Isolating device; The output of said signal isolation circuit is connected with the Enable Pin of said isolating device; Level signal by said signal isolation circuit produces is directly controlled the signal that isolating device is isolated said main power source territory, so that the signal in said main power source territory can't get into said stand-by power supply territory.
The signal isolation method that embodiment of the invention technical scheme is provided through the main power voltage for the power supply of main power source territory is detected, can in time detect main power voltage and change; And detecting main power voltage when being in the predeterminated voltage section; Produce reset signal,, produce first level signal according to this reset signal; Control the signal that isolating device is isolated said main power source territory according to this first level signal, so that the signal in said main power source territory can't get into said stand-by power supply territory.Therefore; Adopt embodiment of the invention technical scheme; Can be in the predeterminated voltage section through detecting main power voltage, in time find the main power source power down, and the signal in control isolating device isolation main power source territory; Thereby make the signal in main power source territory can't get into the stand-by power supply territory, avoided the signal in stand-by power supply territory is exerted an influence.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art; To do to introduce simply to the accompanying drawing of required use among the embodiment below; Obviously, the accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills; Under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is in the embodiment of the invention one, the signal isolation method schematic flow sheet;
Fig. 2 is in the embodiment of the invention two, signal isolating device first structural representation;
Fig. 3 is in the embodiment of the invention two, isolated location 23 first structural representations;
Fig. 4 is in the embodiment of the invention two, isolated location 23 second structural representations;
Fig. 5 is in the embodiment of the invention two, signal isolating device second structural representation;
Fig. 6 is in the embodiment of the invention three, chip first circuit theory diagrams;
Fig. 7 is in the embodiment of the invention four, chip second circuit schematic diagram;
Fig. 8 is in the embodiment of the invention five, chip tertiary circuit schematic diagram;
Fig. 9 is in the embodiment of the invention five, the sequential chart of main power source, reset signal and isolation signals;
Figure 10 is in the embodiment of the invention six, chip the 4th circuit theory diagrams;
Figure 11 is in the embodiment of the invention, and a kind of whole chip is formed sketch map.
Embodiment
To combine the accompanying drawing in the embodiment of the invention below, the technical scheme in the embodiment of the invention is carried out clear, complete description, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the present invention's protection.
Embodiment one
As shown in Figure 1, be the signal isolation method schematic flow sheet that the embodiment of the invention one proposes, its concrete handling process is following:
Wherein, can detect main power voltage through original voltage detecting (VD, Voltage Detector) module in the chip or electrification reset (PoR, Power on Reset) module.
In the embodiment of the invention one, above-mentioned predeterminated voltage section can be set to a magnitude of voltage in advance, and for example 2.55 volts, also can be set to a voltage range in advance, for example, 2.55～2.15V.
Can bring in through resetting of a basic circuit unit triggers device (flip-flop) and receive above-mentioned reset signal; After the reset terminal of flip-flop receives reset signal; Output by flip-flop produces first level signal, and at this moment, above-mentioned first level signal is a low level signal.
Wherein, Can directly control the signal that isolating device is isolated the main power source territory by above-mentioned first level signal; So that the signal in said main power source territory can't get into said stand-by power supply territory; After also can handling to above-mentioned first level signal, the signal of isolating the main power source territory by the signal controlling isolating device after handling again.
In the embodiment of the invention one, to the processing mode of above-mentioned first level signal can but be not limited to following two kinds:
First kind of processing mode carried out voltage to first level signal and kept handling, and produces second level signal, directly controls the signal that isolating device is isolated the main power source territory by second level signal, so that the signal in main power source territory can't get into the stand-by power supply territory.
Because after the main power source power down is accomplished; First level signal that step 12 produced may change; For example become high-impedance state by low level signal, directly controlling isolating device by above-mentioned first level signal, to isolate the reliability of signal in main power source territory lower, in the embodiment of the invention one; After adopting above-mentioned first kind of processing mode that first level signal is carried out voltage maintenance processing; Can be after the main power source power down to be accomplished, second level signal still keeps stable low level signal, and the reliability of signal of being isolated the main power source territory by this second level signal control isolating device is higher.
Second kind of processing mode; Earlier first level signal being carried out voltage keeps handling; Produce three level signal, then three level signal is carried out voltage stabilizing and handle, produce the 4th level signal; Directly control the signal that isolating device is isolated the main power source territory by the 4th level signal, so that the signal in main power source territory can't get into the stand-by power supply territory.
Owing to adopt first kind of processing mode, first level signal is carried out after voltage keeps handling second level signal that obtains; The situation that still might have voltage instability after making the main power source power down, can produce stable level signal and control isolating device and come into force; Can adopt second kind of processing mode; Owing in second kind of processing mode, not only will carry out voltage to first level signal and keep handling, also will carry out voltage stabilizing to the three level signal that produces and handle; Therefore further strengthened the stability of level signal, higher thereby the 4th level signal control isolating device after being handled by voltage stabilizing is isolated the reliability of signal in main power source territory.
In addition, in order to guarantee after main power source powers on, make the signal in main power source territory get into the stand-by power supply territory; Also to pass through program setting; Power on the back by input signal of CPU generation at main power source, behind the input signal that receives the CPU generation, produce the 5th level signal; According to the bypass of the 5th level signal control isolating device, make the signal in main power source territory can get into the stand-by power supply territory.
Above-mentioned the 5th level signal should be different with the signal condition of first level signal, second level signal, three level signal and the 4th level signal; For example; If first level signal, second level signal, three level signal and the 4th level signal are low level signal, then the 5th level signal can be high level signal.
Can know by above-mentioned processing procedure; Adopt the signal isolation method of the embodiment of the invention one,, can in time detect main power voltage and change through the main power voltage for the power supply of main power source territory is detected; And detecting main power voltage when being in the predeterminated voltage section; Produce reset signal,, produce first level signal according to this reset signal; Control the signal that isolating device is isolated said main power source territory according to this first level signal, so that the signal in said main power source territory can't get into said stand-by power supply territory.Therefore; Adopt the technical scheme of the embodiment of the invention one; Can be in the predeterminated voltage section through detecting main power voltage, in time find the main power source power down, and the signal in control isolating device isolation main power source territory; Thereby make the signal in main power source territory can't get into the stand-by power supply territory, avoided the signal in stand-by power supply territory is exerted an influence.
Embodiment two
Accordingly, the embodiment of the invention two provides a kind of signal isolating device, and its structure is as shown in Figure 2, comprising:
The first signal generation unit 22 is used for the reset signal according to said voltage detection unit 21 generations, produces first level signal;
Isolated location 23 is used for controlling the signal that isolating device is isolated said main power source territory according to first level signal that the said first signal generation unit 22 produces, so that the signal in said main power source territory can't get into said stand-by power supply territory.
Preferably, said isolated location 23 specifically is used for: first level signal by the said first signal generation unit 22 produces is directly controlled the signal that isolating device is isolated said main power source territory, so that the signal in said main power source territory can't get into said stand-by power supply territory.
Preferably, the embodiment of the invention two provides a kind of isolated location 23, and its structure is as shown in Figure 3, and isolated location 23 comprises:
Secondary signal produces subelement 231, is used for that first level signal that the said first signal generation unit 22 produces is carried out voltage and keeps handling, and produces second level signal;
The first separaant unit 232 is used for directly controlling the signal that isolating device is isolated said main power source territory by second level signal that said secondary signal generation subelement 231 produces, so that the signal in said main power source territory can't get into said stand-by power supply territory.
Preferably, the embodiment of the invention two provides another kind of isolated location 23, and its structure is as shown in Figure 4, and isolated location 23 comprises:
The 3rd signal produces subelement 233, is used for that first level signal that the said first signal generation unit 22 produces is carried out voltage and keeps handling, and produces three level signal;
The 4th signal produces subelement 234, is used for that the three level signal that said the 3rd signal generation subelement 233 produces is carried out voltage stabilizing and handles, and produces the 4th level signal;
The second separaant unit 235 is used for directly controlling the signal that isolating device is isolated said main power source territory by the 4th level signal that said the 4th signal generation subelement 234 produces, so that the signal in said main power source territory can't get into said stand-by power supply territory.
Preferably, the embodiment of the invention two provides another kind of signal isolating device, and its structure is as shown in Figure 5, comprising:
The first signal generation unit 52 is used for the reset signal according to said voltage detection unit 51 generations, produces first level signal;
Isolated location 53 is used for controlling the signal that isolating device is isolated said main power source territory according to first level signal that the said first signal generation unit 52 produces, so that the signal in said main power source territory can't get into said stand-by power supply territory;
The 5th signal generation unit 54 is used for behind the input signal that receives the CPU generation, producing the 5th level signal;
The signal isolating device that adopts the embodiment of the invention two to provide; Detect by 21 pairs of main power voltages of voltage detection unit earlier for the power supply of main power source territory; Can in time detect main power voltage and change, and detect main power voltage when being in the predeterminated voltage section, produce reset signal; The reset signal that produces according to voltage detection unit 21 by the first signal generation unit 22 then; Produce first level signal, the signal that first level signal control isolating device that is produced according to the first signal generation unit 22 by isolated location 23 is again isolated said main power source territory is so that the signal in said main power source territory can't get into said stand-by power supply territory.Therefore; Adopt embodiment of the invention technical scheme; Can detect main power voltage through voltage detection unit 21 and be in the predeterminated voltage section, in time find the main power source power down, and control the signal that isolating devices are isolated the main power source territories by isolated location 23; Thereby make the signal in main power source territory can't get into the stand-by power supply territory, avoided the signal in stand-by power supply territory is exerted an influence.
Embodiment three
Accordingly, the embodiment of the invention three provides a kind of chip, and its circuit theory diagrams are as shown in Figure 6, comprising:
VD, said VD detects the main power voltage for main power source territory power supply, when detecting said main power voltage when being in the predeterminated voltage section, produces reset signal;
Signal isolation circuit, the output of said VD is connected with the input of said signal isolation circuit, and said signal isolation circuit produces a level signal according to the reset signal that said VD produces;
Isolating device; The output of said signal isolation circuit is connected with the Enable Pin of said isolating device; Level signal by said signal isolation circuit produces is directly controlled the signal that isolating device is isolated said main power source territory, so that the signal in said main power source territory can't get into said stand-by power supply territory.
After main power source is powered on; The bypass of control isolating device makes the signal in main power source territory get into the stand-by power supply territory, can utilize the CPU that is provided with in advance in the main power source territory; The input of said signal isolation circuit is connected with said cpu bus; After the main power source for the power supply of main power source territory powers on, control said signal isolation circuit by said CPU, produce a level signal; The signal in the said main power source of the level signal control isolating device conducting territory that is produced by said signal isolation circuit makes the signal in said main power source territory get into said stand-by power supply territory.
Wherein, VD also can be substituted by PoR, and main power voltage is detected, and when detecting said main power voltage when being in the predeterminated voltage section, produces reset signal.
Embodiment four
Accordingly; The embodiment of the invention four provides another kind of chip, and its circuit theory diagrams are as shown in Figure 7, and signal isolation circuit comprises: a flip-flop; The output of said VD is connected with the reset terminal of a said flip-flop; A said flip-flop produces a level signal according to the reset signal that said VD produces, and the output of a said flip-flop is connected with the Enable Pin of said isolating device; Level signal by a said flip-flop produces is directly controlled the signal that isolating device is isolated said main power source territory, so that the signal in said main power source territory can't get into said stand-by power supply territory.
Embodiment five
Accordingly; The embodiment of the invention five provides another kind of chip; Its circuit theory diagrams are as shown in Figure 8, and signal isolation circuit comprises: a flip-flop, and the output of said VD is connected with the reset terminal of a said flip-flop; A said flip-flop produces a level signal according to the reset signal that said VD produces; The first bus level holding unit Bushold; The output of a said flip-flop is connected with the input of a said Bushold; The level signal that a said Bushold produces a said flip-flop is carried out voltage and is kept handling; Produce a level signal; The output of a said Bushold is connected with the Enable Pin of said isolating device, directly controls the signal that isolating device is isolated said main power source territory by the level signal that a said Bushold produces, so that the signal in said main power source territory can't get into said stand-by power supply territory.
Wherein, compact in order to make circuit structure, when concrete design chips, can a VD and a flip-flop be placed in the main power source territory, a Bushold is placed in the stand-by power supply territory.
As shown in Figure 9, in the embodiment of the invention five, how the sequential chart of main power source VCC, reset signal and isolation signals realizes that to chip shown in Figure 8 the signal of isolating the main power source territory specifies below in conjunction with this sequential chart.
Under VCC in the electric process; VD driving reset signal is a low level; The level signal that causes a flip-flop becomes low level, and then the level signal upset that drives a Bushold comes into force isolating device for low level; Promptly control isolating device and isolate the signal in main power source territory, so that the signal in main power source territory can't get into the stand-by power supply territory.After the VCC power down was accomplished, the level signal of a flip-flop became high-impedance state, and the level signal of a Bushold can continue to keep low level, and isolating device is come into force.After VCC re-powers; Is high level by program through the input signal that cpu bus is provided with a flip-flop; And then drive the level signal of a flip-flop and the level signal of a Bushold becomes high level; So that the isolating device bypass, even the signal in main power source territory gets into the stand-by power supply territory.
Embodiment six
Accordingly; The embodiment of the invention six provides another chip; Its circuit theory diagrams are shown in figure 10, and signal isolation circuit comprises: a flip-flop, and the output of said VD is connected with the reset terminal of a said flip-flop; A said flip-flop produces a level signal according to the reset signal that said VD produces; The first bus level holding unit Bushold; The output of a said flip-flop is connected with the input of a said Bushold; The level signal that a said Bushold produces a said flip-flop is carried out voltage and is kept handling, and produces a level signal; The 2nd flip-flop, the output of said VD is connected with the reset terminal of said the 2nd flip-flop, and said the 2nd flip-flop produces a level signal after receiving the reset signal of said VD generation; The 2nd Bushold, the output of said the 2nd flip-flop is connected with the input of said the 2nd Bushold, and the level signal that said the 2nd Bushold produces said the 2nd flip-flop is carried out voltage and is kept handling, and produces a level signal; The 3rd flip-flop; The output of a said Bushold is connected with the clock end of said the 3rd flip-flop; The output of said the 2nd Bushold is connected with the reset terminal of said the 3rd flip-flop; The level signal that the level signal that said the 3rd flip-flop produces according to said the 2nd Bushold produces a said Bushold is carried out voltage stabilizing and is handled; Produce a level signal; Said isolating device is connected with the output of said the 3rd flip-flop, directly controls the signal that isolating device is isolated said main power source territory by the level signal that said the 3rd fl ip-flop produces, so that the signal in said main power source territory can't get into said stand-by power supply territory.
Wherein, compact for circuit structure, when concrete design chips, can VD, a flip-flop and the 2nd fl ip-flop be placed in the main power source territory, a Bushold, the 2nd Bushold and the 3rd flip-flop are placed in the stand-by power supply territory.
Adopt the signal isolation circuit of the embodiment of the invention six, the input of the 3rd flip-flop fixedly connects high level.Like this, under the VCC in the electric process, VD produces reset signal and drives the 2nd flip-flop output low level signal, behind the 2nd Bushold output low level signal, drives the 3rd flip-flop output low level signal that resets.Can strengthen the reliability that low level signal is stablized in generation through increasing by the 3rd flip-flop; When electricity under VCC; The equal output low level signal of the one Bushold and the 2nd Bushold when having only the two instability to occur simultaneously, just can interfere with the level signal of the 3rd flip-flop.After electricity finishes under VCC,, can not influence the 3rd flip-flop output low level signal even there is one instability to occur among a Bushold and the 2nd Bushold yet.After VCC re-powered, program was that the input signal of high level and the 2nd flip-flop is a high level through the input signal of setting a flip-flop, can make the 3rd flip-flop output high level signal, made the isolating device bypass.
The signal isolation circuit that the embodiment of the invention proposed based on digital circuit and analog circuit co-design, has simple in structurely, is easy to be integrated into chip, advantage such as technological parameter is insensitive.
Shown in figure 11, in the embodiment of the invention, a kind of whole chip is formed sketch map; Comprise power domain 1 and power domain 2, wherein, power domain 1 is supplied power by main power source VCC; Can be referred to as the main power source territory, power domain 2 can be referred to as the stand-by power supply territory by stand-by power supply VBAT power supply.Main power source comprises CPU in the territory; Can also comprise direct memory access (DMA; Direct Memory Access) memory, Flash, RAM and NVRAM controller etc.; Can comprise low pressure difference linear voltage regulator (LDO, low dropout regulator), control circuit and NVRAM etc. in the stand-by power supply territory.Isolating device is connected between main power source territory and the stand-by power supply territory, the signal that is used to isolate the main power source territory so that the signal in main power source territory can't get into the stand-by power supply territory, can avoid the power down of main power source territory after, the stand-by power supply territory is exerted an influence.The reset terminal of signal isolation circuit is connected with the output of VD, and the output of signal isolation circuit is connected with the Enable Pin of isolating device, and the realization Signal Spacing is used for matching with isolating device.
The chip that the embodiment of the invention provided can be used to the signal isolation method of realizing that the embodiment of the invention provides.
The professional can also further should be able to recognize; The unit and the algorithm steps of each example of describing in conjunction with embodiment disclosed herein; Can realize with electronic hardware, computer software or the combination of the two; For the interchangeability of hardware and software clearly is described, the composition and the step of each example described prevailingly according to function in above-mentioned explanation.These functions still are that software mode is carried out with hardware actually, depend on the application-specific and the design constraint of technical scheme.The professional and technical personnel can use distinct methods to realize described function to each certain applications, but this realization should not thought the scope that exceeds the embodiment of the invention.
The method of describing in conjunction with embodiment disclosed herein or the step of algorithm can be directly with the software modules of hardware, processor execution, and perhaps the combination of the two is implemented.
To the above-mentioned explanation of the disclosed embodiments, make this area professional and technical personnel can realize or use the embodiment of the invention.Multiple modification to these embodiment will be conspicuous concerning those skilled in the art, and defined General Principle can realize under the situation of spirit that does not break away from the embodiment of the invention or scope in other embodiments among this paper.Therefore, the embodiment of the invention will can not be restricted to these embodiment shown in this paper, but will meet and principle disclosed herein and features of novelty the wideest corresponding to scope.
The above is merely the preferred embodiment of the embodiment of the invention; Not in order to the restriction embodiment of the invention; All within the spirit and principle of the embodiment of the invention, any modification of being done, be equal to replacement, improvement etc., all should be included within the protection range of the embodiment of the invention.
Claims (15)
1. a signal isolation method is characterized in that, comprising:
Main power voltage to for main power source territory power supply detects, and when detecting said main power voltage when being in the predeterminated voltage section, produces reset signal;
According to said reset signal, produce first level signal;
Control the signal that isolating device is isolated said main power source territory according to said first level signal, so that the signal in said main power source territory can't get into said stand-by power supply territory.
2. the method for claim 1 is characterized in that, said signal of isolating said main power source territory according to said first level signal control isolating device so that the signal in said main power source territory can't get into said stand-by power supply territory, comprising:
Directly control the signal that isolating device is isolated said main power source territory by said first level signal, so that the signal in said main power source territory can't get into said stand-by power supply territory.
3. the method for claim 1 is characterized in that, said signal of isolating said main power source territory according to said first level signal control isolating device so that the signal in said main power source territory can't get into said stand-by power supply territory, comprising:
Said first level signal is carried out voltage keep handling, produce second level signal;
Directly control the signal that isolating device is isolated said main power source territory by said second level signal, so that the signal in said main power source territory can't get into said stand-by power supply territory.
4. the method for claim 1 is characterized in that, said signal of isolating said main power source territory according to said first level signal control isolating device so that the signal in said main power source territory can't get into said stand-by power supply territory, comprising:
Said first level signal is carried out voltage keep handling, produce three level signal;
Said three level signal is carried out voltage stabilizing handle, produce the 4th level signal;
Directly control the signal that isolating device is isolated said main power source territory by said the 4th level signal, so that the signal in said main power source territory can't get into said stand-by power supply territory.
5. like the described method of arbitrary claim in the claim 1 to 4, it is characterized in that, also comprise:
Behind the input signal that receives the central processor CPU generation, produce the 5th level signal;
According to said the 5th level signal control isolating device, make the signal in said main power source territory get into said stand-by power supply territory.
6. a signal isolating device is characterized in that, comprising:
Voltage detection unit is used for the main power voltage for main power source territory power supply is detected, and when detecting said main power voltage when being in the predeterminated voltage section, produces reset signal;
The first signal generation unit is used for the reset signal according to said voltage detection unit generation, produces first level signal;
Isolated location, the signal that first level signal control isolating device that is used for producing according to the said first signal generation unit is isolated said main power source territory is so that the signal in said main power source territory can't get into said stand-by power supply territory.
7. device as claimed in claim 6; It is characterized in that; Said isolated location specifically is used for: first level signal by the said first signal generation unit produces is directly controlled the signal that isolating device is isolated said main power source territory, so that the signal in said main power source territory can't get into said stand-by power supply territory.
8. device as claimed in claim 6 is characterized in that, said isolated location comprises:
Secondary signal produces subelement, is used for that first level signal that the said first signal generation unit produces is carried out voltage and keeps handling, and produces second level signal;
The first separaant unit is used for directly controlling the signal that isolating device is isolated said main power source territory by second level signal that said secondary signal generation subelement produces, so that the signal in said main power source territory can't get into said stand-by power supply territory.
9. device as claimed in claim 6 is characterized in that, said isolated location comprises:
The 3rd signal produces subelement, is used for that first level signal that the said first signal generation unit produces is carried out voltage and keeps handling, and produces three level signal;
The 4th signal produces subelement, is used for that the three level signal that said the 3rd signal generation subelement produces is carried out voltage stabilizing and handles, and produces the 4th level signal;
The second separaant unit is used for directly controlling the signal that isolating device is isolated said main power source territory by the 4th level signal that said the 4th signal generation subelement produces, so that the signal in said main power source territory can't get into said stand-by power supply territory.
10. like the described device of arbitrary claim in the claim 6 to 9, it is characterized in that, also comprise:
The 5th signal generation unit is used for behind the input signal that receives the central processor CPU generation, producing the 5th level signal;
Control unit, the 5th level signal that is used for producing according to said the 5th signal generation unit is controlled isolating device, makes the signal in said main power source territory get into said stand-by power supply territory.
11. a chip is characterized in that, comprising:
Voltage detector VD, said VD detects the main power voltage for main power source territory power supply, when detecting said main power voltage when being in the predeterminated voltage section, produces reset signal;
Signal isolation circuit, the output of said VD is connected with the reset terminal of said signal isolation circuit, and said signal isolation circuit produces a level signal according to the reset signal that said VD produces;
Isolating device; The output of said signal isolation circuit is connected with the Enable Pin of said isolating device; Level signal by said signal isolation circuit produces is directly controlled the signal that isolating device is isolated said main power source territory, so that the signal in said main power source territory can't get into said stand-by power supply territory.
12. chip as claimed in claim 11 is characterized in that, said signal isolation circuit comprises:
The first basic circuit unit triggers device flip-flop; The output of said VD is connected with the reset terminal of a said flip-flop; The reset signal that a said flip-flop produces according to said VD; Produce a level signal; The output of a said flip-flop is connected with the Enable Pin of said isolating device, directly controls the signal that isolating device is isolated said main power source territory by the level signal that a said flip-flop produces, so that the signal in said main power source territory can't get into said stand-by power supply territory.
13. chip as claimed in claim 12 is characterized in that, said signal isolation circuit also comprises:
The first bus level holding unit Bushold; The output of a said flip-flop is connected with the input of a said Bushold; The level signal that a said Bushold produces a said flip-flop is carried out voltage and is kept handling; Produce a level signal; The output of a said Bushold is connected with the Enable Pin of said isolating device, directly controls the signal that isolating device is isolated said main power source territory by the level signal that a said Bushold produces, so that the signal in said main power source territory can't get into said stand-by power supply territory.
14. chip as claimed in claim 13 is characterized in that, said signal isolation circuit also comprises:
The 2nd flip-flop, the output of said VD is connected with the reset terminal of said the 2nd flip-flop, and said the 2nd flip-flop produces a level signal after receiving the reset signal of said VD generation;
The 2nd Bushold, the output of said the 2nd flip-flop is connected with the input of said the 2nd Bushold, and the level signal that said the 2nd Bushold produces said the 2nd flip-flop is carried out voltage and is kept handling, and produces a level signal;
The 3rd flip-flop; The output of a said Bushold is connected with the clock end of said the 3rd flip-flop; The output of said the 2nd Bushold is connected with the reset terminal of said the 3rd flip-flop; The level signal that the level signal that said the 3rd fl ip-flop produces according to said the 2nd Bushold produces a said Bushold is carried out voltage stabilizing and is handled; Produce a level signal; Said isolating device is connected with the output of said the 3rd flip-flop, directly controls the signal that isolating device is isolated said main power source territory by the level signal that said the 3rd flip-flop produces, so that the signal in said main power source territory can't get into said stand-by power supply territory.
15. like the described chip of arbitrary claim in the claim 12 to 14, it is characterized in that, also comprise:
Central processor CPU; Said CPU places the main power source territory, and the input of said signal isolation circuit is connected with said cpu bus, after the main power source for the power supply of main power source territory powers on; Control said signal isolation circuit by said CPU; Produce a level signal, the signal in the said main power source of the level signal control isolating device conducting territory that is produced by said signal isolation circuit makes the signal in said main power source territory get into said stand-by power supply territory.
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| CN111052037A (en) * | 2017-09-06 | 2020-04-21 | Arm有限公司 | Reset isolation bridge |
| CN111052037B (en) * | 2017-09-06 | 2023-10-27 | Arm有限公司 | Reset isolation bridge |
| CN111258404A (en) * | 2018-12-03 | 2020-06-09 | 珠海格力电器股份有限公司 | Isolation circuit system and method for signal isolation |
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