CN102694542B - Signal isolation methods, apparatus and chip - Google Patents

Signal isolation methods, apparatus and chip Download PDF

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CN102694542B
CN102694542B CN 201210141650 CN201210141650A CN102694542B CN 102694542 B CN102694542 B CN 102694542B CN 201210141650 CN201210141650 CN 201210141650 CN 201210141650 A CN201210141650 A CN 201210141650A CN 102694542 B CN102694542 B CN 102694542B
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CN 201210141650
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CN102694542A (en )
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于立波
马文波
张炜
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北京华大信安科技有限公司
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Abstract

本发明实施例公开了信号隔离方法、装置及芯片,该方法包括:对为主电源域供电的主电源电压进行检测,当检测出所述主电源电压处于预设电压区段时,产生复位信号;根据所述复位信号,产生第一电平信号;根据所述第一电平信号控制隔离器件隔离所述主电源域的信号,以使所述主电源域的信号无法进入所述备用电源域。 Example embodiments disclosed isolation method of the present invention, a signal, and a chip device, the method comprising: a primary power supply voltage of the main power domains can be detected, when the mains voltage is detected at a preset voltage section that generates a reset signal ; according to the reset signal, generating a first signal level; according to the first signal for controlling the level of the main power supply isolation means isolating domain signals, the main power supply so that the signal can not enter the domain of the standby power domain . 本发明技术方案中,可以及时发现主电源掉电,并控制隔离器件隔离主电源域的信号,从而使主电源域的信号无法进入备用电源域,避免了对备用电源域的信号产生影响。 Aspect of the present invention, it is possible to detect the main power failure, and the control signal of the main power supply isolation device isolation region, so that the signal of the main power domain can not enter standby power field, to avoid the affect on the standby power domain.

Description

信号隔离方法、装置及芯片 Signal isolation methods, apparatus and chip

技术领域 FIELD

[0001]本发明涉及芯片设计技术领域,尤其涉及信号隔离方法、装置及芯片。 [0001] The present invention relates to the field of chip design technology, and particularly to a signal isolation method, apparatus and chip.

背景技术 Background technique

[0002]在进行芯片设计时,通常采用多电源域设计,以便实现特定的电路功能,例如,安全芯片的片上系统(SoC,System on Chip)内可以设置两个电源域,其中由主电源供电的电源域称为主电源域,一般包含常规芯片逻辑,例如,中央处理器(CPU,Central ProcessingUnit)、闪存(Flash)、只读存储器(R0M,Read_0nly Memory)、随机存取存储器(RAM,RandomAccess Memory)等,由备用电源供电的电源域称为备用电源域,通常包括非易失随机存取存储体(NVRAM,Non_Volatile Random Access Memory)等,正常情况下主电源为上电状态,备用电源为掉电状态,而当主电源意外掉电时,备用电源才变为上电状态,这时备用电源仅给备用电源域进行供电,从而在主电源掉电后,可以由备用电源给备用电源域内的NVRAM供电,使NVRAM仍能保持数据,以延长数据保持时间。 [0002] During chip design, the design usually multiple power domains, in order to achieve a specific circuit function, for example, the system (SoC, System on Chip) on the security chip may be provided two sheet supply domains, wherein the main power supply the main power supply domain is called domain, typically comprising a conventional logic chip, e.g., a central processing unit (CPU, central ProcessingUnit), flash memory (the Flash), read-only memory (R0M, Read_0nly memory), a random access memory (RAM, RandomAccess memory), etc., by a power supply backup power domain called standby power domain, typically comprising a non-volatile random access memory bank (NVRAM, Non_Volatile random access memory) and the like, under normal circumstances, the main power supply to a powered state, standby power power-down state, the main power source when an unexpected power-down, it becomes the standby power supply state, then only standby power to the backup power supply field, so that after the main power failure, a backup power source may be a backup power supply in the art NVRAM power, so it can maintain NVRAM data, to extend the data retention time.

[0003] 上述安全芯片的SoC设计方案中,虽然通过设置主电源域和备用电源域,可以在主电源掉电后,由备用电源给备用电源域供电,但是在主电源掉电后,主电源域的信号仍然能够进入备用电源域,从而对备用电源域的信号产生影响。 [0003] SoC design of the above security chip, although the power domain by providing the primary and backup power domains, may, after the main power failure, a backup power supply to the backup power supply domain, but after the main power failure, the main power supply signal domain can still enter standby power domain, and thus affect on the standby power domain.

发明内容 SUMMARY

[0004]本发明实施例中提供了信号隔离方法、装置及芯片,用以解决现有技术中存在的在主电源掉电后,主电源域的信号仍然能够进入备用电源域,从而对备用电源域的信号产生影响的问题。 [0004] The embodiments of the present invention provides signal isolation method, apparatus and chip to solve the prior art after the power is switched off the main power domain signal can still enter standby power domain, thereby standby power issues affecting the signal domain.

[0005]为解决上述问题,本发明实施例提供的技术方案如下: [0005] In order to solve the above problem, the technical solution provided by the embodiment of the present invention is as follows:

[0006] —种信号隔离方法,该方法包括:对为主电源域供电的主电源电压进行检测,当检测出所述主电源电压处于预设电压区段时,产生复位信号;根据所述复位信号,产生第一电平信号;根据所述第一电平信号控制隔离器件隔离所述主电源域的信号,以使所述主电源域的信号无法进入所述备用电源域。 [0006] - isolating kinds of signals, the method comprising: a primary power supply voltage of the main power domains can be detected, when the mains voltage is detected at a preset voltage section that generates a reset signal; reset according to the signal, generating a first signal level; level signal according to the first control signal isolation means isolating the main power supply domain, the main power supply so that the signal can not enter the domain of the standby power domain.

[0007] —种信号隔离装置,包括:电压检测单元,用于对为主电源域供电的主电源电压进行检测,当检测出所述主电源电压处于预设电压区段时,产生复位信号;第一信号产生单元,用于根据所述电压检测单元产生的复位信号,产生第一电平信号;隔离单元,用于根据所述第一信号产生单元产生的第一电平信号控制隔离器件隔离所述主电源域的信号,以使所述主电源域的信号无法进入所述备用电源域。 [0007] - seed signal isolating means, comprising: a voltage detecting unit for the power supply to the main power supply voltage detection domain master, when the mains voltage is detected at a preset voltage section that generates a reset signal; a first signal generating unit, a reset signal according to the detection voltage generating unit generates a first level signal; isolation means, means for generating a first signal generated from the first level signal controlling the isolation means isolating the main power supply domain signals, the main power supply so that the signal can not enter the domain of the standby power domain.

[0008] —种芯片,包括:电压检测器VD,所述VD对为主电源域供电的主电源电压进行检测,当检测出所述主电源电压处于预设电压区段时,产生复位信号;信号隔离电路,所述VD的输出端与所述信号隔离电路的输入端相连接,所述信号隔离电路根据所述VD产生的复位信号,产生一电平信号;隔离器件,所述信号隔离电路的输出端与所述隔离器件的使能端相连接,由所述信号隔离电路产生的电平信号直接控制隔离器件隔离所述主电源域的信号,以使所述主电源域的信号无法进入所述备用电源域。 [0008] - seed chip, comprising: a voltage detector VD, the primary power supply voltage VD of the main power domains can be detected, when the mains voltage is detected at a preset voltage section that generates a reset signal; signal isolation circuit input terminal, an output terminal of the VD signal of said isolation circuit is connected to said signal separating circuit to the reset signal VD generated by generating a level signal; isolation devices, said signal separating circuit the output of the isolation device is enabled end connected to the level signal generated by said signal separating circuit directly controlling the isolation means isolating the main power supply signal domain, the main power supply so that a signal can not enter the domain the standby power domain.

[0009]本发明实施例技术方案所提供的信号隔离方法,通过对为主电源域供电的主电源电压进行检测,能够及时检测出主电源电压发生变化,并在检测出主电源电压处于预设电压区段时,产生复位信号,根据该复位信号,产生第一电平信号,根据该第一电平信号控制隔离器件隔离所述主电源域的信号,以使所述主电源域的信号无法进入所述备用电源域。 [0009] The method for isolating signals of the technical solution provided in embodiments of the present invention, the power source voltage detected by the main power supply to the main field, the ability to detect changes in the mains voltage and mains voltage is detected in a preset voltage section, a reset signal is generated, based on the reset signal, generating a first signal level, the main power supply signal according to the first domain isolation level signal controlling the isolation means, so that the signal is not the main power supply domain entering the standby power domain. 由上可见,采用本发明实施例技术方案,可以通过检测主电源电压处于预设电压区段,及时发现主电源掉电,并控制隔离器件隔离主电源域的信号,从而使主电源域的信号无法进入备用电源域,避免了对备用电源域的信号产生影响。 As seen above, the signal using the technical solution of the present embodiment of the invention, may be in the main power supply by detecting a predetermined voltage section, to detect the main power failure, and a control signal isolation means isolating the main power supply domain, so that the main power domain entering standby power domain, avoiding the impact on standby power domain signal.

附图说明 BRIEF DESCRIPTION

[0010]为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。 [0010] In order to more clearly illustrate the technical solutions in the embodiments or the prior art embodiment of the present invention, the drawings are briefly introduced as required for use in the embodiments describing the embodiments. Apparently, the accompanying drawings described below are merely Some embodiments of the invention, those of ordinary skill in the art is concerned, without creative efforts, can derive from these drawings other drawings.

[0011]图1是本发明实施例一中,信号隔离方法流程示意图; [0011] FIG. 1 is an embodiment of the present invention, in the embodiment, signal isolation schematic flow chart of the method;

[0012]图2是本发明实施例二中,信号隔离装置第一结构示意图; [0012] FIG. 2 is a II, a schematic view of a first configuration example of the signal isolator device of the present embodiment of the invention;

[0013]图3是本发明实施例二中,隔离单元23第一结构示意图; [0013] FIG. 3 is the second embodiment of the present invention, a schematic view of a first structural isolating unit 23;

[0014]图4是本发明实施例二中,隔离单元23第二结构示意图; [0014] FIG. 4 is the second embodiment of the present invention, a schematic view of a second structural isolating unit 23;

[0015]图5是本发明实施例二中,信号隔离装置第二结构示意图; [0015] FIG. 5 is a diagram illustrating a second configuration example II, the embodiment of the present invention, the signal isolation means;

[0016]图6是本发明实施例三中,芯片第一电路原理图; [0016] FIG. 6 is three in the embodiment, the first chip circuit schematic embodiment of the present invention;

[0017]图7是本发明实施例四中,芯片第二电路原理图; [0017] FIG. 7 is four, the circuit diagram of a second embodiment of the chip of the present invention;

[0018]图8是本发明实施例五中,芯片第三电路原理图; [0018] FIG. 8 is a fifth embodiment, the chip of the third embodiment of the present invention, the circuit diagram;

[0019]图9是本发明实施例五中,主电源、复位信号与隔离信号的时序图; [0019] FIG. 9 is a fifth embodiment, a timing chart of the main power supply, the reset signal and the isolation signal according to the present invention;

[0020]图10是本发明实施例六中,芯片第四电路原理图; [0020] Sixth embodiment FIG. 10 is a chip of the fourth embodiment of the present invention, the circuit diagram;

[0021]图11是本发明实施例中,一种整体芯片组成示意图。 [0021] FIG. 11 is a diagram of a schematic overall chips embodiment of the present invention.

具体实施方式 detailed description

[0022]下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整的描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。 [0022] below in conjunction with the present invention in the accompanying drawings, technical solutions of embodiments of the present invention will be clearly and fully described, obviously, the described embodiments are merely part of embodiments of the present invention, but not all embodiments example. 基于本发明中的实施例,本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。 Based on the embodiments of the present invention, those of ordinary skill in the art to make all other embodiments without creative work obtained by, it falls within the scope of the present invention.

[0023] 实施例一 [0023] Example a

[0024]如图1所示,为本发明实施例一提出的信号隔离方法流程示意图,其具体处理流程如下: [0024] As shown in FIG. 1, a schematic flow chart of the present method of isolating a signal diagram of a proposed embodiment of the invention, the specific process is as follows:

[0025] 步骤11,对为主电源域供电的主电源电压进行检测,当检测出所述主电源电压处于预设电压区段时,产生复位信号。 [0025] Step 11, based on the main power supply voltage supply region is detected, when the mains voltage is detected at a preset voltage section that generates a reset signal.

[0026] 其中,可以通过芯片内原有的电压检测(VD,Voltage Detector)模块或上电复位(PoR,Power on Reset)模块对主电源电压进行检测。 [0026] wherein, by detecting the original chip voltage (VD, Voltage Detector) module or a power-on reset (PoR, Power on Reset) module for detecting the mains voltage.

[0027]本发明实施例一中,上述预设电压区段可以预先设置为一个电压值,例如2.55伏,也可以预先设置为一个电压区间,例如,2.55〜2.15V。 Embodiment [0027] In an embodiment of the present invention, the above-described predetermined voltage sections may be set in advance to a voltage value, for example 2.55 volts, may be previously set to a voltage range, e.g., 2.55~2.15V.

[0028]步骤12,根据复位信号,产生第一电平信号。 [0028] Step 12, according to the reset signal, generating a first level signal.

[0029]可以通过一个基本电路单元触发器(flip-flop)的复位端来接收上述复位信号,flip-flop的复位端接收到复位信号后,由flip-flop的输出端产生第一电平信号,此时,上述第一电平信号为低电平信号。 After [0029] the reset signal may be received by a base unit flop circuit (flip-flop) of the reset terminal, the reset flip-flop receives a reset signal, generating a first level signal from the output terminal of flip-flop In this case, the first level signal is a low level signal.

[0030]步骤13,根据第一电平信号控制隔离器件隔离所述主电源域的信号,以使主电源域的信号无法进入备用电源域。 [0030] Step 13, the control signal isolation means isolating the main power supply according to a first domain signal level, so that the signal can not enter the main power supply domain standby power domain.

[0031]其中,可以由上述第一电平信号直接控制隔离器件隔离主电源域的信号,以使所述主电源域的信号无法进入所述备用电源域,也可以对上述第一电平信号进行处理后,再由处理后的信号控制隔离器件隔离主电源域的信号。 [0031] wherein the isolation means can be directly controlled by the first level signal isolation domain signal of the main power supply, the main power supply so that the signal can not enter the domain of the standby power domain may be on the first level signal after treatment, the isolation device and then isolating the control signal from the main power supply domain signal processing.

[0032] 本发明实施例一中,对上述第一电平信号的处理方式可以但不限于下述两种: [0032] In an embodiment of the present invention embodiment, the handling of the first level signal may be but is not limited to the following two:

[0033]第一种处理方式,对第一电平信号进行电压保持处理,产生第二电平信号,由第二电平信号直接控制隔离器件隔离主电源域的信号,以使主电源域的信号无法进入备用电源域。 [0033] The first approach, the first level of the signal voltage holding process, generating a second level signal, the control signal directly to the main power supply isolation device isolation region by the second level signal, so that the main power domain signal entering standby power domain.

[0034]由于在主电源掉电完成后,步骤12所产生的第一电平信号可能会发生变化,例如由低电平信号变为高阻状态,由上述第一电平信号直接控制隔离器件隔离主电源域的信号的可靠性较低,本发明实施例一中,通过采用上述第一种处理方式对第一电平信号进行电压保持处理后,可以在主电源掉电完成后,第二电平信号仍然保持稳定的低电平信号,由该第二电平信号控制隔离器件隔离主电源域的信号的可靠性较高。 [0034] Since the completion of the main power failure, the first signal level generated by the step 12 may vary, for example, a low level signal becomes high impedance, the control means directly by the first isolation level signal the lower signal power domain primary isolation reliability, in one embodiment of the present invention, the first level by holding the voltage signal processing using the above-described manner after the first treatment, after the completion of the main power supply can be powered down, the second level signal is a low level signal remains stable, highly reliable isolation device by the second level signal to control the main power supply isolation domain signal.

[0035]第二种处理方式,先对第一电平信号进行电压保持处理,产生第三电平信号,然后对第三电平信号进行稳压处理,产生第四电平信号,由第四电平信号直接控制隔离器件隔离主电源域的信号,以使主电源域的信号无法进入备用电源域。 [0035] A second process embodiment, the first level of a first voltage holding process signal, generating a third signal level, and then to the third level regulator signal processing to produce a fourth level signal by the fourth level signal to directly control the main power supply signal isolation device isolation region so that the main power supply domain signal entering standby power domain.

[0036]由于采用第一种处理方式,对第一电平信号进行电压保持处理后,得到的第二电平信号,仍然有可能存在电压不稳的情况,为了使主电源掉电后,能够产生稳定的电平信号来控制隔离器件生效,可以采用第二种处理方式,由于第二种处理方式中,对第一电平信号不仅要进行电压保持处理,还要对产生的第三电平信号进行稳压处理,因此进一步加强了电平信号的稳定性,从而由稳压处理后的第四电平信号控制隔离器件隔离主电源域的信号的可靠性更高。 After [0036] As a result of the first approach, the first level of the signal voltage hold processing, the second level signal is obtained, there may still voltage instability case, to the main power supply after a power failure, it is possible generate a stable level signal to control the isolation device into effect, the second approach may be employed, since the second process, the signal level of the first voltage holding process to be performed not only, but also on the third level generated Regulators signal processing, thus to further strengthen the stability of the level of the signal to isolate the control signal from the fourth level to a regulated process isolation means higher reliability of the main power signal domain.

[0037] 此外,为了保证在主电源上电后,使主电源域的信号进入备用电源域,还要通过程序设定,在主电源上电后由CPU产生一个输入信号,当接收到CPU产生的输入信号后,产生第五电平信号,根据第五电平信号控制隔离器件旁路,使主电源域的信号能够进入备用电源域。 [0037] Further, in order to ensure that after power on the main power supply, the main power supply of the signal domain enter standby power domain, but also be programmed to produce a signal input from the CPU after the power on the main power supply to the CPU is generated when the received after the input signal to produce a fifth level signal, the level signal according to the fifth bypass control isolation devices, the main power source of the signal field can enter the standby power domain.

[0038]上述第五电平信号应与第一电平信号、第二电平信号、第三电平信号及第四电平信号的信号状态不同,例如,若第一电平信号、第二电平信号、第三电平信号及第四电平信号为低电平信号,则第五电平信号可以为高电平信号。 [0038] The fifth level signal should the first level signal, a second signal level, a different state of the third signal and the fourth signal level of the level signal, for example, when the first level signal, the second level signal, the fourth signal and the third level is a low signal level of the signal, the fifth level of the signal may be a high-level signal.

[0039]由上述处理过程可知,采用本发明实施例一的信号隔离方法,通过对为主电源域供电的主电源电压进行检测,能够及时检测出主电源电压发生变化,并在检测出主电源电压处于预设电压区段时,产生复位信号,根据该复位信号,产生第一电平信号,根据该第一电平信号控制隔离器件隔离所述主电源域的信号,以使所述主电源域的信号无法进入所述备用电源域。 [0039] From the above process, the signal isolation method using an embodiment of the present invention, the power source voltage detected by the main power supply to the main field can be detected in time the main power supply voltage changes, and the main power supply is detected when the segment voltage is the predetermined voltage, a reset signal is generated, based on the reset signal, generating a first signal level, the main power supply signal according to the first domain isolation level signal controlling the isolation means, so that said main power supply signal domain can not enter the standby power domain. 由上可见,采用本发明实施例一的技术方案,可以通过检测主电源电压处于预设电压区段,及时发现主电源掉电,并控制隔离器件隔离主电源域的信号,从而使主电源域的信号无法进入备用电源域,避免了对备用电源域的信号产生影响。 Seen from the above, the use of a technical solution of the embodiment of the present invention, may be in the main power supply by detecting a predetermined voltage section, to detect the main power failure, and a control signal isolation means isolating the main power supply domain, so that the main power domain signal entering standby power domain, avoiding the impact on standby power domain signal.

[0040] 实施例二 [0040] Second Embodiment

[0041]相应的,本发明实施例二提供一种信号隔离装置,其结构如图2所示,包括: [0041] Accordingly, according to a second embodiment of the present invention to provide a signal isolation means, the structure shown in Figure 2, comprising:

[0042]电压检测单元21,用于对为主电源域供电的主电源电压进行检测,当检测出所述主电源电压处于预设电压区段时,产生复位信号; [0042] The voltage detecting unit 21, a main power supply voltage of the main power domain detects when the mains voltage is detected at a preset voltage section that generates a reset signal;

[0043]第一信号产生单元22,用于根据所述电压检测单元21产生的复位信号,产生第一电平信号; [0043] 22, according to a reset signal generated by said voltage detecting means 21 generates a first level signal a first signal generating means;

[0044]隔离单元23,用于根据所述第一信号产生单元22产生的第一电平信号控制隔离器件隔离所述主电源域的信号,以使所述主电源域的信号无法进入所述备用电源域。 [0044] isolating unit 23 for isolating the main power supply signal according to a first domain signal for controlling the level of the spacer means 22 generates a first signal generating unit, and the main power supply so that the signal can not enter the domain standby power domain.

[0045]较佳地,所述隔离单元23具体用于:由所述第一信号产生单元22产生的第一电平信号直接控制隔离器件隔离所述主电源域的信号,以使所述主电源域的信号无法进入所述备用电源域。 [0045] Preferably, the spacer unit 23 is specifically configured to: a first level of a signal generated by the first signal generating unit 22 directly controls the signal isolation means isolating the main power supply domain, so that the main domain signal power can not enter the standby power domain.

[0046]较佳地,本发明实施例二提供一种隔离单元23,其结构如图3所示,隔离单元23包括: [0046] Preferably, a separator unit according to a second embodiment 23 of the present invention, the structure as shown in FIG isolation unit 323 comprises:

[0047]第二信号产生子单元231,用于对所述第一信号产生单元22产生的第一电平信号进行电压保持处理,产生第二电平信号; [0047] The second sub-signal generating unit 231, a first-level signal generating unit 22 for generating the first signal voltage holding process, generating a second level signal;

[0048]第一隔离子单元232,用于由所述第二信号产生子单元231产生的第二电平信号直接控制隔离器件隔离所述主电源域的信号,以使所述主电源域的信号无法进入所述备用电源域。 Second level signal [0048] The first isolation sub-unit 232, for generating a signal generated by said second sub-unit 231 directly controls the signal isolation means isolating the main power supply domain, so that the main power supply domain signal domain can not enter the standby power.

[0049]较佳地,本发明实施例二提供另一种隔离单元23,其结构如图4所示,隔离单元23包括: [0049] Preferably, according to a second isolation unit 23 provides another embodiment of the present invention, the structure shown in Figure 4, the isolation means 23 comprises:

[0050]第三信号产生子单元233,用于对所述第一信号产生单元22产生的第一电平信号进行电压保持处理,产生第三电平信号; [0050] The third sub-signal generating unit 233, for generating a first level signal generating unit 22 of the first signal voltage holding process, generating a third signal level;

[0051]第四信号产生子单元234,用于对所述第三信号产生子单元233产生的第三电平信号进行稳压处理,产生第四电平信号; [0051] The fourth sub-signal generating unit 234, a third sub-level signal generating means for generating the third signal 233 is regulated process, generating a fourth level signal;

[0052]第二隔离子单元235,用于由所述第四信号产生子单元234产生的第四电平信号直接控制隔离器件隔离所述主电源域的信号,以使所述主电源域的信号无法进入所述备用电源域。 [0052] The second isolation sub-unit 235, for generating a fourth signal from said fourth level sub-unit 234 generates a signal directly controlling the isolation means isolating the main power supply domain signal, so that the main power supply domain signal domain can not enter the standby power.

[0053]较佳地,本发明实施例二提供另一种信号隔离装置,其结构如图5所示,包括: [0053] Preferably, two embodiments of the present invention provides another signal isolation means, the structure shown in Figure 5, comprising:

[0054]电压检测单元51,用于对为主电源域供电的主电源电压进行检测,当检测出所述主电源电压处于预设电压区段时,产生复位信号; [0054] The voltage detection unit 51, a main power supply voltage of the main power domain detects when the mains voltage is detected at a preset voltage section that generates a reset signal;

[0055]第一信号产生单元52,用于根据所述电压检测单元51产生的复位信号,产生第一电平信号; [0055] The first signal generating unit 52, a reset signal according to the detection voltage generating unit 51 generates a first level signal;

[0056]隔离单元53,用于根据所述第一信号产生单元52产生的第一电平信号控制隔离器件隔离所述主电源域的信号,以使所述主电源域的信号无法进入所述备用电源域; [0056] The isolation unit 53, a control signal for a first level of isolation devices in accordance with the first signal generating unit 52 generates a signal of the main power supply isolation domain, the main power supply so that the signal can not enter the domain standby power domain;

[0057]第五信号产生单元54,用于当接收到CPU产生的输入信号后,产生第五电平信号; [0057] The fifth signal generating unit 54, for receiving the input signal when the CPU is generated, generate a fifth signal level;

[0058]控制单元55,用于根据所述第五信号产生单元54产生的第五电平信号控制隔离器件,使所述主电源域的信号进入所述备用电源域。 [0058] The control unit 55, a fifth level of the control signal generated by the device isolation according to the fifth signal generating unit 54, a signal entering the domain of the main power supply backup power domain.

[0059]采用本发明实施例二提供的信号隔离装置,先由电压检测单元21对为主电源域供电的主电源电压进行检测,能够及时检测出主电源电压发生变化,并在检测出主电源电压处于预设电压区段时,产生复位信号,然后由第一信号产生单元22根据电压检测单元21产生的复位信号,产生第一电平信号,再由隔离单元23根据第一信号产生单元22产生的第一电平信号控制隔离器件隔离所述主电源域的信号,以使所述主电源域的信号无法进入所述备用电源域。 [0059] The signal isolation apparatus according to a second embodiment of the present invention, first voltage detecting unit 21 as the master power supply voltage supply domain be detected, can be detected in time the main power supply voltage changes, and the main power supply is detected when the segment voltage is the predetermined voltage, a reset signal is then generated in accordance with a reset signal 22 from the voltage detection unit 21 a first signal generating unit generates a first level signal, and then by the separating means 2322 according to the first signal generating unit first level control signal generated signal isolation means isolating the main power supply domain, the main power supply so that the signal can not enter the domain of the standby power domain. 由上可见,采用本发明实施例技术方案,可以通过电压检测单元21检测主电源电压处于预设电压区段,及时发现主电源掉电,并由隔离单元23控制隔离器件隔离主电源域的信号,从而使主电源域的信号无法进入备用电源域,避免了对备用电源域的信号产生影响。 As it is seen above, the signal using the technical solution of the present embodiment of the invention, the mains voltage may be detected 21 at a predetermined voltage by the voltage detecting section means, to detect the main power failure, isolated by isolation unit 23 controls the main power source device isolation domain , so that the signal of the main power domain can not enter standby power field, to avoid the affect on the standby power domain.

[0060] 实施例三 [0060] Example three

[0061]相应的,本发明实施例三提供一种芯片,其电路原理图如图6所示,包括: [0061] Accordingly, according to a third embodiment of the present invention to provide a chip, the circuit diagram shown in Figure 6, comprising:

[0062] VD,所述VD对为主电源域供电的主电源电压进行检测,当检测出所述主电源电压处于预设电压区段时,产生复位信号; [0062] VD, the primary power supply voltage VD of the main power domains can be detected, when the mains voltage is detected at a preset voltage section that generates a reset signal;

[0063]信号隔离电路,所述VD的输出端与所述信号隔离电路的输入端相连接,所述信号隔离电路根据所述VD产生的复位信号,产生一电平信号; [0063] The isolation circuit input signal, the output of the signal VD and the end of the isolation circuit connected to said signal separating circuit to the reset signal VD generated by generating a level signal;

[0064]隔离器件,所述信号隔离电路的输出端与所述隔离器件的使能端相连接,由所述信号隔离电路产生的电平信号直接控制隔离器件隔离所述主电源域的信号,以使所述主电源域的信号无法进入所述备用电源域。 [0064] The isolation device, the output terminal of said signal separating circuit and the isolator element end connected to the enable level of a signal generated by said signal separating circuit directly controlling the isolation means isolating the main power supply domain signal, the main power supply so that the signal can not enter the domain of the standby power domain.

[0065]为了使主电源上电后,控制隔离器件旁路,使主电源域的信号进入备用电源域,可以利用主电源域中预先设置的CPU,所述信号隔离电路的输入端与所述CPU总线相连接,当为主电源域供电的主电源上电后,由所述CHJ控制所述信号隔离电路,产生一电平信号;由所述信号隔离电路产生的电平信号控制隔离器件导通所述主电源域的信号,使所述主电源域的信号进入所述备用电源域。 [0065] For the main power supply after power on, bypass control isolation devices, the main power supply of the signal domain enter standby power domain, power domains can use the main CPU is set in advance, an input terminal of said isolation circuit and the signal a CPU bus connected to the main power supply when the main power supply domain, the signal isolation circuit controlled by the CHJ generating a level signal; a level signal generated by said signal separating circuit to control isolation devices guide signal via the main power supply domain, the main power supply so that a signal entering the domain standby power domain.

[0066] 其中,VD也可由PoR替代,对主电源电压进行检测,当检测出所述主电源电压处于预设电压区段时,产生复位信号。 [0066] wherein, VD also be PoR Alternatively, the main power supply voltage is detected, when the mains voltage is detected at a preset voltage section that generates a reset signal.

[0067]实施例四 [0067] Fourth Embodiment

[0068]相应的,本发明实施例四提供另一种芯片,其电路原理图如图7所示,信号隔离电路包括:第一flip-flop,所述VD的输出端与所述第一flip-flop的复位端相连接,所述第一flip-flop根据所述VD产生的复位信号,产生一电平信号,所述第一flip-flop的输出端与所述隔离器件的使能端相连接,由所述第一flip-flop产生的电平信号直接控制隔离器件隔离所述主电源域的信号,以使所述主电源域的信号无法进入所述备用电源域。 [0068] Accordingly, embodiments of the present invention provides another four chip, the circuit diagram shown in Figure 7, the signal isolation circuit comprises: a first flip-flop, the output of VD is the first flip -flop reset end connected to said first flip-flop the reset signal VD generated, generates a level signal, an output terminal of said first flip-flop of the isolation device enable end connection level of the signal generated by said first flip-flop signal directly controlling the isolation means isolating the main power supply domain, the main power supply so that the signal can not enter the domain of the standby power domain.

[0069] 实施例五 [0069] Embodiment V

[0070]相应的,本发明实施例五提供另一种芯片,其电路原理图如图8所示,信号隔离电路包括:第一flip-flop,所述VD的输出端与所述第一flip-flop的复位端相连接,所述第一flip-flop根据所述VD产生的复位信号,产生一电平信号;第一总线电平保持单元Bushold,所述第一flip-flop的输出端与所述第一Bushold的输入端相连接,所述第一Bushold对所述第一flip-flop产生的电平信号进行电压保持处理,产生一电平信号,所述第一Bushold的输出端与所述隔离器件的使能端相连接,由所述第一Bushold产生的电平信号直接控制隔离器件隔离所述主电源域的信号,以使所述主电源域的信号无法进入所述备用电源域。 [0070] Accordingly, according to the fifth embodiment of the present invention provides another chip, the circuit diagram shown in Figure 8, the signal isolation circuit comprises: a first flip-flop, the output of VD is the first flip -flop reset end connected to said first flip-flop reset signal VD generated by said generating a level signal; a first bus Bushold level holding unit, the first output terminal of the flip-flop Bushold the first connected to the input of said first pair of Bushold the first level signal generated by flip-flop voltage holding process, generates a level signal, the first output terminal of the Bushold enabling said isolation devices are connected end level of a signal generated by the direct control of isolation devices Bushold first isolated signal domain the main power supply, the main power supply so that the signal can not enter the domain of the standby power domain .

[0071]其中,为了使电路结构紧凑,在具体设计芯片时,可将VD和第一 flip-flop置于主电源域内,将第一Bushold置于备用电源域内。 [0071] wherein, in order to make the circuit compact, when the specific chip design, and VD may be placed on the first flip-flop within the main power supply, the first power supply in standby Bushold art.

[0072]如图9所示,为本发明实施例五中,主电源VCC、复位信号与隔离信号的时序图,下面结合该时序图对图8所示的芯片如何实现隔离主电源域的信号进行具体说明。 [0072] As shown in FIG 9, the fifth embodiment of the present invention, in conjunction with the VCC main power supply, the reset signal timing diagram of the isolation signal, the next chip timing chart shown in FIG. 8 how the main power domain signal isolation It will be specifically described.

[0073]在VCC下电过程中,VD驱动复位信号为低电平,引起第一 flip-flop的电平信号变为低电平,进而驱动第一Bushold的电平信号翻转为低电平,使隔离器件生效,即控制隔离器件隔离主电源域的信号,以使主电源域的信号无法进入备用电源域。 [0073] In the course of the VCC power, driving the reset signal VD is low, causing the signal level of the first flip-flop goes low, which in turn drives the first Bushold toggles low level signal, to take effect so that isolation devices, i.e. the control signal of the main power supply isolation device isolation region so that the main power supply domain signal entering standby power domain. VCC掉电完成后,第一 flip-flop的电平信号变为高阻状态,第一Bushold的电平信号会继续保持低电平,使隔离器件生效。 VCC power-down after the completion of the first flip-flop of the level of the signal becomes high impedance, Bushold first level signal will remain low, the device isolation effect. 在VCC重新上电后,由程序通过CPU总线设置第一flip-flop的输入信号为高电平,进而驱动第一flip-flop的电平信号及第一Bushold的电平信号成为高电平,以使隔离器件旁路,即使主电源域的信号进入备用电源域。 After the VCC power cycle, the program is provided by a first input signal to the CPU bus flip-flop at a high level, which in turn drives a first flip-flop and the signal level of a first level signal Bushold high level, so that the bypass device isolation, even if the main power domain signal into the standby power domain.

[0074]实施例六 [0074] Sixth Embodiment

[0075]相应的,本发明实施例六提供又一种芯片,其电路原理图如图10所示,信号隔离电路包括:第一flip-flop,所述VD的输出端与所述第一flip-flop的复位端相连接,所述第一flip-flop根据所述VD产生的复位信号,产生一电平信号;第一总线电平保持单元Bushold,所述第一flip-flop的输出端与所述第一Bushold的输入端相连接,所述第一Bushold对所述第一flip-flop产生的电平信号进行电压保持处理,产生一电平信号;第二flip-flop,所述VD的输出端与所述第二flip-flop的复位端相连接,所述第二flip-flop接收到所述VD产生的复位信号后,产生一电平信号;第二Busho Id,所述第二flip-flop的输出端与所述第二Bushold的输入端相连接,所述第二Bushold对所述第二flip-flop产生的电平信号进行电压保持处理,产生一电平信号;第三flip-flop,所述第一Bushold的输出端与所述第三flip-flop的时钟端相连接 [0075] Accordingly, according to a sixth embodiment of the present invention, a further chip, the circuit diagram shown in Figure 10, the signal isolation circuit comprises: a first flip-flop, the output of VD is the first flip -flop reset end connected to said first flip-flop reset signal VD generated by said generating a level signal; a first bus Bushold level holding unit, the first output terminal of the flip-flop Bushold the first connected to the input of said first pair of Bushold the first level signal generated by flip-flop voltage holding process, generating a level signal; a second flip-flop, the VD is after the output terminal connected to the reset terminal of said second flip-flop, the second flip-flop the reset signal is received VD generated, generating a level signal; a second Busho Id, said second flip -flop end and the second output connected to the input Bushold, Bushold the second pair of said second level signal generated by flip-flop voltage holding process, generating a level signal; a third flip- flop, Bushold output of the first and the third flip-flop connected to the clock terminal of ,所述第二Bushold的输出端与所述第三flip-flop的复位端相连接,所述第三flip-flop根据所述第二Bushold产生的电平信号对所述第一Bushold产生的电平信号进行稳压处理,产生一电平信号,所述隔离器件与所述第三flip-flop的输出端相连接,由所述第三fl ip-flop产生的电平信号直接控制隔离器件隔离所述主电源域的信号,以使所述主电源域的信号无法进入所述备用电源域。 , Bushold output of the second and the third flip-flop is connected to the reset terminal of the third flip-flop generating the first Bushold according to the level of a signal generated by a second electrical Bushold level regulator signal processing, generates a level signal, the isolation device and the third flip-flop is connected to the output, the control device isolation isolated directly from the third level of a signal generated fl ip-flop the main power supply domain signals, the main power supply so that the signal can not enter the domain of the standby power domain.

[0076]其中,为了电路结构紧凑,在具体设计芯片时,可将VD、第一flip-flop和第二flip-flop置于主电源域内,将第一BushoId、第二BushoId和第三flip-flop置于备用电源域内。 [0076] wherein, for a compact circuit configuration, when the specific chip design, can VD, the first flip-flop and a second flip-flop is placed within the main power supply, BushoId the first, second and third flip- BushoId flop on standby power supply in the art.

[0077]采用本发明实施例六的信号隔离电路,第三flip-flop的输入端固定接高电平。 [0077] According to the present invention, the signal isolation circuit according to a sixth embodiment, the input terminal of the third flip-flop then high fixation. 这样,VCC下电过程中,VD产生复位信号驱动第二flip-flop输出低电平信号,经第二Bushold输出低电平信号后,驱动第三flip-flop复位输出低电平信号。 Thus, the process of the VCC power, generate a reset signal VD for driving the second flip-flop outputs a low level signal, the second signal Bushold outputs a low level, the reset driving of the third flip-flop outputs a low level signal. 通过增加第三flip-flop可以增强产生稳定低电平信号的可靠性,在VCC下电时,第一Bushold和第二Bushold均输出低电平信号,只有二者同时出现不稳定时,才会干扰到第三flip-flop的电平信号。 Through adding a third flip-flop to produce a stable low level can enhance the reliability of the signal, when the VCC, the first and second Bushold Bushold output low level signals only while both unstable, will interference to the signal level of the third flip-flop. 在VCC下电结束后,即使第一Bushold和第二Bushold中有一个出现不稳定,也不会影响第三flip-flop输出低电平信号。 After the end of the power at the VCC, even if the first and second Bushold has a Bushold unstable, it will not affect the output of the third flip-flop a low level signal. VCC重新上电后,程序通过设定第一flip-flop的输入信号为高电平和第二 flip-flop的输入信号为高电平,可使第三flip-flop输出高电平信号,使隔离器件旁路。 After re-power VCC, the program for setting the input signal to the first flip-flop and a second input signal high flip-flop is high, allows the third flip-flop outputs a high level signal to the isolation bypass device.

[0078]本发明实施例所提出的信号隔离电路,基于数字电路和模拟电路联合设计,具有结构简单,易于整合入芯片,工艺参数不敏感等优点。 [0078] Signal isolation circuit embodiment of the proposed embodiment of the present invention, the digital and analog circuit design based on a joint, having a simple structure, easy to integrate into a chip, is not sensitive to the process parameters and so on.

[0079]如图11所示,为本发明实施例中,一种整体芯片组成示意图,包含电源域I和电源域2,其中,电源域I由主电源VCC供电,可以称之为主电源域,电源域2由备用电源VBAT供电,可以称之为备用电源域。 [0079] 11, the present embodiment 2, wherein the power supply from the main power supply VCC Domain I supply, the main power domain may be referred to the invention, a schematic view of a monolithic chips, comprising a power supply domains and domain I , power domain 2 from the backup power supply VBAT may be called standby power domain. 主电源域中包含CPU,还可以包含直接内存存取(DMA ,DirectMemory Access)存储器、Flash、RAM和NVRAM控制器等,备用电源域中可以包含低压差线性稳压器(LD0,low dropout regulator)、控制电路和NVRAM等。 Main power domain comprises a CPU, it can also comprise a direct memory access (DMA, DirectMemory Access) memory, Flash, RAM and NVRAM controller, backup power domain may comprise a low-dropout linear regulator (LD0, low dropout regulator) , NVRAM, and the control circuit and the like. 隔离器件连接于主电源域与备用电源域之间,用于隔离主电源域的信号,以使主电源域的信号无法进入备用电源域,可以避免主电源域掉电后,对备用电源域产生影响。 Spacer means connected between the main and standby power supply domains domain, signal isolation for the main power supply domain, the main power supply so that the signal domain from entering standby power domain, the domain can be avoided down the main power supply, the standby power generating field influences. 信号隔离电路的复位端与VD的输出端相连接,信号隔离电路的输出端与隔离器件的使能端相连接,用于与隔离器件相配合实现信号隔离。 Output terminal of the reset circuit and signal isolation terminal VD is connected to the output terminal of the isolation device can be a signal terminal of isolation circuit connected to the isolation device cooperating signal isolation.

[0080]本发明实施例所提供的芯片,可以用于实现本发明实施例所提供的信号隔离方法。 The chip according to an embodiment of [0080] the present invention, the method may be used to signal isolation provided by the present embodiment of the invention.

[0081]专业人员还可以进一步应能意识到,结合本文中所公开的实施例描述的各示例的单元及算法步骤,能够以电子硬件、计算机软件或者二者的结合来实现,为了清楚地说明硬件和软件的可互换性,在上述说明中已经按照功能一般性地描述了各示例的组成及步骤。 [0081] professionals may further should be appreciated that, as disclosed herein in conjunction with units and algorithm steps described exemplary embodiments, by electronic hardware, computer software, or a combination thereof. In order to clearly illustrate the interchangeability of hardware and software, in accordance with the foregoing has generally described functional components and steps of each example. 这些功能究竟以硬件还是软件方式来执行,取决于技术方案的特定应用和设计约束条件。 Whether these functions are performed by hardware or software depends upon the particular application and design constraints of the technical solutions. 专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能,但是这种实现不应认为超出本发明实施例的范围。 Professional technical staff may use different methods for each specific application to implement the described functionality, but such implementation should not be considered outside the scope of the embodiments of the present invention.

[0082]结合本文中所公开的实施例描述的方法或算法的步骤可以直接用硬件、处理器执行的软件模块,或者二者的结合来实施。 [0082] The steps of a method or algorithm described in the embodiments disclosed herein may be implemented in hardware, or a combination thereof, in a software module executed by a processor implemented directly.

[0083]对所公开的实施例的上述说明,使本领域专业技术人员能够实现或使用本发明实施例。 [0083] The above description of the disclosed embodiments enables those skilled in the art to make or use embodiments of the present invention. 对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的,本文中所定义的一般原理可以在不脱离本发明实施例的精神或范围的情况下,在其他实施例中实现。 Various modifications to these professionals skilled in the art of the present embodiments will be apparent, and the generic principles defined herein may be made without departing from the spirit or scope of the embodiments of the present invention, be implemented in other embodiments . 因此,本发明实施例将不会被限制于本文所示的这些实施例,而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。 Thus, embodiments of the present invention will not be limited to the embodiments shown herein but is to be accorded herein consistent with the principles and novel features disclosed widest scope.

[0084]以上所述仅为本发明实施例的较佳实施例而已,并不用以限制本发明实施例,凡在本发明实施例的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明实施例的保护范围之内。 [0084] The foregoing is only preferred embodiments of the present invention Example only, not intended to limit embodiments of the present invention, any modification within the spirit and principles of the embodiments of the present invention, equivalent substitutions, improvements shall fall within the protection scope of the embodiments of the present invention.

Claims (4)

  1. 1.一种信号隔离方法,其特征在于,包括: 对为主电源域供电的主电源电压进行检测,当检测出所述主电源电压处于预设电压区段时,产生复位信号,所述主电源域由片上系统SoC的主电源供电; 根据所述复位信号,产生第一电平信号; 根据所述第一电平信号控制隔离器件隔离所述主电源域的信号,以使所述主电源域的信号无法进入备用电源域; 所述方法还包括: 当接收到中央处理器CHJ产生的输入信号后,产生第五电平信号; 根据所述第五电平信号控制隔离器件,使所述主电源域的信号进入所述备用电源域;其中,所述根据所述第一电平信号控制隔离器件隔离所述主电源域的信号,以使所述主电源域的信号无法进入所述备用电源域,包括: 对所述第一电平信号进行电压保持处理,产生第二电平信号; 由所述第二电平信号直接控制隔离器件隔离所述主 A signal isolation method, characterized by comprising: a primary power supply voltage of the main power domains can be detected, when the mains voltage is detected at a preset voltage section that generates a reset signal, the primary power from the main power supply domain system-on-chip SoC; according to the reset signal, generating a first level signal; isolating the main power supply according to the first domain level signal controlling the isolation means, so that said main power supply signal domain can not enter the standby power domain; said method further comprising: after receiving an input signal generated by a central processor CHJ, generate a fifth signal level; according to the fifth level signal controlling the isolation means, the domain signal of the main power supply enters the standby power domain; wherein said main power supply of the signal according to the first domain isolation level signal controlling the isolation means, the main power supply so that the signal can not enter the standby domain domain power, comprising: a signal level of said first voltage holding process, generating a second level signal; isolation devices directly controlled by the main isolating the second level signal 电源域的信号,以使所述主电源域的信号无法进入所述备用电源域;或者, 对所述第一电平信号进行电压保持处理,产生第三电平信号; 对所述第三电平信号进行稳压处理,产生第四电平信号; 由所述第四电平信号直接控制隔离器件隔离所述主电源域的信号,以使所述主电源域的信号无法进入所述备用电源域。 Domain signal power, the main power supply so that the signal domain can not enter the standby power domain; Alternatively, the first level of the signal voltage holding process to generate a third signal level; the third electrical level regulator signal processing to produce a fourth level signal; a control signal isolation means isolating the main power supply directly from the fourth domain level signal, the main power supply so that the signal can not enter the domain of the backup power supply area.
  2. 2.一种信号隔离装置,其特征在于,包括: 电压检测单元,用于对为主电源域供电的主电源电压进行检测,当检测出所述主电源电压处于预设电压区段时,产生复位信号,所述主电源域由片上系统SoC的主电源供电;第一信号产生单元,用于根据所述电压检测单元产生的复位信号,产生第一电平信号;隔离单元,用于根据所述第一信号产生单元产生的第一电平信号控制隔离器件隔离所述主电源域的信号,以使所述主电源域的信号无法进入备用电源域; 还包括: 第五信号产生单元,用于当接收到中央处理器CPU产生的输入信号后,产生第五电平信号; 控制单元,用于根据所述第五信号产生单元产生的第五电平信号控制隔离器件,使所述主电源域的信号进入所述备用电源域; 其中,所述隔离单元具体用于:由所述第一信号产生单元产生的第一电平信号直接控 A signal isolation means, characterized by comprising: a voltage detecting means, based on the main power supply voltage for power domains can be detected, when the mains voltage is detected at a preset voltage segment, generated a reset signal, said main power supply from the main power domain on the SoC chip power; a first signal generating unit, a reset signal according to the detection voltage generating unit generates a first level signal; isolation means, according to the said first signal generating unit generates a first level signal isolation means isolating the control signal of the main power supply domain, the main power supply so that the signal domain from entering standby power domain; further comprising: a fifth signal generating unit, with when receiving the input to the signal generated by the central processing unit CPU generates a fifth level signal; a control unit for controlling the isolation level of the signal V generated by the device according to the fifth signal generating means, the main power supply domain signal into said standby power domain; wherein the isolation unit is configured to: a first level signal generated by the first control signal generation unit directly 制隔离器件隔离所述主电源域的信号,以使所述主电源域的信号无法进入所述备用电源域;或者, 所述隔离单元包括: 第二信号产生子单元,用于对所述第一信号产生单元产生的第一电平信号进行电压保持处理,产生第二电平信号; 第一隔离子单元,用于由所述第二信号产生子单元产生的第二电平信号直接控制隔离器件隔离所述主电源域的信号,以使所述主电源域的信号无法进入所述备用电源域;或者,所述隔离单元包括: 第三信号产生子单元,用于对所述第一信号产生单元产生的第一电平信号进行电压保持处理,产生第三电平信号; 第四信号产生子单元,用于对所述第三信号产生子单元产生的第三电平信号进行稳压处理,产生第四电平信号; 第二隔离子单元,用于由所述第四信号产生子单元产生的第四电平信号直接控制隔离器件隔离所述主电源域 Isolated signal isolation devices made the main power supply domain, the main power supply so that the signal domain can not enter the standby power domain; or the isolation unit comprises: a second sub-signal generating means, for the first a first level signal generating unit generates a signal voltage holding process is performed, generates a second level signal; a first isolation sub-unit, a second level of the signal generated by said second signal generating sub-unit is directly controlled isolation the device isolation domain signal of the main power supply, the main power supply so that the signal domain can not enter the standby power domain; Alternatively, the isolation unit comprises: a third sub-signal generating means for said first signal a first level signal generating unit generates a voltage holding process is performed, generating a third signal level; and a fourth signal generating sub-unit, a third level signal to said third signal generating means generates the sub-process is regulated generating a fourth level signal; and a second isolation sub-unit, for generating a fourth sub-unit level signal generated by the fourth signal to directly control the main power supply isolation device isolation region 的信号,以使所述主电源域的信号无法进入所述备用电源域。 Signal, the main power supply so that the signal can not enter the domain of the standby power domain.
  3. 3.一种芯片,其特征在于,包括: 电压检测器VD,所述VD对为主电源域供电的主电源电压进行检测,当检测出所述主电源电压处于预设电压区段时,产生复位信号;所述主电源域由片上系统SoC的主电源供电;信号隔离电路,所述VD的输出端与所述信号隔离电路的复位端相连接,所述信号隔离电路根据所述VD产生的复位信号,产生一电平信号; 隔离器件,所述信号隔离电路的输出端与所述隔离器件的使能端相连接,由所述信号隔离电路产生的电平信号直接控制隔离器件隔离所述主电源域的信号,以使所述主电源域的信号无法进入备用电源域; 其中,所述信号隔离电路包括: 第一基本电路单元触发器flip-flop,所述VD的输出端与所述第一flip-flop的复位端相连接,所述第一flip-flop根据所述VD产生的复位信号,产生一电平信号,所述第一flip-flop 的输出端与所述隔离 3. A chip, which is characterized in that, comprising: a voltage detector VD, the primary power supply voltage VD of the main power domains can be detected, when the mains voltage is detected at a preset voltage segment, generated a reset signal; said main power supply from the main power source domain SoC chip on a power supply; a signal isolation circuit, and an output terminal of the VD signal to the reset terminal of isolation circuit connected to said signal isolation circuit VD is generated according to the reset signal, generating a level signal; isolation device, the output terminal of said signal separating circuit and the isolator element end connected to the enable level of a signal generated by said signal separating circuit directly controlling the isolation means isolating said domain signal of the main power supply, the main power supply so that the signal domain from entering standby power domain; wherein said signal separating circuit comprises: a first flip-flop circuit unit substantially flip-flop, the output terminal of the VD a first flip-flop is connected to the reset terminal of said first flip-flop the reset signal VD generated, generates a level signal, the first output terminal of the flip-flop is isolated 器件的使能端相连接,由所述第一flip-flop 产生的电平信号直接控制隔离器件隔离所述主电源域的信号,以使所述主电源域的信号无法进入所述备用电源域; 所述信号隔离电路还包括: 第一总线电平保持单元Busho Id,所述第一flip-flop的输出端与所述第一Busho Id的输入端相连接,所述第一Busho Id对所述第一flip-flop产生的电平信号进行电压保持处理,产生一电平信号,所述第一Bushold的输出端与所述隔离器件的使能端相连接,由所述第一Bushold产生的电平信号直接控制隔离器件隔离所述主电源域的信号,以使所述主电源域的信号无法进入所述备用电源域; 所述信号隔离电路还包括: 第二flip-flop,所述VD的输出端与所述第二flip-flop的复位端相连接,所述第二flip-flop接收到所述VD产生的复位信号后,产生一电平信号; 第二Bushold,所述第二flip-flop的输出端与所述第 Enabled end devices connected to the level signal generated by said first flip-flop signal directly controlling the isolation means isolating the main power supply domain, the main power supply so that the signal can not enter the domain of the standby power domain ; said signal separating circuit further comprises: a first bus Busho Id level holding unit, the output of the first flip-flop is connected to the first input terminal Id Busho, the first of their Busho Id said first level signal generated by flip-flop voltage holding process, generates a level signal, the first output terminal Bushold the isolation device is enabled end connected to said first generated by the Bushold level of the signal directly control the signal isolation means isolating the main power supply domain, the main power supply so that the signal domain can not enter the standby power domain; said signal separating circuit further comprises: a second flip-flop, the VD the output terminal connected to the reset terminal of said second flip-flop, the second flip-flop the reset signal is received VD generated, generating a level signal; a second Bushold, said second flip and an output terminal of the first -flop Bushold的输入端相连接,所述第二Bushold对所述第二flip-flop产生的电平信号进行电压保持处理,产生一电平信号;第三flip-flop,所述第一Bushold的输出端与所述第三flip-flop的时钟端相连接,所述第二Bushold的输出端与所述第三flip-flop的复位端相连接,所述第三flip-flop根据所述第二Bushold产生的电平信号对所述第一Bushold产生的电平信号进行稳压处理,产生一电平信号,所述隔离器件与所述第三flip-flop的输出端相连接,由所述第三flip-flop产生的电平信号直接控制隔离器件隔离所述主电源域的信号,以使所述主电源域的信号无法进入所述备用电源域。 Bushold connected to the input of the second pair of Bushold said second level signal generated by flip-flop voltage holding process, generating a level signal; a third flip-flop, said first output terminal Bushold end connected to the third flip-flop clock output terminal of the second Bushold and resetting the flip-flop of the third end connected to said third flip-flop is generated according to the second Bushold the level of the signal level of the signal generated by the first regulator Bushold be processed to produce a level signal, the isolation device and the output terminal of the third flip-flop is connected, by the third flip level of the signal is directly generated -flop control signal isolation means isolating the main power supply domain, the main power supply so that the signal can not enter the domain of the standby power domain.
  4. 4.如权利要求3所述的芯片,其特征在于,还包括: 中央处理器CPU,所述CPU置于主电源域中,所述信号隔离电路的输入端与所述CPU总线相连接,当为主电源域供电的主电源上电后,由所述CPU控制所述信号隔离电路,产生一电平信号,由所述信号隔离电路产生的电平信号控制隔离器件导通所述主电源域的信号,使所述主电源域的信号进入所述备用电源域。 4. The chip according to claim 3, characterized in that, further comprising: a central processing unit CPU, a main CPU in the power domain, said input signal and said isolation circuit is connected to CPU bus, when after the main power supply of the main power supply domain, by the CPU controls said signal separating circuit for generating a level signal, turns on the level of a signal generated by said signal separating circuit controls a main power domain isolation component signal, a signal entering the domain of the main power supply backup power domain.
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CN101478174A (en) * 2008-01-04 2009-07-08 中兴通讯股份有限公司 State detection system and method for DC electric power

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