CN102654828A - Method for increasing response speed of analog adder, analog adder and transformer - Google Patents
Method for increasing response speed of analog adder, analog adder and transformer Download PDFInfo
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Abstract
The invention discloses a method for increasing the response speed of an analog adder, an analog adder and a transformer. The analog adder at least comprises an operational transconductance amplifier; the operational transconductance amplifier is provided with a first input end not connected with an output level circuit and a second input end connected with the output level circuit; by changing the current of the branch of the first input end in the operational transconductance amplifier, the circuit of the output level circuit generates current, thus a switching tube in the output level circuit works in a saturated area; and particularly, when the application circuit of the analog adder is in a no-load or light-load state, the switching tube in the output level circuit can work in the saturated area. Compared with the traditional analog adder, the time for the switching tube in the output level circuit transiting from a cut-off area to the saturated area when the application circuit of the traditional analog adder is in a light-load or no-load state is saved, thus the response speed of the analog adder is greatly increased, and the application range of the analog adder is expanded..
Description
The application's claim 4-8 requires to submit on 06 30th, 2011 Patent Office of the People's Republic of China, application number 201110183130.X; Denomination of invention is the right of priority of the one Chinese patent application of " a kind of analog adder and current mode step-up transformer ", and its full content combines in this application by reference.
Technical field
The application relates to the adder circuit technical field, particularly relates to method, analog adder and the transformer of accelerating the analog adder response speed.
Background technology
Analog adder is used for offset voltage, compensation ramp voltage, sensing voltage are added up; Wherein, Said offset voltage is that the difference for fear of earth terminal current potential between the interference of earth terminal or each module of inside circuit causes that the output signal of totalizer incurs loss in transmission, the jagged compensation oblique wave that said compensation ramp voltage signal is and the clock signal period of oscillator takes place synchronously; Said sensing voltage is electric current and the product of sampling resistor that flows through the coil of current mode transformer, and this sensing voltage has reacted and the corresponding electric current change conditions of the load of circuit.
In the OTA in the conventional analogue totalizer; At the sensing voltage of input hour; The switching tube of output-stage circuit is in cut-off state; It is chronic that switching tube needs from the cut-off region to the saturation region, makes the output current of conventional analogue totalizer can not follow the input signal variation well, and promptly the response speed of analog adder is slow; Can not be advantageously applied in the circuit of the frequent switch of current loading; Can not be advantageously applied in the current mode transformer that is operated under CCM (Continuous Conduction Mode, continuous conduction mode), critical mode of operation or three kinds of mode of operations of DCM (Discontinuous Conduction Mode, discontinuous conduction mode).
Summary of the invention
For solving the problems of the technologies described above, the application embodiment provides a kind of method, analog adder and transformer of accelerating the analog adder response speed, with the response speed of raising analog adder, and enlarging application range, technical scheme is following:
A kind of method of accelerating the analog adder response speed; Be applied to analog adder; This analog adder comprises at least: OTA; This OTA has first input end that is not connected with output-stage circuit and second input end that is connected with output-stage circuit, and this method comprises:
Change the electric current in the branch road of said first input end place,, make that the switching tube in the said output-stage circuit is operated in the saturation region so that produce electric current between said output-stage circuit and said second input end place branch road.
Preferably, the electric current in the branch road of the said first input end of said change place comprises:
Offset current source in the said analog adder is linked to each other with said first input end place branch road, to increase the electric current in this branch road.
Preferably, the electric current in the branch road of the said first input end of said change place comprises:
Change the position relation of bias current sources place branch road and said first input end place branch road in the said analog adder, flow through the electric current that said first input end belongs to current-limiting resistance in the branch road with increase.
The present invention also provides a kind of analog adder; Comprise: OTA, offset current source, first output resistance; Wherein, said OTA has the first input end that is not connected with output-stage circuit, and second input end that is connected with output-stage circuit;
Second input end of said OTA connects earth terminal; First input end has sensing voltage for the input end input of this analog adder; Output terminal is connected to the hot end of said first output resistance through the first mos field effect transistor metal-oxide-semiconductor; The other end ground connection of said first output resistance, the hot end of this first output resistance are the output terminal of this analog adder;
Said offset current source is connected with the first input end place branch road of said OTA, so that the switching tube in the said output-stage circuit is operated in the saturation region.
Preferably, also comprise: compensation oblique wave current source, second output resistance, wherein,
Said compensation oblique wave current source links to each other with the hot end of said first output resistance through said second output resistance, and the hot end of this second output resistance is as the output terminal of this analog adder.
Preferably, said OTA comprises: the first cascade bias unit, input stage circuit, output-stage circuit and backfeed loop, wherein:
The said first cascade bias unit links to each other with said input stage circuit, and the metal-oxide-semiconductor that is used to said input stage circuit provides bias current;
Said input stage circuit comprises: second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor are connected the feedback resistance of the said second metal-oxide-semiconductor source electrode, and second input resistance that is connected said the 3rd metal-oxide-semiconductor source electrode, the mirror current source of formation;
Said output-stage circuit also comprises: the 4th metal-oxide-semiconductor that is connected in series with said the 5th metal-oxide-semiconductor; Wherein, The drain electrode of said the 5th metal-oxide-semiconductor connects the 4th metal-oxide-semiconductor, and the grid of said the 5th metal-oxide-semiconductor links to each other with the drain electrode of said the 3rd metal-oxide-semiconductor, and the grid of the 5th metal-oxide-semiconductor connects said offset current source;
Said backfeed loop comprises: said first metal-oxide-semiconductor and the 5th metal-oxide-semiconductor, and the grid of said first metal-oxide-semiconductor connects the drain electrode of said the 5th metal-oxide-semiconductor, and the source electrode of said the 5th metal-oxide-semiconductor is connected to the hot end of said feedback resistance.
Preferably; The source electrode of the 4th metal-oxide-semiconductor in the said output-stage circuit connects dc positive power; The grid of said the 4th metal-oxide-semiconductor connects the drain electrode of the 4th metal-oxide-semiconductor, and the drain electrode of the 4th metal-oxide-semiconductor connects the drain electrode of said the 5th metal-oxide-semiconductor, and the source electrode of said the 5th metal-oxide-semiconductor connects the hot end of said feedback resistance; The grid of said the 5th metal-oxide-semiconductor connects the drain electrode of said the 3rd metal-oxide-semiconductor, and the grid of the 5th metal-oxide-semiconductor links to each other with said offset current source;
The grid of said first metal-oxide-semiconductor connects the grid of said the 4th metal-oxide-semiconductor, and the source electrode of said first metal-oxide-semiconductor connects dc positive power, and the drain electrode of said first metal-oxide-semiconductor connects the hot end of said second output resistance.
Preferably, also comprise: be connected the second cascade bias unit between said first cascade bias unit and the said input stage circuit, wherein,
The said first cascade bias unit comprises: first bias current sources, the 6th metal-oxide-semiconductor, the 7th metal-oxide-semiconductor and the 8th metal-oxide-semiconductor, wherein:
The source electrode of said the 6th metal-oxide-semiconductor connects dc positive power, and drain electrode connects the negative output terminal of said bias current sources, the positive output end ground connection of said bias current sources;
The grid of said the 7th metal-oxide-semiconductor connects the grid of said the 6th metal-oxide-semiconductor, and the source electrode of said the 7th metal-oxide-semiconductor connects said dc positive power, and the drain electrode of said the 7th metal-oxide-semiconductor connects the drain electrode of said second metal-oxide-semiconductor;
The grid of said the 8th metal-oxide-semiconductor connects the grid of said the 6th metal-oxide-semiconductor, and the source electrode of said the 8th metal-oxide-semiconductor connects said dc positive power, and the drain electrode of said the 8th metal-oxide-semiconductor connects the drain electrode of said the 3rd metal-oxide-semiconductor;
The said second cascade bias unit comprises: second bias current sources, the 9th metal-oxide-semiconductor, the tenth metal-oxide-semiconductor and the 11 metal-oxide-semiconductor, wherein,
The grid of said the 9th metal-oxide-semiconductor is connected with drain electrode, and should drain electrode connect said second bias current sources;
Said the tenth metal-oxide-semiconductor is serially connected between said the 7th metal-oxide-semiconductor and second metal-oxide-semiconductor, and the grid of said the tenth metal-oxide-semiconductor is connected with the grid of said the 9th metal-oxide-semiconductor;
Said the 11 metal-oxide-semiconductor is connected in series between said the 8th metal-oxide-semiconductor and the 3rd metal-oxide-semiconductor, and the grid of said the 11 metal-oxide-semiconductor is connected with the grid of said the 9th metal-oxide-semiconductor.
The present invention also provides a kind of analog adder, comprising: OTA and bias current sources, and wherein, said OTA has the first input end that does not link to each other with output-stage circuit, and second input end that links to each other with output-stage circuit;
Second input end of said OTA is as the input end of this analog adder, and input has sensing voltage, and said first input end input has input voltage, and output terminal is as the output terminal of this analog adder;
Said bias current sources is connected in second input end of said OTA, so that the switching tube in the said output-stage circuit is operated in the saturation region.
Preferably, also comprise: the compensation oblique wave current source that is connected the output terminal of said OTA.
Preferably, said OTA comprises: input stage circuit and output-stage circuit, wherein,
Said input stage circuit comprises: first resistance, second resistance, the first cascade bias unit, the second cascade bias unit and first metal-oxide-semiconductor, wherein,
First branch road of the said first cascade bias unit connects said bias current sources; Second branch road connects first branch road of the said second cascade bias unit; And this second branch road links to each other with an end of said first resistance, and the other end of said first resistance is as the in-phase input end of this OTA;
Second branch road of the said second cascade bias unit connects first end of said first metal-oxide-semiconductor, and first end of this first metal-oxide-semiconductor connects an end of said second resistance, and second end of this second resistance is as the inverting input of this OTA;
Said output-stage circuit comprises: the 6th metal-oxide-semiconductor and sampling resistor, wherein,
First end of said the 6th metal-oxide-semiconductor connects second end of said first metal-oxide-semiconductor; Second end of said the 6th metal-oxide-semiconductor connects earth terminal through said sampling resistor; This second end connects said compensation oblique wave current source, and this second end output terminal that is said OTA.
Preferably, the said first cascade bias unit comprises: second metal-oxide-semiconductor and the 3rd metal-oxide-semiconductor, wherein,
The grid of said second metal-oxide-semiconductor links to each other with first end, and said grid connects the grid of said the 3rd metal-oxide-semiconductor, and first end of second metal-oxide-semiconductor connects said offset current source, and second end of said second metal-oxide-semiconductor connects second end of said the 3rd metal-oxide-semiconductor;
First end of said the 3rd metal-oxide-semiconductor connects first branch road of said second cascode amplifier, and second end of the 3rd metal-oxide-semiconductor is the in-phase input end of this OTA;
The said second cascade bias unit comprises: the 4th metal-oxide-semiconductor and the 5th metal-oxide-semiconductor, wherein,
The grid of said the 4th metal-oxide-semiconductor links to each other with first end; And the grid of said the 4th metal-oxide-semiconductor connects the grid of said the 5th metal-oxide-semiconductor; First end of said the 4th metal-oxide-semiconductor connects second branch road of said first cascode amplifier, and second end of said the 4th metal-oxide-semiconductor connects earth terminal;
First end of said the 5th metal-oxide-semiconductor connects first end of said first metal-oxide-semiconductor, and second end of the 5th metal-oxide-semiconductor connects earth terminal.
The present invention also provides a kind of analog adder, comprising: OTA and offset current source, wherein:
Said OTA comprises input stage circuit and output-stage circuit; And have first input end, second input end and output terminal; Wherein, Said first input end is not connected with output-stage circuit, said second input end is connected with output-stage circuit, and said output terminal is the output terminal of this analog adder;
Said offset current source is connected in said first input end place branch road, so that the switching tube in the said output-stage circuit is operated in the saturation region.
The present invention also provides a kind of transformer; Comprise error amplifier, pulse width modulation (PWM) comparer, pwm control circuit and metal-oxide-semiconductor; Also comprise: above-mentioned analog adder; The sensing voltage input end of this analog adder is connected to the source electrode of said metal-oxide-semiconductor, and the output terminal of this analog adder is connected to the in-phase input end of said PWM comparer.
The present invention also provides a kind of transformer; Comprise error amplifier, pulse width modulation (PWM) comparer, pwm control circuit and metal-oxide-semiconductor; Also comprise: above-mentioned analog adder; The sensing voltage input end of this analog adder connects the drain electrode of said switching tube, and the output terminal of analog adder is connected to the in-phase input end of said PWM comparer.
Technical scheme by above the application embodiment provides is visible; Said analog adder comprises at least: OTA, and this OTA has the first input end that is not connected with output-stage circuit, and second input end that is connected with output-stage circuit; Through changing the electric current in the first input end place branch road in the said OTA; So that produce electric current in the circuit of said output-stage circuit place, thus make the switching tube in the said output-stage circuit be operated in the saturation region, especially when the application circuit of this analog adder is in zero load or underloading; Just can make the switching tube in the output-stage circuit be operated in the saturation region; Compare with the conventional analogue totalizer, the application circuit that has saved the conventional analogue totalizer is when underloading or zero load, and the switching tube in the output-stage circuit carries out the transition to the needed time of saturation region from cut-off region; Thereby improved the response speed of analog adder greatly, enlarged the scope of application of this analog adder.
Description of drawings
In order to be illustrated more clearly in the application embodiment or technical scheme of the prior art; To do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below; Obviously, the accompanying drawing in describing below only is some embodiment that put down in writing among the application, for those of ordinary skills; Under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the circuit theory synoptic diagram of a kind of analog adder of the application embodiment;
Fig. 2 is the physical circuit synoptic diagram of a kind of analog adder of the application embodiment;
Fig. 3 is the waveform synoptic diagram of the input/output signal of analog adder shown in Figure 2;
Fig. 4 is the circuit theory synoptic diagram of the another kind of analog adder of the application embodiment;
Fig. 5 is the physical circuit synoptic diagram of analog adder shown in Figure 4;
Fig. 6 is the circuit theory synoptic diagram of the another kind of analog adder of the application embodiment;
Fig. 7 is the physical circuit synoptic diagram of analog adder shown in Figure 6;
Fig. 8 is the structural representation of a kind of transformer of the application embodiment;
Fig. 9 is the structural representation of the another kind of transformer of the application embodiment.
Embodiment
The application embodiment provides a kind of method of accelerating the analog adder response speed; Said analog adder comprises at least: OTA; This OTA has the first input end that is not connected with output-stage circuit, and second input end that is connected with output-stage circuit, and this method specifically comprises: change the electric current in the branch road of said first input end place; So that output-stage circuit place branch road produces electric current, make that the switching tube in the output-stage circuit is operated in the saturation region.
During practical implementation, the electric current in the above-mentioned change first input end place branch road comprises following two kinds of situation at least:
A kind of situation is the offset current source in the said analog adder to be connected with said first input end place branch road, thereby to increase the electric current in the branch road of said first input end place.
Because the electric current in the said OTA in first input end place branch road and second input end place branch road is managed balance all the time; Therefore; When the electric current in the branch road of said first input end place increases; And the structure of second input end place branch road does not change, and therefore, produces electric current from the branch road between output-stage circuit and said second input end; And flow through said second input end place branch road, the electric current in the branch road of second input end place is equated with the electric current that said first input end belongs in the branch road.In this process, owing to produce electric current in the branch road of said output-stage circuit place, thus make the switching tube in the output-stage circuit be operated in the saturation region.
Another kind of situation is; The position that changes bias current sources place branch road and said first input end place branch road in the said analog adder concerns; Flow through the electric current of current-limiting resistance in the branch road of said first input end place with increase, thereby make the switching tube in the output-stage circuit be operated in the saturation region.
Concrete, increase the electric current of current-limiting resistance in the branch road of said first input end place after because the electric current of first input end electric current and said second input end remains balance; Therefore; The electric current that flows through current-limiting resistance in the branch road of said second input end place also must be followed increase, and therefore, output-stage circuit place branch road produces electric current; And flow through said second input end place branch road; Thereby the electric current that flows through current-limiting resistance in said second input end is increased, finally make electric current and the current balance type of second input end of the first input end of OTA, in this process; Owing to produce electric current in the branch road of said output-stage circuit place, be that switching tube in the output-stage circuit is operated in the saturation region thereby make.
The method of the response speed of the quickening analog adder that the application embodiment provides; Through changing the electric current in the first input end place branch road in the said OTA; So that produce electric current in the circuit of said output-stage circuit place, thus make the switching tube in the said output-stage circuit be operated in the saturation region, especially when the application circuit of this analog adder is in zero load or underloading; Just can make the switching tube in the output-stage circuit be operated in the saturation region; Compare with the conventional analogue totalizer, the application circuit that has saved the conventional analogue totalizer is when underloading or zero load, and the switching tube in the output-stage circuit carries out the transition to the needed time of saturation region from cut-off region; Thereby improved the response speed of analog adder greatly, enlarged the scope of application of this analog adder.
Corresponding to the method for above-mentioned quickening analog adder response speed, the application embodiment also provides corresponding analog adder.
In order to make those skilled in the art person understand the technical scheme among the application better; To combine the accompanying drawing among the application embodiment below; Technical scheme among the application embodiment is carried out clear, intactly description; Obviously, described embodiment only is the application's part embodiment, rather than whole embodiment.Based on the embodiment among the application, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all should belong to the scope of the application's protection.
See also Fig. 1; Show a kind of circuit theory synoptic diagram of analog adder; This analog adder mainly comprises: OTA 100, offset current source 121, a MOS (Metal OxidSemiconductor; Mos field effect transistor) pipe M1, the first output resistance R1, wherein:
Output-stage circuit comprises metal-oxide-semiconductor 105 and metal-oxide-semiconductor 106, and the grid of metal-oxide-semiconductor 106 is connected to the grid of the first metal-oxide-semiconductor M1, and the output current of this OTA 100 is passed to the first metal-oxide-semiconductor M1 through metal-oxide-semiconductor 105 and metal-oxide-semiconductor 106.Simultaneously, the source electrode of metal-oxide-semiconductor 106 is connected to the first input end of this OTA, forms backfeed loop, thereby guarantees OTA 100 operate as normal.
The drain electrode of the first metal-oxide-semiconductor M1 is through the first output resistance R1 ground connection, and the source electrode of the first metal-oxide-semiconductor M1 connects dc positive power VDD.The hot end of said first output resistance is the output terminal of this analog adder.
Offset current source 121 is connected the first input end place branch road of said OTA, and this first input end place branch road is connected with output-stage circuit, and promptly this offset current source 121 is connected the grid of said metal-oxide-semiconductor 106.
After offset current source 121 being connected the first input end place branch road of said OTA, the amplification of the electric current in the said first input end is the size in offset current source 121, because the first input end of OTA and the electric current in second input end balance all the time; And the circuit structure of second input end place branch road does not change; Therefore, the electric current in this branch road does not change yet, at this moment; For keeping the electric current in the first input end and second input end to keep balance; The output-stage circuit place branch road that is connected with said second input end produces electric current, and flows through said second input end place branch road, thereby the electric current of second input end is increased; And the electric current of final and said first input end balances each other; In this process, produce electric current in the branch road at output-stage circuit place, make that the switching tube in the output-stage circuit is operated in state of saturation.Especially; When the application circuit of analog adder is operated in zero load or underloading; Switching tube in the output-stage circuit just is operated in state of saturation; Make the output signal of this analog adder can follow well input sensing voltage variation and change, promptly improved the response speed of analog adder.
Preferably; See also Fig. 1, this analog adder also comprises compensation oblique wave current source 122, the second output resistance R2; Wherein, Said compensation oblique wave current source 122 links to each other with the hot end of said first output resistance through the said second output resistance R2, at this moment, and with the hot end of the second output resistance R2 output terminal as said analog adder.
Seeing also Fig. 2, show the physical circuit synoptic diagram that the application embodiment provides analog adder, is a kind of concrete embodiment of the corresponding embodiment of Fig. 1; This analog adder comprises: OTA 100, offset current source 121, compensation oblique wave current source 122, the first output resistance R1 and the second output resistance R2; The first metal-oxide-semiconductor M1, wherein, said compensation oblique wave current source 122; Be to rise since 0 with certain slope, the control signal of exporting up to pwm control circuit is a low level, and the first metal-oxide-semiconductor M1 ends; Then, compensation oblique wave current source 122 reduces to 0.Electric current descending slope on described certain slope and the inductance L, cycle of OSC clock signal etc. are relevant.
The effect of OTA 100 is that the voltage signal that second input end is imported is sensing voltage VSN; Convert current signal output into, said OTA 100 comprises: input stage circuit, output-stage circuit, backfeed loop and the first cascade bias unit 110.
The voltage that the electric current of OTA output, said offset current source 121 and compensation oblique wave current source 122 produce on the first output resistance R1 superposes, thereby obtains the output signal of this analog adder.
The said first cascade bias unit 110 comprises first bias current sources, 111, the six metal-oxide-semiconductors 112, the 7th metal-oxide-semiconductor 113 and the 8th metal-oxide-semiconductor 114, wherein:
Said first bias current sources 111 is that second metal-oxide-semiconductor 101 provides bias current through the 7th metal-oxide-semiconductor 113; Simultaneously; First bias current sources 111 is that the 3rd metal-oxide-semiconductor 102 provides bias current through the 8th metal-oxide-semiconductor 114; Thereby, guarantee the saturation region that is operated in of second metal-oxide-semiconductor 101 and the 3rd metal-oxide-semiconductor 102.
Concrete; First bias current sources, 111 1 end ground connection, the other end is connected to the drain electrode of said the 6th metal-oxide-semiconductor 112, simultaneously; The drain electrode of the 6th metal-oxide-semiconductor 112 links to each other with grid; The grid of the 6th metal-oxide-semiconductor 112 is connected to the grid of said the 7th metal-oxide-semiconductor 113, and the drain electrode of the 7th metal-oxide-semiconductor 113 connects the drain electrode of said second metal-oxide-semiconductor 101, and the source electrode of the 7th metal-oxide-semiconductor 113 connects dc positive power VDD; The grid of the 8th metal-oxide-semiconductor 114 connects the grid of the 6th metal-oxide-semiconductor 112, and the source electrode of the 8th metal-oxide-semiconductor 114 connects dc positive power VDD, and the drain electrode of the 8th metal-oxide-semiconductor 114 connects the drain electrode of said the 3rd metal-oxide-semiconductor 102.
Said input stage circuit comprises: second metal-oxide-semiconductor 101, the 3rd metal-oxide-semiconductor 102, feedback resistance R103, the second input resistance R104.
Concrete, the drain electrode of second metal-oxide-semiconductor 101 links to each other with grid, and simultaneously, the drain electrode of second metal-oxide-semiconductor 101 links to each other with the drain electrode of the 7th metal-oxide-semiconductor 113, and the source electrode of second metal-oxide-semiconductor 101 is as the inverting input of this OTA, through resistance R 103 ground connection;
The drain electrode of the 3rd metal-oxide-semiconductor 102 links to each other with grid; Simultaneously; The drain electrode of the 3rd metal-oxide-semiconductor 102 links to each other with the drain electrode of the 8th metal-oxide-semiconductor 114, and the source electrode of the 3rd metal-oxide-semiconductor 102 has said sensing voltage VSN as the in-phase input end of this OTA through resistance R 104 inputs.
Said output-stage circuit comprises: the 4th metal-oxide-semiconductor 105 that is connected in series and the 5th metal-oxide-semiconductor 106.
The grid of said the 4th metal-oxide-semiconductor 105 connects the drain electrode of the 4th metal-oxide-semiconductor 105, and source electrode connects dc positive power VDD, and drain electrode connects the drain electrode of said the 5th metal-oxide-semiconductor 106.
The source electrode of said the 5th metal-oxide-semiconductor 106 connects the common port of said second metal-oxide-semiconductor 101 and resistance R 103; The grid of the 5th metal-oxide-semiconductor 106 connects the drain electrode of said the 3rd metal-oxide-semiconductor 102; Simultaneously, said offset current source 121 is connected to the drain electrode of said the 3rd metal-oxide-semiconductor 102, promptly connects the grid of the 5th metal-oxide-semiconductor 106; The electric current that flows through on the 4th metal-oxide-semiconductor 105 and the 5th metal-oxide-semiconductor 106 equates; And be the output current of this OTA, the electric current on the 4th metal-oxide-semiconductor 105 feeds back to the first input end of this OTA through resistance R 103, forms a closed-loop system.
At sensing voltage VSN is 0 o'clock, and first bias current sources 111 rationally is set, and the 5th metal-oxide-semiconductor 106 is chosen suitable breadth length ratio, can guarantee that so all metal-oxide-semiconductors in the OTA all are operated in the saturation region.
The output terminal of OTA is connected to the grid of the first metal-oxide-semiconductor M1; The source electrode of this first metal-oxide-semiconductor M1 connects dc positive power VDD; Drain electrode connects the hot end of the first output resistance R1; The other end ground connection of the first output resistance R1, compensation oblique wave current source 122 is connected to the hot end of the first output resistance R1 through the second output resistance R2, and then compensating ramp voltage is 122 * (R1+R2).
The hot end of the second output resistance R2 i.e. the output terminal VADD of this analog adder; Suppose that the 4th MOS105 pipe and the breadth length ratio of the first metal-oxide-semiconductor M1 are 1: 1; In the current mode step-up transformer of the frequent switch of current loading; Compensation oblique wave current source 122 increases progressively since 0, so hypothesis compensation oblique wave current source 122 is 0, then the voltage exported of this analog adder is:
VADD＝(VSN/R
104+I
121)×R1+I
122×(R1+R2)
=(VSN/R
104+ I
121) * R1 (formula 1)
Fig. 3 is the input and output waveform synoptic diagram of analog adder shown in Figure 2, and the VSN among the figure is the corresponding waveform of input signal VSN, and VADD promptly exports the corresponding waveform of signal VADD.
When the current mode step-up transformer is operated in critical mode of operation; Compensation oblique wave current source 122 is 0; And offset current source 121 equates that with first bias current sources 111 resistance of feedback resistance R103, the second input resistance R104 and the second output resistance R2 is all equal, i.e. R103=R104=R2.The input signal VSN of analog adder rises to 50mV from 0mV in 500ns, at t=0 constantly, and VADD=I
121* R
2, hence one can see that, and the output signal VADD of analog adder can be good at following input signal VSN to be changed.And; Sensing voltage VSN initial value in input is in 0 the step response; The response speed of the analog adder that present embodiment provides is obviously faster than the step response speed of existing analog adder; Because at the sensing voltage VSN initial value annex of input, the bandwidth that the analog machine that present embodiment provides is initiated is far longer than the bandwidth of analog adder in the prior art.
Need to prove that said first metal-oxide-semiconductor in the foregoing description, said the 4th metal-oxide-semiconductor, said the 6th metal-oxide-semiconductor, said the 7th metal-oxide-semiconductor and said the 8th metal-oxide-semiconductor are the PMOS pipe.To sum up can know; The analog adder that present embodiment provides; Through the offset current source being connected the inside of OTA, all metal-oxide-semiconductors all are operated in the saturation region in the OTA thereby can make, thereby the response speed that has improved this analog adder is fast; Make this analog adder can be applicable in the application circuit of the frequent switch of current loading, and might be operated in the application circuit under CCM, critical mode of operation or three kinds of patterns of DCM.
Preferably; See also Fig. 2; The analog adder that the application embodiment provides also comprises: the second cascade bias unit 130; Effect is the output impedance that improves the mirror current source of mainly being made up of second metal-oxide-semiconductor 101 and the 3rd metal-oxide-semiconductor 102 in the OTA, so that the performance of this analog adder of following adopted formula computational analysis.
This second cascade bias unit mainly comprises: the 9th metal-oxide-semiconductor 131, the tenth metal-oxide-semiconductor the 132, the 11 metal-oxide-semiconductor 133, and second bias current sources 134, wherein:
The grid of said the 9th metal-oxide-semiconductor 131 is connected with drain electrode, and should drain electrode connect said second bias supply 134, and source electrode connects dc positive power VDD.
Said the tenth metal-oxide-semiconductor 132 is serially connected between said the 7th metal-oxide-semiconductor 113 and second metal-oxide-semiconductor 101; The source electrode of the tenth metal-oxide-semiconductor 132 connects the drain electrode of said the 7th metal-oxide-semiconductor 113; The drain electrode of the tenth metal-oxide-semiconductor 132 connects the drain electrode of said second metal-oxide-semiconductor 101, and the grid of the tenth metal-oxide-semiconductor 132 is connected with the grid of said the 9th metal-oxide-semiconductor 131;
Between said the 11 metal-oxide-semiconductor 133 said the 8th metal-oxide-semiconductors of serial connection and the 3rd metal-oxide-semiconductor; The source electrode of the 11 metal-oxide-semiconductor 133 connects the drain electrode of said the 8th metal-oxide-semiconductor 114; The drain electrode of the 11 metal-oxide-semiconductor 133 connects the drain electrode of said the 3rd metal-oxide-semiconductor 102, and the grid of the 11 metal-oxide-semiconductor 133 is connected with the grid of said the 9th metal-oxide-semiconductor 131.The summation of the stray capacitance that electric capacity 135 expression a are ordered, its value is C
Par
The output of OTA 100 is the current signals on the 4th metal-oxide-semiconductor 105, feeds back to the first input end of OTA 100 through resistance R 103, forms a voltage input, the closed-loop system of electric current output.
When present embodiment provided the input signal of analog adder to comprise step signal and ramp signal, the error that the step input is produced was exponential damping, and the error that the slope input is produced, but along with the time is exponential increase.Yet in the current mode step-up transformer, the frequency of analog adder work is the frequency that receives the clock signal OSC of oscillator; And the restriction of dutycycle D; Thereby the error that can make analog adder is a very little value all the time, therefore; When the analog adder that the application embodiment provides was applied in the transformer, the error of generation can be controlled near the very little value.
To sum up; The application embodiment provides is applicable to the analog adder in the current mode step-up transformer; The response speed that at the input signal initial value is 0 step response is far away faster than existing analog adder, and output error can be controlled near the very little value.
To introduce the application embodiment below in detail another kind of analog adder also will be provided
As shown in Figure 4, this analog adder comprises: OTA 110, bias current sources 120, wherein:
Said OTA has the first input end 111 that does not link to each other with output-stage circuit, and second input end 112 that links to each other with output-stage circuit.
Second input end, 112 inputs of said OTA 110 have sensing voltage VSN, and first input end 111 is the input end of this analog adder, and input has input voltage VIN, and output terminal is as the output terminal of this analog adder.
Said bias current sources 120 is connected on second input end of said OTA, to increase the electric current on the current-limiting resistance in the branch road of said first input end place, so that the switching tube in the said output-stage circuit is operated in the saturation region.
The analog adder that present embodiment provides is after the said first input end 111 of increase belongs to the electric current of current-limiting resistance R119 in the branch roads, because the electric current of first input end 111 and the electric current of said second input end 112 remain balance; Therefore; The electric current that flows through current-limiting resistance in said second input end, the 112 place branch roads also must be followed increase, at this moment, produces electric current by output-stage circuit place branch road; And flow through said second input end 112 place branch roads; Thereby the electric current that flows through current-limiting resistance R118 in said second input end 112 is increased, finally make electric current and the current balance type of second input end 112 of the first input end 111 of OTA, in this process; Owing to produce electric current in the branch road of said output-stage circuit place, be that switching tube 121 in the output-stage circuit is operated in the saturation region thereby make.
Preferably; This analog adder also comprises compensation oblique wave current source 130; Compensation oblique wave current source 130 is and the cycle synchronisation of the clock signal OSC of oscillator, and jagged compensation oblique wave electric current takes place, and is used for sensing voltage is revised; Make dutycycle greater than 50% o'clock, subharmonic oscillation can not take place.
Seeing also Fig. 5, show a kind of physical circuit synoptic diagram of analog adder, is a kind of particular circuit configurations of analog adder shown in Figure 4.
This analog adder comprises: OTA 110, bias current sources 120, and compensation oblique wave current source 130, wherein, said bias current sources 120 also can be thought the offset current source.
Said OTA 110 comprises input stage circuit and output-stage circuit.
Said input stage circuit comprises: the first current-limiting resistance R119, the second current-limiting resistance R118, the first cascade bias unit, the second cascade bias unit and first metal-oxide-semiconductor 113.
The said first cascade bias unit comprises: second metal-oxide-semiconductor 114 and the 3rd metal-oxide-semiconductor 115, and the breadth length ratio of two pipes is 1: 1.
The grid of said second metal-oxide-semiconductor 114 is connected with first end; Simultaneously; This grid links to each other with the grid of said the 3rd metal-oxide-semiconductor 115; First end of second metal-oxide-semiconductor 114 connects the end that said bias current sources 120, the second ends connect the said first current-limiting resistance R119, and the other end of this first current-limiting resistance R119 is the first input end 111 of this OTA.
The said second cascade bias unit comprises: the breadth length ratio of the 4th metal-oxide-semiconductor 116 and the 5th metal-oxide-semiconductor 117, two pipes is 1: 1.
The grid of said the 4th metal-oxide-semiconductor 116 links to each other with first end, and this grid connects the grid of said the 5th metal-oxide-semiconductor 117, and first end that first end of said the 4th metal-oxide-semiconductor connects said the 3rd metal-oxide-semiconductor links to each other, and second end of the 4th metal-oxide-semiconductor connects earth terminal; First end of the 5th metal-oxide-semiconductor 117 connects first end of said first metal-oxide-semiconductor 113, and second end of the 5th metal-oxide-semiconductor 117 connects earth terminal.
Said output-stage circuit comprises: the 6th metal-oxide-semiconductor 118 and sampling resistor Rs; Wherein, First end of said the 6th metal-oxide-semiconductor 118 connects second end of said first metal-oxide-semiconductor 113; Second end of the 6th metal-oxide-semiconductor 118 connects earth terminal through said sampling resistor Rs, and this second end connects said compensation oblique wave current source 130, and this second end output terminal that is said OTA.
Concrete, the principle of work of this analog adder is following:
Electric current is the electric current of said bias current sources 120 on second metal-oxide-semiconductor 114; Because the electric current on the 3rd metal-oxide-semiconductor 115 is the image current of said second metal-oxide-semiconductor 114; Again because the breadth length ratio of second metal-oxide-semiconductor 114 and the 3rd metal-oxide-semiconductor 115 is 1: 1; Therefore, the electric current that flows through on two pipes equates, is the current Ib of bias current sources 120; The electric current that flows through the said first current-limiting resistance R119 is 2*Ib, and therefore, the source voltage of the 3rd metal-oxide-semiconductor 115 is:
V
S115=VSN-2*Ib*R119 (formula 2)
Said the 4th metal-oxide-semiconductor 116 is connected with said the 3rd metal-oxide-semiconductor 115; Therefore, the electric current that flows through on the 4th metal-oxide-semiconductor 116 also is the electric current of said bias current sources 120, because the electric current that flows through on the 5th metal-oxide-semiconductor 117 is the image current of the 4th metal-oxide-semiconductor 116; Therefore; The electric current of said the 5th metal-oxide-semiconductor 117 also is the electric current of bias current sources 120, and first metal-oxide-semiconductor 113 is connected with the 5th metal-oxide-semiconductor 117, so the electric current that flows through on first metal-oxide-semiconductor 113 also is the current Ib of bias current sources 120.
First metal-oxide-semiconductor 113, second metal-oxide-semiconductor 114, the 3rd metal-oxide-semiconductor 115 threes' grid connects together, and the electric current that flows through is Ib, and therefore, three's grid equates with the voltage difference of source electrode, therefore, and the source voltage V of first metal-oxide-semiconductor 113
S113Source voltage V with the 3rd metal-oxide-semiconductor 115
S115Equate that the electric current that let flow is crossed the 6th metal-oxide-semiconductor 118 is Iout, then
Iout=(VIN-(VSN-2*Ib*R119))/R119-Ib=(VIN-VSN)/R119+Ib (formula 3)
Can know by formula 14 and formula 15; Voltage, the electric current of two input ends of OTA remain balance, promptly during VIN=VSN, and Iout=Ib; Be that the 6th metal-oxide-semiconductor 118 upper reaches excess current in the output-stage circuit are Ib, thereby make the 6th metal-oxide-semiconductor 118 be operated in the saturation region.
Preferably, first metal-oxide-semiconductor 113 in the present embodiment, second metal-oxide-semiconductor 114, the 3rd metal-oxide-semiconductor 115 can be realized through P type metal-oxide-semiconductor, and first end is a source electrode for drain electrode, second end.
Said the 4th metal-oxide-semiconductor 116, the 5th metal-oxide-semiconductor 117, the 6th metal-oxide-semiconductor 118 can be realized through N type metal-oxide-semiconductor, and first end is a source electrode for drain electrode, second end.
Preferably, see also Fig. 6, said analog adder also comprises: be connected the capacitor C par that said the 5th metal-oxide-semiconductor 117 links to each other, this electric capacity is represented the summation of the stray capacitance of this point.
The 6th metal-oxide-semiconductor in the output-stage circuit of the analog adder that present embodiment provides is operated in the saturation region at the very start; Compare with the conventional analogue totalizer; The application circuit that has saved the conventional analogue totalizer especially when the application circuit of this analog adder is in zero load or underloading, just can make the switching tube in the output-stage circuit be operated in the saturation region when underloading or zero load; Switching tube in the output-stage circuit carries out the transition to the needed time of saturation region from cut-off region; Thereby, improved the response speed of analog adder greatly, enlarged the scope of application of this analog adder.
The application embodiment also provides a kind of analog adder, and is identical with the application scenarios of Fig. 4 corresponding simulating totalizer, and the function of realization is identical, but inner circuit structure is different.
See also Fig. 6, show the circuit theory synoptic diagram of the another kind of analog adder of the application embodiment, this analog adder comprises: OTA 210 and offset current source 220, wherein,
Said OTA 210 comprises input stage circuit and output-stage circuit; Have first input end 211, second input end 212 and the output terminal, wherein, said first input end 211 is not connected with output-stage circuit; Said second input end 212 links to each other with said output-stage circuit; And said first input end 211 inputs have sensing voltage VSN, and it is the output terminal of analog adder that 212 inputs of second input end have input voltage VIN, output terminal.
Offset current source 220 links to each other with said first input end 211 place branch roads, changing the electric current that said first input end 211 belongs in the branch roads, thereby makes the switching tube 213 in the said output-stage circuit be operated in the saturation region.
The analog adder that present embodiment provides; Increased the electric current that belongs in the branch roads with said first input end 211; Because the electric current in two input ends of OTA remains balance, produce electric current in the switching tube in the said output-stage circuit and flow through second input end place branch road, thereby increase the electric current in the branch road of second input end place; The first input end of OTA and the electric current in second input end are balanced each other; In this process,, make that the switching tube 213 in the output-stage circuit is operated in the saturation region owing to produce electric current in the said output-stage circuit.
Preferably; This analog adder also comprises compensation oblique wave current source 230; Compensation oblique wave current source 230 is and the cycle synchronisation of the clock signal OSC of oscillator, and jagged compensation oblique wave electric current takes place, and is used for sensing voltage is revised; Make dutycycle greater than 50% o'clock, subharmonic oscillation can not take place.
Seeing also Fig. 7, show the physical circuit synoptic diagram of another kind of analog adder, is a kind of particular circuit configurations of analog adder shown in Figure 6.
This analog adder comprises: OTA 210, offset current source 220, compensation oblique wave current source 230.
Wherein, The input stage circuit of said OTA 210 comprises: first metal-oxide-semiconductor 201, second metal-oxide-semiconductor 202 and the 3rd metal-oxide-semiconductor 203; Wherein, the first cascade bias unit that first metal-oxide-semiconductor 201, second metal-oxide-semiconductor 202 are formed, and the breadth length ratio of two pipes is 1: 1;
Concrete; The grid of said first, second metal-oxide-semiconductor links to each other; And link to each other with first end of first metal-oxide-semiconductor; Both second ends all connect earth terminal, and first end that first end of first metal-oxide-semiconductor 201 connects said bias current sources 207, the second metal-oxide-semiconductors 202 connects first end of said the 4th metal-oxide-semiconductor 204; Grid, first end that the grid of the 3rd metal-oxide-semiconductor 203 connects said first metal-oxide-semiconductor 201 connects first end of said the 5th metal-oxide-semiconductor 205, and second end connects earth terminal.
The second cascade bias unit that the 4th metal-oxide-semiconductor 204, the 5th metal-oxide-semiconductor are formed, second end of said the 4th metal-oxide-semiconductor 204 connects said current-limiting resistance R1, and current-limiting resistance R1 is second input end 212 of this OTA 210; Second end of said the 5th metal-oxide-semiconductor connects current-limiting resistance R2, and this current-limiting resistance R2 is the first input end 211 of this OTA 210.
The output-stage circuit of said OTA 210 comprises: the 6th metal-oxide-semiconductor 206, sampling resistor Rs; First end that the grid of the 6th metal-oxide-semiconductor 206 connects said the 3rd metal-oxide-semiconductor 203 links to each other; First end connects earth terminal through said sampling resistor Rs; Second end is connected to second end of said the 4th metal-oxide-semiconductor 204, as the feedback branch of OTA.
The offset current source is connected first end of said the 3rd metal-oxide-semiconductor 203, and compensation oblique wave current source 203 is connected first end of said the 6th metal-oxide-semiconductor 206.
The concrete course of work of this analog adder is following:
Electric current is the image current of first metal-oxide-semiconductor, 201 electric currents on said second metal-oxide-semiconductor 202; Be the current Ib of bias current sources 207, electric current equates with the electric current of second metal-oxide-semiconductor 202 on the 4th metal-oxide-semiconductor 204, and electric current is the image current of electric current on the 4th metal-oxide-semiconductor 204 on the 5th metal-oxide-semiconductor 205; Electric current equates with electric current on the 5th metal-oxide-semiconductor 205 on the 3rd metal-oxide-semiconductor 203; Be the current Ib of bias current sources 207, owing to offset current source 208 links to each other with the 5th metal-oxide-semiconductor 205, therefore; The electric current that flows through the 3rd metal-oxide-semiconductor 203 is bias current sources 207 and offset current source 208 both sums; Promptly increased the electric current that flows through first input end, at this moment, to this branch road of earth terminal, produced the electric current that numerical value equates with the electric current in said offset current source 208 through current-limiting resistance R1, the 6th metal-oxide-semiconductor 206, sampling resistor Rs from VIN; Thereby increased the electric current that flows through second input end, made the first input end of OTA and the electric current in second input end remain balance.
Offset current source, sensing voltage current corresponding, the compensation oblique wave current source voltage that obtains that on sampling resistor Rs, superpose is the output signal of the output terminal VADD of this analog adder.
Need to prove that said first metal-oxide-semiconductor 201, second metal-oxide-semiconductor 202, the 3rd metal-oxide-semiconductor 203 are specially N type metal-oxide-semiconductor, and first end is a source electrode for drain electrode, second end.The 4th metal-oxide-semiconductor 204, the 5th metal-oxide-semiconductor 205, the 6th metal-oxide-semiconductor 206 all can be realized through P type metal-oxide-semiconductor, and first end is a source electrode for drain electrode, second end.
The analog adder that present embodiment provides; The 6th metal-oxide-semiconductor in the output-stage circuit is operated in the saturation region at the very start, compares with the conventional analogue totalizer, and the application circuit that has saved the conventional analogue totalizer is when underloading or zero load; Especially when the application circuit of this analog adder is in zero load or underloading; Just can make the switching tube in the output-stage circuit be operated in the saturation region, the switching tube in the output-stage circuit carries out the transition to the needed time of saturation region from cut-off region, thereby; Improve the response speed of analog adder greatly, enlarged the scope of application of this analog adder.
Corresponding to above-mentioned analog adder, the application embodiment also provides a kind of transformer, application drawing 1 and Fig. 2 corresponding simulating totalizer embodiment,
Concrete, seeing also Fig. 8, this transformer mainly comprises: totalizer 100, error amplifier 101, PWM (Pulse Width Modulation, pulse-length modulation) comparer 102, pwm control circuit 103, and switching tube M1, wherein:
When pwm control circuit 103 output high level, switching tube M1 conducting, electric current flows to coil L from input power supply VIN, through switching tube M1, and sampling resistor R
SNBack inflow place end, this moment coil L storage power, output capacitance C
OUTFor load LOAD energy is provided separately; When totalizer 100 output voltages when detecting voltage, pwm control circuit 103 output low levels, switching tube M1 turn-offs; Electric current exports load LOAD to behind input power supply VIN flowing through coil L, diode D; At this moment, store the coil L of energy and import power supply VIN, thereby realize boosting jointly for load provides energy.
Concrete circuit structure is following:
The input signal of said totalizer 100 comprises: offset voltage, compensation ramp signal, and sensing voltage, the signal of output terminal output is as the input signal of the in-phase input end of PWM comparer.Wherein:
Offset voltage is that the output signal of the totalizer 100 that perhaps the earth potential difference causes between each module of inside circuit incurs loss in transmission for fear of the interference owing to ground;
The compensation ramp signal is and the cycle synchronisation of the clock signal OSC of oscillator, and jagged compensation oblique wave electric current takes place, and is used for sensing voltage is revised, and makes dutycycle greater than 50% o'clock, subharmonic oscillation can not take place;
Electric current and the sampling resistor R of flowing through coil L when sensing voltage VSN is pwm control circuit 103 output high-level control signal
SNProduct, flow through the electric current of coil L through detection, can detect and the corresponding current variation of load.
The in-phase input end of PWM comparer 102 connects the output terminal of totalizer 100, and output terminal is connected to the input end of pwm control circuit 103, when the voltage signal of totalizer output surpasses said detectable voltage signals, and PWM comparer 102 output high level signals.
Capacitor C among the figure
INBe used for stablizing input signal VIN, capacitor C
OUTWhen the conducting of M1 pipe, energy is provided, R to output load
ESRIt is capacitor C
OUTSeries connection ESR resistance, load I
LOADExpression is a current loading.
See also Fig. 9, show the structural representation of the another kind of transformer of the application embodiment, mainly comprise: totalizer 100, error amplifier 101, PWM comparer 102, pwm control circuit 103, and switching tube M1, M2 and M3, wherein:
Said totalizer 100 is above-mentioned Fig. 5 and Fig. 6 corresponding simulating totalizer; Its input signal comprises offset voltage input, the input of compensation ramp voltage and sensing voltage input; Its output result is as the input signal of the in-phase input end of PWM comparer 102; The input of offset voltage is for fear of the interference owing to earth terminal, or the current potential difference of the earth terminal between each module of inside circuit causes that the output signal of totalizer 100 is impaired in transmission.
This transformer generates control signal Q and QB, CS pipe M1, M2, the duty of M3 through output voltage and both feedback informations of coil peak point current.
Concrete, when the output voltage of totalizer 100 is not more than detection voltage, when the output terminal Q end of pwm control circuit 103 is output as high level; When the QB end is output as low level, said switching tube M1 and M2 conducting, switching tube M3 turn-offs; Electric current flows to coil L and process output load Iload to earth terminal, coil L storage power in this process behind input end VIN process switching tube M1 and M2; Accumulation energy in output capacitance Cout provides power supply for output load Iload simultaneously.When totalizer 100 output voltages when detecting voltage, the output terminal Q end of pwm control circuit 103 is output as low level, the QB end is output as high level, switching tube M1 and M2 shutoff, switching tube M3 conducting, coil L energy stored provides power supply for output load Iload.
Capacitor C among the figure is used for stablizing input signal VIN, and capacitor C out connects with coil L, can prevent current break, and resistance R esr is a capacitor C out resistance in series, and output load Iload representes it is current loading, can be any value of zero that is not less than.
Because the response speed of the totalizer of the transformer adopting that present embodiment provides is fast; Therefore; When this transformer be in zero load or underloading the time; The output signal of totalizer also can be followed input signal well and changed, and the totalizer in this transformer can adapt to these three kinds of mode of operations of CCM, critical mode of operation and DCM well.
Each embodiment in this instructions all adopts the mode of going forward one by one to describe, and identical similar part is mutually referring to getting final product between each embodiment, and each embodiment stresses all is the difference with other embodiment.Those of ordinary skills promptly can understand and implement under the situation of not paying creative work.
Need to prove; In this article; Relational terms such as first and second grades only is used for an entity or operation are made a distinction with another entity or operation, and not necessarily requires or hint relation or the order that has any this reality between these entities or the operation.
The above only is the application's a embodiment; Should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the application's principle; Can also make some improvement and retouching, these improvement and retouching also should be regarded as the application's protection domain.
Claims (16)
1. method of accelerating the analog adder response speed; Be applied to analog adder; This analog adder comprises at least: OTA; This OTA has first input end that is not connected with output-stage circuit and second input end that is connected with output-stage circuit, it is characterized in that this method comprises:
Change the electric current in the branch road of said first input end place,, make that the switching tube in the said output-stage circuit is operated in the saturation region so that produce electric current between said output-stage circuit and said second input end place branch road.
2. method according to claim 1 is characterized in that, the electric current in the branch road of the said first input end of said change place comprises:
Offset current source in the said analog adder is linked to each other with said first input end place branch road, to increase the electric current in this branch road.
3. method according to claim 1 is characterized in that, the electric current in the branch road of the said first input end of said change place comprises:
Change the position relation of bias current sources place branch road and said first input end place branch road in the said analog adder, flow through the electric current that said first input end belongs to current-limiting resistance in the branch road with increase.
4. analog adder; It is characterized in that, comprising: OTA, offset current source, first output resistance, wherein; Said OTA has the first input end that is not connected with output-stage circuit, and second input end that is connected with output-stage circuit;
Second input end of said OTA connects earth terminal; First input end has sensing voltage for the input end input of this analog adder; Output terminal is connected to the hot end of said first output resistance through the first mos field effect transistor metal-oxide-semiconductor; The other end ground connection of said first output resistance, the hot end of this first output resistance are the output terminal of this analog adder;
Said offset current source is connected with the first input end place branch road of said OTA, so that the switching tube in the said output-stage circuit is operated in the saturation region.
5. analog adder according to claim 4 is characterized in that, also comprises: compensation oblique wave current source, second output resistance, wherein,
Said compensation oblique wave current source links to each other with the hot end of said first output resistance through said second output resistance, and the hot end of this second output resistance is as the output terminal of this analog adder.
6. according to claim 4 or 5 described analog adders, it is characterized in that said OTA comprises: the first cascade bias unit, input stage circuit, output-stage circuit and backfeed loop, wherein:
The said first cascade bias unit links to each other with said input stage circuit, and the metal-oxide-semiconductor that is used to said input stage circuit provides bias current;
Said input stage circuit comprises: second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor are connected the feedback resistance of the said second metal-oxide-semiconductor source electrode, and second input resistance that is connected said the 3rd metal-oxide-semiconductor source electrode, the mirror current source of formation;
Said output-stage circuit also comprises: the 4th metal-oxide-semiconductor that is connected in series with said the 5th metal-oxide-semiconductor; Wherein, The drain electrode of said the 5th metal-oxide-semiconductor connects the 4th metal-oxide-semiconductor, and the grid of said the 5th metal-oxide-semiconductor links to each other with the drain electrode of said the 3rd metal-oxide-semiconductor, and the grid of the 5th metal-oxide-semiconductor connects said offset current source;
Said backfeed loop comprises: said first metal-oxide-semiconductor and the 5th metal-oxide-semiconductor, and the grid of said first metal-oxide-semiconductor connects the drain electrode of said the 5th metal-oxide-semiconductor, and the source electrode of said the 5th metal-oxide-semiconductor is connected to the hot end of said feedback resistance.
7. analog adder according to claim 6 is characterized in that:
The source electrode of the 4th metal-oxide-semiconductor in the said output-stage circuit connects dc positive power; The grid of said the 4th metal-oxide-semiconductor connects the drain electrode of the 4th metal-oxide-semiconductor; The drain electrode of the 4th metal-oxide-semiconductor connects the drain electrode of said the 5th metal-oxide-semiconductor; The source electrode of said the 5th metal-oxide-semiconductor connects the hot end of said feedback resistance, and the grid of said the 5th metal-oxide-semiconductor connects the drain electrode of said the 3rd metal-oxide-semiconductor, and the grid of the 5th metal-oxide-semiconductor links to each other with said offset current source;
The grid of said first metal-oxide-semiconductor connects the grid of said the 4th metal-oxide-semiconductor, and the source electrode of said first metal-oxide-semiconductor connects dc positive power, and the drain electrode of said first metal-oxide-semiconductor connects the hot end of said second output resistance.
8. according to claim 4 or 5 described analog adders, it is characterized in that, also comprise: be connected the second cascade bias unit between said first cascade bias unit and the said input stage circuit, wherein,
The said first cascade bias unit comprises: first bias current sources, the 6th metal-oxide-semiconductor, the 7th metal-oxide-semiconductor and the 8th metal-oxide-semiconductor, wherein:
The source electrode of said the 6th metal-oxide-semiconductor connects dc positive power, and drain electrode connects the negative output terminal of said bias current sources, the positive output end ground connection of said bias current sources;
The grid of said the 7th metal-oxide-semiconductor connects the grid of said the 6th metal-oxide-semiconductor, and the source electrode of said the 7th metal-oxide-semiconductor connects said dc positive power, and the drain electrode of said the 7th metal-oxide-semiconductor connects the drain electrode of said second metal-oxide-semiconductor;
The grid of said the 8th metal-oxide-semiconductor connects the grid of said the 6th metal-oxide-semiconductor, and the source electrode of said the 8th metal-oxide-semiconductor connects said dc positive power, and the drain electrode of said the 8th metal-oxide-semiconductor connects the drain electrode of said the 3rd metal-oxide-semiconductor;
The said second cascade bias unit comprises: second bias current sources, the 9th metal-oxide-semiconductor, the tenth metal-oxide-semiconductor and the 11 metal-oxide-semiconductor, wherein,
The grid of said the 9th metal-oxide-semiconductor is connected with drain electrode, and should drain electrode connect said second bias current sources;
Said the tenth metal-oxide-semiconductor is serially connected between said the 7th metal-oxide-semiconductor and second metal-oxide-semiconductor, and the grid of said the tenth metal-oxide-semiconductor is connected with the grid of said the 9th metal-oxide-semiconductor;
Said the 11 metal-oxide-semiconductor is connected in series between said the 8th metal-oxide-semiconductor and the 3rd metal-oxide-semiconductor, and the grid of said the 11 metal-oxide-semiconductor is connected with the grid of said the 9th metal-oxide-semiconductor.
9. an analog adder is characterized in that, comprising: OTA and bias current sources, and wherein, said OTA has the first input end that does not link to each other with output-stage circuit, and second input end that links to each other with output-stage circuit;
Second input end of said OTA is as the input end of this analog adder, and input has sensing voltage, and the first input end input has input voltage, and output terminal is as the output terminal of this analog adder;
Said bias current sources is connected in second input end of said OTA, so that the switching tube in the said output-stage circuit is operated in the saturation region.
10. analog adder according to claim 9 is characterized in that, also comprises: the compensation oblique wave current source that is connected the output terminal of said OTA.
11., it is characterized in that said OTA comprises according to claim 9 or 10 described analog adders: input stage circuit and output-stage circuit, wherein,
Said input stage circuit comprises: first resistance, second resistance, the first cascade bias unit, the second cascade bias unit and first metal-oxide-semiconductor, wherein,
First branch road of the said first cascade bias unit connects said bias current sources; Second branch road connects first branch road of the said second cascade bias unit; And this second branch road links to each other with an end of said first resistance, and the other end of said first resistance is as the in-phase input end of this OTA;
Second branch road of the said second cascade bias unit connects first end of said first metal-oxide-semiconductor, and first end of this first metal-oxide-semiconductor connects an end of said second resistance, and second end of this second resistance is as the inverting input of this OTA;
Said output-stage circuit comprises: the 6th metal-oxide-semiconductor and sampling resistor, wherein,
First end of said the 6th metal-oxide-semiconductor connects second end of said first metal-oxide-semiconductor; Second end of said the 6th metal-oxide-semiconductor connects earth terminal through said sampling resistor; This second end connects said compensation oblique wave current source, and this second end output terminal that is said OTA.
12. analog adder according to claim 11 is characterized in that, the said first cascade bias unit comprises: second metal-oxide-semiconductor and the 3rd metal-oxide-semiconductor, wherein,
The grid of said second metal-oxide-semiconductor links to each other with first end, and said grid connects the grid of said the 3rd metal-oxide-semiconductor, and first end of second metal-oxide-semiconductor connects said offset current source, and second end of said second metal-oxide-semiconductor connects second end of said the 3rd metal-oxide-semiconductor;
First end of said the 3rd metal-oxide-semiconductor connects first branch road of said second cascode amplifier, and second end of the 3rd metal-oxide-semiconductor is the in-phase input end of this OTA;
The said second cascade bias unit comprises: the 4th metal-oxide-semiconductor and the 5th metal-oxide-semiconductor, wherein,
The grid of said the 4th metal-oxide-semiconductor links to each other with first end; And the grid of said the 4th metal-oxide-semiconductor connects the grid of said the 5th metal-oxide-semiconductor; First end of said the 4th metal-oxide-semiconductor connects second branch road of said first cascode amplifier, and second end of said the 4th metal-oxide-semiconductor connects earth terminal;
First end of said the 5th metal-oxide-semiconductor connects first end of said first metal-oxide-semiconductor, and second end of the 5th metal-oxide-semiconductor connects earth terminal.
13. an analog adder is characterized in that, comprising: OTA, offset current source, wherein:
Said OTA comprises input stage circuit and output-stage circuit; And have first input end, second input end and output terminal; Wherein, Said first input end is not connected with output-stage circuit, said second input end is connected with output-stage circuit, and said output terminal is the output terminal of this analog adder;
Said offset current source is connected in said first input end place branch road, so that the switching tube in the said output-stage circuit is operated in the saturation region.
14. analog adder according to claim 13 is characterized in that, also comprises: the compensation oblique wave current source that is connected the output terminal of said OTA.
15. transformer; Comprise error amplifier, pulse width modulation (PWM) comparer, pwm control circuit and metal-oxide-semiconductor; It is characterized in that; Also comprise: each described analog adder of claim 4-8, the sensing voltage input end of this analog adder is connected to the source electrode of said metal-oxide-semiconductor, and the output terminal of this analog adder is connected to the in-phase input end of said PWM comparer.
16. transformer; Comprise error amplifier, pulse width modulation (PWM) comparer, pwm control circuit and metal-oxide-semiconductor; It is characterized in that; Also comprise: each described analog adder of claim 9-13, the sensing voltage input end of this analog adder connects the drain electrode of said switching tube, and the output terminal of analog adder is connected to the in-phase input end of said PWM comparer.
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| CN201110183130.X | 2011-06-30 | ||
| CN201210002200.1A CN102654828B (en) | 2011-06-30 | 2012-01-05 | Method for increasing response speed of analog adder, analog adder and transformer |
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Cited By (2)
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| CN113612208A (en) * | 2021-07-20 | 2021-11-05 | Tcl华星光电技术有限公司 | Current limiting circuit |
| CN115454199A (en) * | 2022-09-20 | 2022-12-09 | 圣邦微电子（北京）股份有限公司 | Current selection circuit |
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| CN102231100A (en) * | 2011-06-30 | 2011-11-02 | 上海新进半导体制造有限公司 | Analog adder and current-type boosting transformer |
| CN103683929A (en) * | 2013-12-11 | 2014-03-26 | 矽力杰半导体技术(杭州)有限公司 | Self-adaptive loop compensating method, compensating circuit and switching power supply with compensating circuit |
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| CN102231100A (en) | 2011-11-02 |
| CN102654828B (en) | 2015-06-03 |
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