CN102629598A - 具有金属化源极、栅极与漏极接触区域的半导体芯片的封装 - Google Patents

具有金属化源极、栅极与漏极接触区域的半导体芯片的封装 Download PDF

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CN102629598A
CN102629598A CN2012100639020A CN201210063902A CN102629598A CN 102629598 A CN102629598 A CN 102629598A CN 2012100639020 A CN2012100639020 A CN 2012100639020A CN 201210063902 A CN201210063902 A CN 201210063902A CN 102629598 A CN102629598 A CN 102629598A
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semiconductor chip
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CN102629598B (zh
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孙明
何约瑟
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Alpha and Omega Semiconductor Cayman Ltd
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Abstract

本发明涉及一种金属化半导体芯片的源极、栅极与漏极接触区域的晶圆级方法，其包含有步骤(a)植入镍至半导体芯片的源极、栅极与漏极接触区域，并在完成步骤(a)之后，进行步骤(b)植入金至半导体芯片的源极、栅极与漏极接触区域。另外，本发明也涉及一种半导体封装结构，其包含有数个内连接层板，设置于导线架的数条导线与数个金属化钝化区域之间。

Description

具有金属化源极、栅极与漏极接触区域的半导体芯片的封装
本案是分案申请
原案发明名称：半导体芯片的金属化源极、栅极与漏极接触区域的晶圆级方法
原案国际申请号：PCT/US2006/037833
原案国际申请日：2006年9月30日
原案国家申请号：200680035632.5
原案进入中国日：2008年3月27日
技术领域
本发明涉及一种半导体封装的制作方法，特别是指一种半导体芯片的金属化源极、栅极与漏极接触区域的晶圆级方法。特别说明，本发明方法和本申请人的另一相关美国专利申请案同时处于申请待审中，请参考于公元2005年9月13日递交的，申请号为第11/226,913号的，题目为“具有内连接层板之半导体封装(Semiconductor Package Having Plate Interconnections)”的美国专利所公开的内容。
背景技术
传统上，半导体装置不是藉由内连接层板就是藉由打线接合的方式连接到导线架。例如，美国专利第5,821,611号公开一种半导体组件，其包含有第一导线、半导体芯片单元以及复数个额外的导线，其中第一导线具有尖端部与岛部，半导体芯片单元则利用焊接层安装于第一导线的岛部上，并具有多个电极凸块而突出远离该岛部，而每条额外的导线都具有尖端，这些尖端透过个别的焊镀而连接至电极凸块，并且，额外的导线至少包含有第二导线与第三导线。前述导线会在加热炉中和电极凸块形成合金，且焊接凸块可能会在加热过程中延展开来并形成不可预期的形状。
美国专利第6,040,626号公开了一种半导体封装，其是使用混合的连接部位在包含低电阻的层板部位的氧化半导体场效晶体管(MOSFET)的上表面以及金属打线之间，分别用以连接至源极与栅极。然而，在打线过程中，金属打线可能会由于组件的介电层受损而导致组件发生电流短路。
美国专利第6,249,041号则公开了一种使用直接连接导线的半导体封装。一半导体装置包含有半导体芯片，此半导体芯片上表面或下表面具有多个接触区域，另外，第一导线组件是由导电材料的半硬式层板所形成，其具有一导线组件接点贴附于半导体芯片的多个接触区域之一，且第一导线组件也具有至少一个导线连接导线组件并从导线组件接点延伸而出。此外，第二导线组件也是由导电材料的半硬式层板所形成，其具有一导线组件接点贴附于半导体芯片的另一个接触区域，且第二导线组件也具有至少一个导线连接导线组件并从导线组件接点延伸而出。并以封胶封住半导体芯片、第一导线组件的导线组件接点与第二导线组件的导线组件接点。由于导线组件是直接连接到半导体芯片，使得半导体装置的封装具有低的电阻与热阻。而导线组件接触区域是藉由导电黏着层来和半导体芯片上的导线接触区域相连接，且导电黏着层可为银填充胶、或聚亚酰胺膏、或焊接凸块。另外，假如有所需要的话，亦可以将此导电黏着层在烘箱中进行烘烤，而导电黏着层并不包括软焊料或焊膏。
美国专利第6,479,888号公开了另一种使用直接连接导线的半导体封装。一MOSFET包含有复数个内导线，这些内导线是电性连接至半导体圆球的表面电极的主要表面，该主要表面上设有场效应晶体管。并且，藉由多个凸块所构成的栅极连接部位与源极连接部位，使这些内导线可机械连接以及电性连接至所述的主要表面。
为了减少焊接凸块的需求，因而有必要去寻求该技术领域中对于金属化源极、栅极与漏极接触区域的晶圆级方法。并且，也有必要寻求一种半导体封装结构，其具有镍/金金属化区域，可以用来限制焊接过程中所造成的焊料过溢。再者，也有必要寻求一种半导体封装过程，藉以获得生产力的提升。另外，也有必要寻求一种半导体封装方法，来提供功率半导体装置上的图案化层板的软接合制作。还有必要寻求一种具有外露的源极层板的半导体封装结构。还有必要寻求一种可缩减电阻的半导体封装结构。此外，更有必要寻求一种可提升散热特性的半导体封装结构。还有必要寻求一种可提升机械特性的半导体封装结构。
发明内容
本发明提供一种具有镍/金金属化源极、栅极与漏极的半导体装置的封装方法，藉以大体上解决先前技术存在的种种困难与限制。本发明所提供的方法改善了金属化源极、栅极与漏极区域的焊接与接合。
根据本发明的一个方面所提供的一种半导体芯片的金属化源极、栅极与漏极接触区域的晶圆级方法，其步骤包括有：(a)将镍植入至半导体芯片的源极、栅极与漏极接触区域，及(b)在完成步骤(a)之后，植入金至半导体芯片的源极、栅极与漏极接触区域。
根据本发明的另一方面所提供的一种半导体封装，其包括有导线架、半导体芯片、图案化源极连接部位、图案化栅极连接部位及封胶，其中导线架具有漏极导线、源极导线与栅极导线，半导体芯片连接于导线架，半导体芯片具有镍/金金属化源极、栅极与漏极接触区域，且该镍/金金属化源极、栅极与漏极接触区域是藉由前述本发明提供的半导体芯片的金属化源极、栅极与漏极接触区域的晶圆级方法所形成的。并且，图案化源极连接部位是连接源极导线与半导体芯片镍/金金属化源极接触区域，图案化栅极连接部位是连接栅极导线与半导体芯片镍/金金属化栅极接触区域。另外，半导体芯片镍/金金属化漏极接触区域是连接至漏极导线，而封胶则覆盖至少一部分的半导体芯片以及漏极导线、源极导线与栅极导线。
根据本发明的又一方面所提供的一种半导体封装，其具有栅极夹持部，且该栅极夹持部卡锁于半导体芯片镍/金金属化栅极钝化区域，此半导体封装包含有导线架、半导体芯片、源极夹持部及封胶，其中导线架具有漏极导线、源极导线与栅极导线，半导体芯片连接于导线架，半导体芯片具有镍/金金属化源极与栅极接触区域，且镍/金金属化源极与栅极是藉由前述的本发明提供的半导体芯片的金属化源极、栅极与漏极接触区域的晶圆级方法所形成的。至于源极夹持部是连接源极导线至半导体芯片镍/金金属化源极接触区域，半导体芯片漏极接触区域是连接至漏极导线，而封胶是覆盖至少一部分的半导体芯片以及漏极导线、源极导线与栅极导线。并且，其中栅极夹持部上形成一开孔，并通过该开孔使得栅极夹持部连接栅极导线至半导体芯片镍/金金属化栅极接触区域。
以上概略地与宽广地描述了本发明，而有关本发明的更多特征可由下述的详细说明进行更进一步的了解，并使本发明对于此技术领域的贡献更被突显出来。当然，本发明的其它特征也将在下文作详细说明，并构成本发明的权利要求。
就这方面而言，在详细解释本发明的至少一个实施例之前，必须了解本说明书中的后述内容及附图，仅为详细说明笨发明的实施方式和具体流程，并非用以限定本发明。本发明能够以各种方式的实施例来实行与实现。并且，必须了解在此所使用的措词与用语，乃是和摘要相同地，其内容仅是为了说明本发明的目的，并不应该视为一种限制。
也就是说，任何熟习本领域的技术人员，在不脱离本发明的精神和范围内，均可作些许的更动与润饰，因此本发明的保护范围应当视权利要求所界定的为准。
附图说明
图1是本发明提供的半导体封装的结构示意图；
图2是本发明图1所示的半导体封装沿着剖面线A-A的剖面示意图；
图3是本发明图1所示的半导体封装沿着剖面线B-B的剖面示意图；
图3A是本发明的图案化栅极连接部位位于金属化栅极区域的示意图；
图3B是本发明的栅极卡锁的示意图；
图3C是本发明图1所示的半导体封装具有另一种金属化栅极区域的示意图；
图4是本发明图1所示的半导体封装的局部示意图；
图5是本发明图1所示的半导体封装的另一幅局部示意图；
图6是本发明所提供的半导体封装的另一实施例的结构示意图；
图7是本发明图6所示的半导体封装沿着剖面线A-A的剖面示意图；
图8是本发明图6所示的半导体封装沿着剖面线B-B的剖面示意图；
图9是本发明图6所示的半导体封装的局部示意图；
图10是本发明所提供的半导体封装的另一实施例的结构示意图；
图11是本发明图10所示的半导体封装沿着剖面线A-A的剖面示意图；
图12是本发明图10所示的半导体封装沿着剖面线B-B的剖面示意图；以及
图13是本发明中用以形成镍/金上镀层方法的流程图。
具体实施方式
以下详细说明目前本发明的最佳实施例。此详细说明并不会导致一种限制，其目的仅仅作为说明本发明的基本原理。本发明的保护范围是由权利要求所界定的为准。
本发明主要提供一种用于提供半导体装置的封装方法，此半导体装置封装是在导线架的源极与栅极接触区域之间设有多个连接层板，并具有功率半导体装置金属化源极与栅极区域。此金属化源极与栅极区域最好为镍/金施镀或溅镀的表面。而金属化源极与栅极区域可改善连接层板并能减少过度接合的状况，可防止在接合过程期间经常会因为介电层受损所导致的短路问题。金属化源极与栅极区域更可减少焊接凸块与胶合黏着层的需求，而可以使用软焊料与焊膏来连接每个连接层板至金属化源极与栅极区域。
在本发明的第一部分中，请参考图1～图5，一种半导体封装100可包括导线架105，且导线架105具有漏极接触区域107、源极接触区域110与栅极接触区域115。另外，功率半导体芯片120可具有一金属化漏极区域(图中未标示)，且该金属化漏极区域是藉由回流焊接的方式连接到漏极接触区域107的。
金属化半导体源极与栅极区域可以藉由镍/金施镀或溅镀的方法来形成。请参照图3A，金属化栅极区域160可以为环形结构，且发现此环形金属化栅极区域160的优点是，可以在回流焊接期间将软焊料与焊膏限制在环形金属化栅极区域160的范围内，因此，将可以减少预期之外的形状与短路的状况发生。
图案化源极层板125可包括外露部位127与内部部位130。该内部部位130可连接到源极接触区域110，外露部位127可露出在封胶135的外侧。另外，图案化源极层板125可藉由回流焊接的方式，使用软焊料或焊膏来连接到金属化源极区域，且金属化源极区域可覆盖在功率半导体芯片120上表面的大部分区域，用以改善散热并减少电阻与电感。
图案化栅极层板137可连接金属化栅极区域140到导电架的栅极接触区域115，图案化栅极层板137可包含孔洞165，此孔洞165形成在图案化栅极层板的末端167。球形锁155可以在回流焊接期间形成，用以提供图案化栅极层板137的机械稳定性(请见图3B)。本发明的一方面，可以在回流焊接期间将软焊料设置在孔洞165中，金属化栅极区域160可以提供一个供焊料接合的表面，而将焊料流体限制在环形区域内。
请参照图3C，显示了另一种金属化栅极区域170，其包含有十字形区域。
根据本发明的另一个方面，以及如图6～图9所示，其半导体封装600可包含导线架605，且导线架605具有漏极接触区域607、源极接触区域610与栅极接触区域615。另外，功率半导体芯片620可具有一金属化漏极区域(图中未标示)，其连接到漏极接触区域607。
金属化半导体源极与栅极区域可以藉由镍/金施镀或溅镀的方法来形成。图案化源极层板625可包括外露部位627与内部部位630。该外露部位627可露出在封胶635的外侧。另外，图案化源极层板625可藉由回流焊接方式，使用软焊料或焊膏来连接到金属化源极区域。
图案化栅极层板637可连接金属化栅极区域640到导电架的栅极接触区域，且图案化栅极层板637可藉由回流焊接方式，使用软焊料或焊膏来连接到金属化栅极区域640，用以提供图案化栅极层板637的机械稳定性。
在本发明的另一方面中，请参照图10～图12所示，其半导体封装1000可包含有导线架1005，且导线架1005具有漏极接触区域1007、源极接触区域1010与栅极接触区域1015。另外，功率半导体芯片1020可具有一金属化漏极区域(图中未标示)，其藉由回流焊接的方式连接到漏极接触区域1007。
半导体源极与栅极金属化区域可以藉由镍/金施镀或溅镀的方法来形成。图案化源极层板1025可包括外露部位1027与内部部位1030。该外露部位1027可露出在封胶1035的外侧。另外，图案化源极层板1025可藉由回流焊接方式，使用软焊料或焊膏来连接到金属化源极区域。
图案化栅极层板1037可连接金属化栅极区域1040到导电架栅极接触区域。该图案化栅极层板1037可包含一卡扣部位1039，用以连接到金属化栅极区域1040。且图案化栅极层板1037可藉由回流焊接方式，使用软焊料或焊膏来连接到金属化栅极区域1040，用以提供图案化栅极层板1037的机械稳定性。
本发明优越地使用了镍/金金属化源极、栅极与漏极接触区域，镍/金提供了图案化源极层板与图案化栅极层板间的连接改善，并让源极、漏极与栅极的金属化制作过程可藉由一个镍/金的制作过程获得简化，从而帮助生产力的提升。
另外，此镍/金制作过程提供了位于源极、漏极与栅极金属化区域上的镍镀层，以及提供了金镀层去保护镍镀层。同时，为了避免镍不会扩散到铝的源极、漏极与栅极接触区域，会利用包含镍/铝的介金属层去提供一个高密度镀层给可能被焊接的图案化源极与栅极连接部位。
请参照图13，其显示了用以在一晶圆上的源极、漏极与栅极接触区域形成镍/金上镀层的方法1300，其首先包含步骤1310，将晶圆经过钝化清洗。然后，可于步骤1320中，将晶圆经过碱洗。接着，可于步骤1330中，对于晶圆进行加铝脱氧的过程。之后，可于步骤1340中，将晶圆经过酸镀锌的步骤，以锌的薄层披覆于源极、漏极与栅极接触区域上。然后，还可于步骤1350中，进行自身催化镀镍。并可于步骤1360中，将晶圆浸镀于一金/硫化物的浸镀液中，以在镍镀层上形成金镀层。
本发明优越地提供了一种金属化半导体芯片的源极、栅极与漏极接触区域的晶圆级方法。而金属化源极与栅极接触区域则提供了连接层板的改善并能减少过度接合的状况，可防止在接合过程期间经常会因为介电层受损所导致的短路问题。金属化源极与栅极区域更可减少焊接凸块与胶合黏着层的需求，而可以使用软焊料与焊膏来连接每个层板至金属化源极与栅极区域。
虽然本发明的实施例描述如上，但是其并非用以限定本发明。在不脱离本发明的精神和范围内，任何的更改与润饰，均属本发明的专利保护范围。关于本发明所界定的保护范围请参考所附的权利要求。

Claims (6)

1.一种半导体封装，其特征在于，包括：
一导线架，具有一漏极导线、一源极导线与一栅极导线；
一半导体芯片，与导线架连接，该半导体芯片具有在该半导体芯片的源极接触区域、栅极接触区域与漏极接触区域分别先镀镍再镀金而形成的镍/金金属化源极接触区域、镍/金金属化栅极接触区域与镍/金金属化漏极接触区域；其中，该半导体芯片镍/金金属化漏极接触区域连接至所述的漏极导线；
一图案化源极连接部位，连接所述的源极导线与半导体芯片镍/金金属化源极接触区域，且该图案化源极连接部位是焊接到所述半导体芯片镍/金金属化源极接触区域上的；
一图案化栅极连接部位，连接所述的栅极导线与半导体芯片镍/金金属化栅极接触区域，且该图案化栅极连接部位是焊接到所述半导体芯片镍/金金属化栅极接触区域；及
一封胶，覆盖至少一部分所述的半导体芯片以及所述的漏极导线、源极导线与栅极导线
其中，所述的图案化栅极连接部位包含一开口，且该图案化栅极连接部位通过该开口焊接于所述的半导体芯片的镍/金金属化栅极接触区域。
2.如权利要求1所述的半导体封装，其特征在于，所述的图案化源极连接部位的其中一部分是穿过封胶曝露出来的。
3.如权利要求1所述的半导体封装，其特征在于，所述的焊接所使用的焊料在半导体芯片的镍/金金属化栅极接触区域的顶部形成一卡锁。
4.一种半导体封装，具有一栅极夹持部，且该栅极夹持部是锁固于一半导体芯片镍/金金属化栅极钝化区域，该半导体封装包含：
一导线架，具有一漏极导线、一源极导线与一栅极导线；
一半导体芯片，与导线架连接，该半导体芯片具有在该半导体芯片的源极接触区域、栅极接触区域与漏极接触区域分别先镀镍再镀金而形成的镍/金金属化源极接触区域、镍/金金属化栅极接触区域与镍/金金属化漏极接触区域；其中，该半导体芯片镍/金金属化漏极接触区域连接至所述的漏极导线；
一源极夹持部，连接所述的源极导线至半导体芯片镍/金金属化源极接触区域；
一封胶，覆盖至少一部分所述的半导体芯片以及所述的漏极导线、源极导线与栅极导线；及
在所述的栅极夹持部上形成一开孔，该栅极夹持部通过该开孔，连接栅极导线至半导体芯片镍/金金属化栅极接触区域。
5.如权利要求4所述的半导体封装，其特征在于，所述的图案化源极连接部位的其中一部分是穿过封胶曝露出来的。
6.如权利要求4所述的半导体封装，其特征在于，所述的栅极夹持部与源极夹持部分别焊接至所述的半导体芯片的镍/金金属化栅极接触区域与半导体芯片的镍/金金属化源极接触区域上，且焊接该栅极夹持部所使用的焊料形成一卡锁。
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Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7683464B2 (en) * 2005-09-13 2010-03-23 Alpha And Omega Semiconductor Incorporated Semiconductor package having dimpled plate interconnections
US7397120B2 (en) * 2005-12-20 2008-07-08 Semiconductor Components Industries, L.L.C. Semiconductor package structure for vertical mount and method
CN103314437B (zh) * 2011-03-24 2016-03-30 三菱电机株式会社 功率半导体模块及电源单元装置
US9202946B2 (en) 2013-02-08 2015-12-01 OMG Electronic Chemicals, Inc. Methods for metallizing an aluminum paste
WO2014123535A1 (en) * 2013-02-08 2014-08-14 OMG Electronic Chemicals, Inc. Methods for metallizing an aluminum paste
CN104992934B (zh) * 2015-05-29 2018-01-09 株洲南车时代电气股份有限公司 功率半导体器件子模组
EP3703119B1 (en) * 2017-10-26 2022-06-08 Shindengen Electric Manufacturing Co., Ltd. Semiconductor device and method for manufacturing semiconductor device
US11145576B2 (en) 2017-11-10 2021-10-12 Shindengen Electric Manufacturing Co., Ltd. Electronic module
US11222858B1 (en) * 2020-06-19 2022-01-11 Alpha And Omega Semiconductor International Lp Semiconductor package having enlarged gate pad and method of making the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5132772A (en) * 1991-05-31 1992-07-21 Motorola, Inc. Semiconductor device having tape automated bonding (TAB) leads which facilitate lead bonding
US6774466B1 (en) * 1999-01-28 2004-08-10 Renesas Technology Corp. Semiconductor device
US20050148111A1 (en) * 2003-12-30 2005-07-07 Texas Instruments Incorporated Method and system for producing resilient solder joints
CN1653603A (zh) * 2002-03-12 2005-08-10 费查尔德半导体有限公司 晶片级涂覆的铜柱状凸起

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5821611A (en) * 1994-11-07 1998-10-13 Rohm Co. Ltd. Semiconductor device and process and leadframe for making the same
US6249041B1 (en) * 1998-06-02 2001-06-19 Siliconix Incorporated IC chip package with directly connected leads
US6040626A (en) * 1998-09-25 2000-03-21 International Rectifier Corp. Semiconductor package
JP3871486B2 (ja) * 1999-02-17 2007-01-24 株式会社ルネサステクノロジ 半導体装置
DE50103781D1 (de) * 2001-10-11 2004-10-28 Franz Oberflaechentechnik Gmbh Beschichtungsverfahren für Leichtmetalllegierungsoberflächen
US7294565B2 (en) * 2003-10-01 2007-11-13 International Business Machines Corporation Method of fabricating a wire bond pad with Ni/Au metallization
US20060012055A1 (en) * 2004-07-15 2006-01-19 Foong Chee S Semiconductor package including rivet for bonding of lead posts

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5132772A (en) * 1991-05-31 1992-07-21 Motorola, Inc. Semiconductor device having tape automated bonding (TAB) leads which facilitate lead bonding
US6774466B1 (en) * 1999-01-28 2004-08-10 Renesas Technology Corp. Semiconductor device
CN1653603A (zh) * 2002-03-12 2005-08-10 费查尔德半导体有限公司 晶片级涂覆的铜柱状凸起
US20050148111A1 (en) * 2003-12-30 2005-07-07 Texas Instruments Incorporated Method and system for producing resilient solder joints

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