CN102624271A

CN102624271A - Five-level inverted topology unit and five-level inverter

Info

Publication number: CN102624271A
Application number: CN2012100976397A
Authority: CN
Inventors: 汪洪亮; 赵为; 张彦虎
Original assignee: Sungrow Power Supply Co Ltd
Current assignee: Sungrow Power Supply Co Ltd
Priority date: 2012-04-01
Filing date: 2012-04-01
Publication date: 2012-08-01
Anticipated expiration: 2032-04-01
Also published as: CN102624271B

Abstract

The invention provides a five-level inverted topology unit. The five-level inverted topology unit comprises six switch tubes and four diodes, wherein the switch tubes are reversely connected in parallel with diodes, and the four diodes are connected in series with the switch tubes. Compared with the prior art which needs to take pressure equalizing measures and employ a larger RC (Resistor-Capacitor) absorption circuit to prevent two ends of part of the diodes from overvoltage so as to result in huge volume, increased cost, higher loss and lower efficiency of an inverter, less semiconductor devices, smaller volume, lower cost, less loss and higher efficiency of the entire inverter are ensured when single-phase and multi-phase applications are realized and a current path is guaranteed.

Description

A kind of five level inverse conversion topology unit and five-electrical level inverters

Technical field

The application relates to electric and electronic technical field, particularly a kind of five level inverse conversion topology unit and five-electrical level inverters.

Background technology

The big capacity occasion of middle pressure, multi-electrical level inverter is widely used, and present five-electrical level inverter mainly is a diode-clamped.Introduce in the face of the diode-clamped five-level inverter down.

Referring to Fig. 1, this figure is the five-electrical level inverter topological diagram of the diode-clamped that provides in the prior art.

Shown in Figure 1 is the topological structure of half-bridge five-electrical level inverter.Diode is used to each switching tube and carries out voltage clamp.For example, the first diode DB1 is used for the voltage clamp of switch transistor T 1 lower end is positioned at the lower end of first capacitor C 1; The second diode DB2 is used for the voltage clamp of switch transistor T 5 lower ends is positioned at the lower end of first capacitor C 1.Other diodes DB3, DB4, DB5 and DB6 are similar, repeat no more at this.

Because clamping diode need be blocked many times of level voltages, need the diode series connection of a plurality of same nominal values usually, these diodes are together in series and bear the voltage that diode DB2 bears among Fig. 1 jointly.Because the dispersiveness of diode and the influence of stray parameter, the pressure that the diode that nominal value is identical can bear be difference to some extent also, being together in series like this to cause the diode two ends overvoltage that has.Therefore, need all press measure and very big RC to absorb circuit, but will cause systems bulky like this, cost increases, and loss is more, and efficient is lower.

Summary of the invention

The application's technical problem to be solved provides a kind of five level inverse conversion topology unit and five-electrical level inverters, and bulky in order to inverter system in the solution prior art, cost increases, and loss is more, the technical problem that efficient is lower.

The application provides a kind of five level inverse conversion topology unit, comprises switch transistor T 1, switch transistor T A1, switch transistor T A2, switch transistor T 2, switch transistor T B1, switch transistor T B2, diode D1, diode DA1, diode DB1, diode D2;

Diode of the equal reverse parallel connection of each said switching tube;

The first direct-flow input end M1 of this topology unit is through diode in series DA1, switch transistor T A1, switch transistor T 1, switch transistor T 2, switch transistor T B1 and diode DB1 link to each other with the second direct-flow input end M2 of this topology unit successively;

The 3rd direct-flow input end M3 of this topology unit links to each other with the 4th direct-flow input end M4 of this topology unit with switch transistor T B2 through the switch transistor T A2 of series connection successively;

The connecting line of switch transistor T 2 and switch transistor T B1 links to each other with the connecting line of switch transistor T 1 with switch transistor T A1 with diode D1 through diode in series D2 successively;

The 5th direct-flow input end M5 of this topology unit links to each other with the connecting line of diode D1 with diode D2;

The connecting line of switch transistor T A2 and switch transistor T B2 links to each other with first ac output end of this topology unit, and the connecting line of diode D2 and diode D1 links to each other with second ac output end of this topology unit.

The application also provides a kind of five-electrical level inverter, comprises the above topology unit, wherein:

The first direct current positive level PV1+ links to each other with the first direct-flow input end M1; The second direct current positive level PV2+ links to each other with the 3rd direct-flow input end M3; Direct current zero level PV0 links to each other with the 5th direct-flow input end M5; The first direct current negative level PV1-links to each other with the second direct-flow input end M2, and the second direct current negative level PV2-links to each other with the 4th direct-flow input end M4;

The connecting line of the first direct current positive level PV1+ and the first direct-flow input end M1 links to each other with the connecting line of the first direct current negative level PV1-and the second direct-flow input end M2 with capacitor C B 1 through the capacitor C A1 of series connection successively;

The connecting line of the second direct current positive level PV2+ and the 3rd direct-flow input end M3 links to each other with the connecting line of the second direct current negative level PV2-and the 4th direct-flow input end M4 with capacitor C B2 through the capacitor C A2 of series connection successively;

The connecting line of capacitor C A1 and capacitor C B 1 links to each other and links to each other with the 5th direct-flow input end M5 with the connecting line of capacitor C A2 and capacitor C B2;

First ac output end of topology unit links to each other with first ac output end of this inverter, and second ac output end of topology unit links to each other with second ac output end of this inverter.

The application also provides another kind of five level inverse conversion topology unit, comprises switch transistor T 1, switch transistor T A1, switch transistor T A2, switch transistor T 2, switch transistor T B1, switch transistor T B2, diode D1, diode DA1, diode DB1, diode D2;

Diode of the equal reverse parallel connection of each said switching tube;

The first direct-flow input end M1 of this topology unit links to each other with the second direct-flow input end M2 of this topology unit through switch transistor T 1, switch transistor T A1, diode DA1, diode DB1, switch transistor T B1 and the switch transistor T 2 of series connection successively;

The 3rd direct-flow input end M3 of this topology unit links to each other with the 4th direct-flow input end M4 of this topology unit with switch transistor T B2 through the switch transistor T A2 of series connection successively; The connecting line of switch transistor T 2 and switch transistor T B 1 links to each other with the connecting line of switch transistor T 1 with switch transistor T A1 with diode D1 through diode in series D2 successively; The 5th direct-flow input end M5 of this topology unit links to each other with the connecting line of diode D1 with diode D2;

The application also provides another kind of five-electrical level inverter, comprises the above topology unit, wherein:

The connecting line of the first direct current positive level PV1+ and the first direct-flow input end M1 links to each other with the connecting line of the first direct current negative level PV1-and the second direct-flow input end M2 with capacitor C B1 through the capacitor C A1 of series connection successively;

The connecting line of the second direct current positive level PV2+ and the 3rd direct-flow input end M3 links to each other with the connecting line of the second direct current negative level PV2-and the 4th direct-flow input end M4 with capacitor C B2 through the capacitor C A2 of series connection successively; The connecting line of capacitor C A1 and capacitor C B1 links to each other and links to each other with the 5th direct-flow input end M5 with the connecting line of capacitor C A2 and capacitor C B2; First ac output end of topology unit links to each other with first ac output end of this inverter, and second ac output end of topology unit links to each other with second ac output end of this inverter.

The application also provides a kind of five-electrical level inverter, comprises two above-mentioned topology unit: first topology unit and second topology unit, wherein:

The first direct current positive level PV1+ links to each other with each first direct-flow input end M1 of first topology unit and second topology unit; The first direct current negative level PV1-links to each other with each second direct-flow input end M2 of first topology unit and second topology unit;

The connecting line of the first direct current positive level PV1+ and the first direct-flow input end M1 of first topology unit or second topology unit links to each other with first direct current negative level PV1-of first topology unit or second topology unit and the connecting line of the second direct-flow input end M2 with capacitor C B1 through the capacitor C A1 of series connection successively;

The second direct current positive level PV2+ links to each other with each the 3rd direct-flow input end M3 of first topology unit and second topology unit; The second direct current negative level PV2-links to each other with each the 4th direct-flow input end M4 of first topology unit and second topology unit;

The connecting line of the second direct current positive level PV2+ and the 3rd direct-flow input end M3 of first topology unit or second topology unit links to each other with second direct current negative level PV2-of first topology unit or second topology unit and the connecting line of the 4th direct-flow input end M4 with capacitor C B2 through the capacitor C A2 of series connection successively;

Direct current zero level PV0 links to each other with each the 5th direct-flow input end M5 of first topology unit and second topology unit; The connecting line of capacitor C A1 and capacitor C B1 links to each other with the connecting line of capacitor C A2 and capacitor C B2 and links to each other with the 5th direct-flow input end M5 of first topology unit or second topology unit;

Each first ac output end in first topology unit and second topology unit links to each other with second ac output end with first ac output end of this inverter respectively.

The application also provides a kind of five-electrical level inverter, comprises three above-mentioned topology unit: first topology unit, second topology unit and the 3rd topology unit; The first direct current positive level PV1+ links to each other with each first direct-flow input end M1 of first topology unit, second topology unit and the 3rd topology unit; The first direct current negative level PV1-links to each other with each second direct-flow input end M2 of first topology unit, second topology unit and the 3rd topology unit;

The connecting line of the first direct current positive level PV1+ and the first direct-flow input end M1 of first topology unit, second topology unit or the 3rd topology unit links to each other with first direct current negative level PV1-of first topology unit, second topology unit or the 3rd topology unit and the connecting line of the second direct-flow input end M2 with capacitor C B1 through the capacitor C A1 of series connection successively;

The second direct current positive level PV2+ links to each other with each the 3rd direct-flow input end M3 of first topology unit, second topology unit and the 3rd topology unit;

The second direct current negative level PV2-links to each other with each the 4th direct-flow input end M4 of first topology unit, second topology unit and the 3rd topology unit;

The connecting line of the second direct current positive level PV2+ and the 3rd direct-flow input end M3 of first topology unit, second topology unit or the 3rd topology unit links to each other with second direct current negative level PV2-of first topology unit, second topology unit or the 3rd topology unit and the connecting line of the 4th direct-flow input end M4 with capacitor C B2 through the capacitor C A2 of series connection successively;

Direct current zero level PV0 links to each other with each the 5th direct-flow input end M5 of first topology unit, second topology unit and the 3rd topology unit;

The connecting line of capacitor C A1 and capacitor C B1 links to each other with the connecting line of capacitor C A2 and capacitor C B2 and links to each other with the 5th direct-flow input end M5 of first topology unit, second topology unit or the 3rd topology unit;

Each first ac output end in first topology unit, second topology unit and the 3rd topology unit links to each other with first ac output end, second ac output end and the 3rd ac output end of this inverter respectively.

The application also provides a kind of five-electrical level inverter, comprises four above-mentioned topology unit: first topology unit, second topology unit, the 3rd topology unit and the 4th topology unit;

The first direct current positive level PV1+ links to each other with each first direct-flow input end M1 of first topology unit, second topology unit, the 3rd topology unit and the 4th topology unit;

The first direct current negative level PV1-links to each other with each second direct-flow input end M2 of first topology unit, second topology unit, the 3rd topology unit and the 4th topology unit;

The connecting line of the first direct current positive level PV1+ and the first direct-flow input end M1 of first topology unit, second topology unit, the 3rd topology unit or the 4th topology unit links to each other with first direct current negative level PV1-of first topology unit, second topology unit, the 3rd topology unit or the 4th topology unit and the connecting line of the second direct-flow input end M2 with capacitor C B1 through the capacitor C A1 of series connection successively;

The second direct current positive level PV2+ links to each other with each the 3rd direct-flow input end M3 of first topology unit, second topology unit, the 3rd topology unit and the 4th topology unit;

The second direct current negative level PV2-links to each other with each the 4th direct-flow input end M4 of first topology unit, second topology unit, the 3rd topology unit and the 4th topology unit;

The connecting line of the second direct current positive level PV2+ and the 3rd direct-flow input end M3 of first topology unit, second topology unit links to each other with second direct current negative level PV2-of first topology unit, second topology unit, the 3rd topology unit or the 4th topology unit and the connecting line of the 4th direct-flow input end M4 with capacitor C B2 through the capacitor C A2 of series connection successively;

Direct current zero level PV0 links to each other with each the 5th direct-flow input end M5 of first topology unit, second topology unit, the 3rd topology unit and the 4th topology unit;

The connecting line of capacitor C A1 and capacitor C B1 links to each other with the connecting line of capacitor C A2 and capacitor C B2 and links to each other with the 5th direct-flow input end M5 of first topology unit, second topology unit, the 3rd topology unit or the 4th topology unit;

Each first ac output end in first topology unit, second topology unit, the 3rd topology unit and the 4th topology unit links to each other with first ac output end, second ac output end, the 3rd ac output end and the 4th ac output end of this inverter respectively.

From the above; The five level inverse conversion topology unit that the application provides comprise switching tube and four and the switching tube diode in series of six reverse parallel connection diodes; All press measure and bigger RC absorption circuit to prevent the two ends overvoltage of part diode and cause the problem that inverter is bulky, cost increases, loss is more and efficient is lower that the five level inverse conversion topology unit that the application provides when assurance provides path for electric current, guarantee that the semiconductor device of whole inverter is less when realizing single-phase and heterogeneous application with respect to adopting in the prior art; Volume is less; Cost is lower, and loss simultaneously is less, and efficient is higher.

Certainly, arbitrary product of enforcement the application might not reach above-described all advantages simultaneously.

Description of drawings

In order to be illustrated more clearly in the technical scheme among the application embodiment; The accompanying drawing of required use is done to introduce simply in will describing embodiment below; Obviously, the accompanying drawing in describing below only is some embodiment of the application, for those of ordinary skills; Under the prerequisite of not paying creative work property, can also obtain other accompanying drawing according to these accompanying drawings.

Fig. 1 is diode-clamped five-level inverter topology figure in the prior art;

The topological diagram of a kind of five level inverse conversion topology unit embodiment one that Fig. 2 provides for the application;

The topological diagram of a kind of five-electrical level inverter embodiment two that Fig. 3 provides for the application;

Another topological diagram of a kind of five-electrical level inverter embodiment two that Fig. 4 provides for the application;

Another topological diagram of a kind of five-electrical level inverter embodiment two that Fig. 5 provides for the application;

Another topological diagram of a kind of five-electrical level inverter embodiment two that Fig. 6 provides for the application;

A kind of five-electrical level inverter embodiment two that Fig. 7 provides for the application is in the topological diagram of first operation mode;

A kind of five-electrical level inverter embodiment two that Fig. 8 provides for the application is in the topological diagram of second operation mode;

A kind of five-electrical level inverter embodiment two that Fig. 9 provides for the application is in the topological diagram of the 3rd operation mode;

A kind of five-electrical level inverter embodiment two that Figure 10 provides for the application is in the topological diagram of the 4th operation mode;

A kind of five-electrical level inverter embodiment two that Figure 11 provides for the application is in the topological diagram of the 5th operation mode;

A kind of five-electrical level inverter embodiment two that Figure 12 provides for the application is in the topological diagram of the 6th operation mode;

A kind of five-electrical level inverter embodiment two that Figure 13 provides for the application is in the topological diagram of the 7th operation mode;

A kind of five-electrical level inverter embodiment two that Figure 14 provides for the application is in the topological diagram of the 8th operation mode;

The topological diagram of a kind of five level inverse conversion topology unit embodiment three that Figure 15 provides for the application;

The topological diagram of a kind of five-electrical level inverter embodiment four that Figure 16 provides for the application;

Another topological diagram of a kind of five-electrical level inverter embodiment four that Figure 17 provides for the application;

Another topological diagram of a kind of five-electrical level inverter embodiment four that Figure 18 provides for the application;

Another topological diagram of a kind of five-electrical level inverter embodiment four that Figure 19 provides for the application;

The isoboles of a kind of five level inverse conversion topology unit embodiment one that Figure 20 provides for the application;

The isoboles of a kind of five level inverse conversion topology unit embodiment three that Figure 21 provides for the application;

The topological diagram of a kind of five-electrical level inverter embodiment five that Figure 22 passes through for the application;

Another topological diagram of a kind of five-electrical level inverter embodiment five that Figure 23 passes through for the application;

The topological diagram of a kind of five-electrical level inverter embodiment six that Figure 24 passes through for the application;

Another topological diagram of a kind of five-electrical level inverter embodiment six that Figure 25 passes through for the application;

Another topological diagram of a kind of five-electrical level inverter embodiment six that Figure 26 passes through for the application;

The topological diagram of a kind of five-electrical level inverter embodiment seven that Figure 27 passes through for the application;

Another topological diagram of a kind of five-electrical level inverter embodiment seven that Figure 28 passes through for the application.

Embodiment

To combine the accompanying drawing among the application embodiment below, the technical scheme among the application embodiment is carried out clear, intactly description, obviously, described embodiment only is the application's part embodiment, rather than whole embodiment.Based on the embodiment among the application, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the application's protection.

With reference to figure 2; It shows the topological diagram of the topology unit embodiment one of a kind of five-electrical level inverter that the application provides, and the topology unit of said five-electrical level inverter comprises: switch transistor T 1, switch transistor T A1, switch transistor T A2, switch transistor T 2, switch transistor T B1, switch transistor T B2, diode D1, diode DA1, diode DB1, diode D2;

Diode of the equal reverse parallel connection of each said switching tube;

Wherein, the switching tube of above topology unit can be managed for IGBT, MOSFET manages, IGCT manages or the IEGT pipe.It is understandable that above switching tube also can be selected the switching tube of other types.More than can be diode independently with the diode of switching tube reverse parallel connection, also can be the diode that integrates with the switching tube encapsulation.

From the above; Need in the corresponding prior art to adopt and all press measure and bigger RC absorption circuit to prevent the two ends overvoltage of part diode and cause the problem that inverter is bulky, cost increases, loss is more and efficient is lower; The five-electrical level inverter of the five level inverse conversion topology unit that provide based on the application when realizing single-phase and heterogeneous application when assurance provides path for electric current; The semiconductor device that guarantees whole inverter is less, and volume is less, and cost is lower; Loss simultaneously is less, and efficient is higher.

With reference to figure 3, it shows the topological diagram of a kind of five-electrical level inverter embodiment two that the application provides, and based on the application embodiment one, the application embodiment two comprises one like embodiment one described topology unit, wherein:

The connecting line of capacitor C A1 and capacitor C B1 links to each other and links to each other with the 5th direct-flow input end M5 with the connecting line of capacitor C A2 and capacitor C B2;

Wherein, As shown in Figure 4, above-mentioned five level can add that two DC/DC booster circuits obtain through two DC power supply PVM and PVN, and are concrete; Two DC power supply PVM and the positive and negative butt joint of PVN; Generate the first direct current positive level PV1+, the first direct current negative level PV1-and direct current zero level PV0, two DC power supply PVM respectively are connected a DC/DC booster circuit with PVN, generate the second direct current positive level PV2+ and the second direct current negative level PV2-.

With reference to figure 5, it shows the another kind of structural representation of the application embodiment two, and based on above-mentioned embodiment as shown in Figure 4, the five-electrical level inverter that the application provides also comprises inductance L 501 and capacitor C 501, wherein:

The connecting line of switch transistor T A2 and switch transistor T B2 links to each other with the connecting line of diode D2 with diode D1 with capacitor C 501 through the inductance L 501 of series connection successively;

The connecting line of inductance L 501 and capacitor C 501 links to each other with first ac output end of this inverter.

Above-mentioned five level as shown in Figure 4 can also be through obtaining like the described mode of Fig. 6; DC power supply PVS produces the first direct current positive level PV1+ and the first direct current negative level PV1-; Dividing potential drop effect through capacitor C A1 and capacitor C B1 produces direct current zero level PV0; DC power supply PVS two ends respectively connect a DC/DC booster circuit, generate the second direct current positive level PV2+ and the second direct current negative level PV2-.

Have and above-mentionedly know, the application realizes the practical application of the application embodiment two through increasing inductance and electric capacity, reduces the harmonic wave of the output current of the application embodiment two, and embodiment two is in the accuracy of carrying out current conversion for raising the application.

The syndeton class of the syndeton of five-electrical level inverter shown in Figure 5 and inductance and electric current formed filtration module and five-electrical level inverter as shown in Figure 6 and inductance and electric current formed filtration module this, no longer set forth at this.

From the above; All press measure and bigger RC absorption circuit to prevent the two ends overvoltage of part diode and cause the problem that inverter is bulky, cost increases, loss is more and efficient is lower with respect to needing in the prior art to adopt; The five-electrical level inverter embodiment two that the application provides, promptly the application embodiment one when assurance provides path for electric current, guarantees that the semiconductor device of whole inverter is less when realization is single-phase; Volume is less; Cost is lower, and loss simultaneously is less, and efficient is higher.

Wherein, the five-electrical level inverter embodiment two that the application provides comprises eight operation modes when realizing the conversion of direct current and alternating current, come eight kinds of operation modes of five-electrical level inverter embodiment two shown in Figure 5 are carried out labor below in conjunction with accompanying drawing.

Wherein, diode DA2 and switch transistor T A2 reverse parallel connection, diode DB2 and switch transistor T B2 reverse parallel connection.Wherein, the operation mode of the application embodiment two forms and can realize through SECO.

With reference to figure 7, it shows the topological diagram of first operation mode of the five-electrical level inverter embodiment two that the application provides.First operation mode: switch transistor T 1 conducting, rest switch Guan Jun ends; Wherein, the path of not conducting illustrates with fine line in the drawings, and the path of conducting illustrates with heavy line.

Path of current is: D1-T1-L501-VG-D1.

With reference to figure 8, it shows the topological diagram of five-electrical level inverter embodiment 2 second operation modes that the application provides.Second operation mode: switch transistor T 1 and switch transistor T A1 conducting, rest switch Guan Jun ends; Wherein, the path of not conducting illustrates with fine line in the drawings, and the path of conducting illustrates with heavy line.

Current path is: PV1+-DA1-TA1-T1-L501-V _G-PV0.

With reference to figure 9, it shows the topological diagram of five-electrical level inverter embodiment 2 the 3rd operation mode that the application provides.The 3rd operation mode: switch transistor T A2 conducting, rest switch Guan Jun ends; Wherein, the path of not conducting illustrates with fine line in the drawings, and the path of conducting illustrates with heavy line.

Current path is: PV2+-TA2-L501-V _G-PV0.

Wherein, Said the 3rd operation mode can also be switch transistor T A2, switch transistor T 1 and switch transistor T A1 conducting; Rest switch Guan Jun ends, and promptly after second operation mode finished, switch transistor T 1 can be selected not give closing with switch transistor T A1; This moment the 3rd operation mode with have only switch transistor T A2 conductive current path consistent, the loss in the time of can reducing switching tube thus and between conducting and closure, operate.

With reference to Figure 10, it shows the topological diagram of the 4th operation mode of the five-electrical level inverter embodiment two that the application provides.The 4th operation mode: switch transistor T 2 conductings, rest switch Guan Jun ends; The path of not conducting illustrates with fine line in the drawings, and the path of conducting illustrates with heavy line.

Current path is: T2-D2-V _G-L501-T2.

With reference to Figure 11, it shows the topological diagram of the 5th operation mode of the five-electrical level inverter embodiment two that the application provides.The 5th operation mode: switch transistor T 2 and switch transistor T B1 conducting, rest switch Guan Jun ends; The path of not conducting illustrates with fine line in the drawings, and the path of conducting illustrates with heavy line.

Current path is: PV0-V _G-L501-T2-TB1-DB1-PV1-.

With reference to Figure 12, it shows the topological diagram of the 6th operation mode of the five-electrical level inverter embodiment two that the application provides.The 6th operation mode: switch transistor T B2 conducting, rest switch Guan Jun ends; The path of not conducting illustrates with fine line in the drawings, and the path of conducting illustrates with heavy line.

Current path is: PV0-V _G-L501-TB2-PV2-.

Wherein, Said the 6th operation mode can also be switch transistor T B2, switch transistor T 2 and switch transistor T B1 conducting; Rest switch Guan Jun ends, and promptly after the 5th operation mode finished, switch transistor T 2 can be selected not give closing with switch transistor T B1; This moment the 6th operation mode with have only switch transistor T B2 conductive current path consistent, the loss in the time of can reducing switching tube thus and between conducting and closure, operate.

With reference to Figure 13, it shows the topological diagram of five-electrical level inverter embodiment 2 the 7th operation mode that the application provides.The 7th operation mode: switch transistor T 1 conducting, switch transistor T 1 and switch transistor T A1 conducting or switch transistor T 1 and switch transistor T A1 and switch transistor T A2 conducting, rest switch Guan Jun ends; The path of not conducting illustrates with fine line in the drawings, and the path of conducting illustrates with heavy line.

Current path is: CA2-V _G-L501-DA2-CA2.

With reference to Figure 14, it shows the topological diagram of the 8th operation mode of the five-electrical level inverter embodiment two that the application provides.The 8th operation mode: switch transistor T 2 conductings, switch transistor T 2 and switch transistor T B1 conducting or switch transistor T 2 and switch transistor T B1 and switch transistor T B2 conducting, rest switch Guan Jun ends; The path of not conducting illustrates with fine line in the drawings, and the path of conducting illustrates with heavy line.

Current path is: CB2-DB2-L501-V _G-CB2.

In above-mentioned second operation mode, switch transistor T 1 is born the first positive level PV1+ jointly with switch transistor T A1; In the 5th operation mode, switch transistor T 2 is born the first negative level PV1-jointly with switch transistor T B1, and with respect to the situation of single switching transistor in the prior art, the voltage stress that the switching tube components and parts bear is little, and is less to the loss of components and parts.

Have and above-mentionedly know, the five-electrical level inverter embodiment two that the application provides adopts the sinusoidal wave thinking of five Level Technology matches, and common-mode voltage is little with respect to prior art, and the ripple loss is lower, and conversion efficiency is higher.

Wherein, eight operation modes of the five level inverse conversion topology unit embodiment one that the application provides when realizing the conversion of direct current and alternating current, similar with Fig. 7 among the application embodiment two to operation mode shown in Figure 14, repeat no more at this.

With reference to Figure 15; It shows the topological diagram of a kind of five level inverse conversion topology unit embodiment three that the application provides, and said five level inverse conversion topology unit comprise: switch transistor T 1, switch transistor T A1, switch transistor T A2, switch transistor T 2, switch transistor T B1, switch transistor T B2, diode D1, diode DA1, diode DB1, diode D2;

Diode of the equal reverse parallel connection of each said switching tube;

From the above; Need in the corresponding prior art to adopt and all press measure and bigger RC absorption circuit to prevent the two ends overvoltage of part diode and cause the problem that inverter is bulky, cost increases, loss is more and efficient is lower; The five-electrical level inverter of the five level inverse conversion topology unit embodiment three that provide based on the application when realizing single-phase and heterogeneous application when assurance provides path for electric current; The semiconductor device that guarantees whole inverter is less, and volume is less, and cost is lower; Loss simultaneously is less, and efficient is higher.

With reference to Figure 16, it shows the topological diagram of a kind of five-electrical level inverter embodiment four that the application provides, and based on the application embodiment three, the application embodiment four comprises one like embodiment three described topology unit, wherein:

Wherein, Shown in figure 17, above-mentioned five level can add that two DC/DC booster circuits obtain through two DC power supply PVM and PVN, and are concrete; Two DC power supply PVM and the positive and negative butt joint of PVN; Generate the first direct current positive level PV1+, the first direct current negative level PV1-and direct current zero level PV0, two DC power supply PVM respectively are connected a DC/DC booster circuit with PVN, generate the second direct current positive level PV2+ and the second direct current negative level PV2-.

Above-mentioned five level can also be through obtaining like the described mode of Figure 19; DC power supply PVS produces the first direct current positive level PV1+ and the first direct current negative level PV1-; Dividing potential drop effect through capacitor C A1 and capacitor C B1 produces direct current zero level PV0; DC power supply PVS two ends respectively connect a DC/DC booster circuit, generate the second direct current positive level PV2+ and the second direct current negative level PV2-.

With reference to Figure 18, it shows the another kind of structural representation of the application embodiment four, and based on the foregoing description, the five-electrical level inverter that the application provides also comprises inductance L 1801 and capacitor C 1801, wherein:

The connecting line of switch transistor T A2 and switch transistor T B2 links to each other with the connecting line of diode D2 with diode D1 with capacitor C 1801 through the inductance L 1801 of series connection successively;

The connecting line of inductance L 1801 and capacitor C 1801 links to each other with first ac output end of this inverter.

Have and above-mentionedly know, the application realizes the practical application of the application embodiment four through increasing inductance and electric capacity, reduces the harmonic wave of the output current of the application embodiment four, and embodiment four is in the accuracy of carrying out current conversion for raising the application.

Based on the syndeton of five-electrical level inverter shown in figure 19 and inductance and electric current formed filtration module and the syndeton class among Figure 18 this, no longer set forth at this.

From the above; All press measure and bigger RC absorption circuit to prevent the two ends overvoltage of part diode and cause the problem that inverter is bulky, cost increases, loss is more and efficient is lower with respect to needing in the prior art to adopt; The five-electrical level inverter embodiment four that the application provides, promptly the application embodiment three when assurance provides path for electric current, guarantees that the semiconductor device of whole inverter is less when realization is single-phase; Volume is less; Cost is lower, and loss simultaneously is less, and efficient is higher.

Wherein, the five-electrical level inverter embodiment four that the application provides comprises eight operation modes when realizing the conversion of direct current and alternating current, carries out labor in the face of eight kinds of operation modes down:

First operation mode: switch transistor T A1 conducting, rest switch Guan Jun ends; Path of current is: D1-TA1-DA1-L1801-VG-D1.

Second operation mode: switch transistor T 1 and switch transistor T A1 conducting, rest switch Guan Jun ends; Current path is: PV1+-T1-TA1-DA1-L1801-V _G-PV0.

The 3rd operation mode: switch transistor T A2 conducting, rest switch Guan Jun ends; Current path is: PV2+-TA2-L1801-V _G-PV0.

Wherein, Said the 3rd operation mode can also be switch transistor T A2, switch transistor T 1 and switch transistor T A1 conducting; Rest switch Guan Jun ends, and promptly after second operation mode finished, switch transistor T 1 can be selected not give closing with switch transistor T A1; This moment, the 3rd operation mode was consistent with the operation mode that has only switch transistor T A2 conducting, the loss in the time of can reducing switching tube thus and between conducting and closure, operate.

The 4th operation mode: switch transistor T B1 conducting, rest switch Guan Jun ends; Current path is: DB1-TB1-D2-V _G-L1801-DB1.

The 5th operation mode: switch transistor T 2 and switch transistor T B1 conducting, rest switch Guan Jun ends; Current path is: PV0-V _G-L1801-DB1-TB1-T2-PV1-.

The 6th operation mode: switch transistor T B2 conducting, rest switch Guan Jun ends; Current path is: PV0-V _G-L1801-TB2-PV2-.

Wherein, Said the 6th operation mode can also be switch transistor T B2, switch transistor T 2 and switch transistor T B1 conducting; Rest switch Guan Jun ends, and promptly after the 5th operation mode finished, switch transistor T 2 can be selected not give closing with switch transistor T B1; This moment, the 6th operation mode was consistent with the operation mode that has only switch transistor T B2 conducting, the loss in the time of can reducing switching tube thus and between conducting and closure, operate.

The 7th operation mode: switch transistor T A1 conducting, switch transistor T 1 and switch transistor T A1 conducting or switch transistor T 1 and switch transistor T A1 and switch transistor T A2 conducting, rest switch Guan Jun ends; Current path is: CA2-V _G-L1801-DA2-CA2.

The 8th operation mode: switch transistor T B1 conducting, switch transistor T 2 and switch transistor T B1 conducting or switch transistor T 2 and switch transistor T B1 and switch transistor T B2 conducting, rest switch Guan Jun ends; Current path is: CB2-DB2-L1801-V _G-CB2.

Have and above-mentionedly know, the five-electrical level inverter embodiment four that the application provides adopts the sinusoidal wave thinking of five Level Technology matches, and common-mode voltage is little with respect to prior art, and the ripple loss is lower, and conversion efficiency is higher.Wherein, eight operation modes of the five level inverse conversion topology unit embodiment three that the application provides when realizing the conversion of direct current and alternating current, similar with the application embodiment four described eight operation modes, repeat no more at this.

With reference to Figure 20, it shows five level inverse conversion topology unit embodiment, one isoboles that the application provides.In said isoboles, first ac output end of said five level inverse conversion topology unit embodiment one is defined as the AC exit of topology unit.

With reference to Figure 21, it shows five level inverse conversion topology unit embodiment, three isoboleses that the application provides.In said isoboles, first ac output end of said five level inverse conversion topology unit embodiment three is defined as the AC exit of topology unit.

With reference to Figure 22; It shows the topological diagram of a kind of five-electrical level inverter embodiment five that the application provides; Based on above-mentioned the application embodiment one or the application embodiment three, the application embodiment five comprise two like the topology unit of Figure 20 or two like the described topology unit of Figure 21: first topology unit and second topology unit;

The first direct current positive level PV1+ links to each other with each first direct-flow input end M1 of first topology unit and second topology unit;

The first direct current negative level PV1-links to each other with each second direct-flow input end M2 of first topology unit and second topology unit;

The second direct current positive level PV2+ links to each other with each the 3rd direct-flow input end M3 of first topology unit and second topology unit;

The second direct current negative level PV2-links to each other with each the 4th direct-flow input end M4 of first topology unit and second topology unit;

Direct current zero level PV0 links to each other with each the 5th direct-flow input end M5 of first topology unit and second topology unit;

The connecting line of capacitor C A1 and capacitor C B1 links to each other with the connecting line of capacitor C A2 and capacitor C B2 and links to each other with the 5th direct-flow input end M5 of first topology unit or second topology unit;

First topology unit links to each other with second ac output end with first ac output end of this inverter respectively with each AC exit in second topology unit.

Wherein, with reference to Figure 23, it shows another topological diagram of the application embodiment five, and like the described embodiment of Figure 22, said five-electrical level inverter also comprises inductance L 2301, inductance L 2302 and capacitor C 2301 based on above-mentioned, wherein:

The AC exit of first topology unit links to each other with the AC exit of second topology unit through inductance L 2301, capacitor C 2301 and the inductance L 2302 of series connection successively;

The connecting line of inductance L 2301 and capacitor C 2301 links to each other with first ac output end of this inverter, and the connecting line of capacitor C 2301 and inductance L 2302 links to each other with second ac output end of this inverter.

Have and above-mentionedly know; All press measure and bigger RC absorption circuit to prevent the two ends overvoltage of part diode and cause the problem that inverter is bulky, cost increases, loss is more and efficient is lower with respect to adopting in the prior art, the five level inverse conversion topology unit that the application provides are realizing that two corresponding times spent when assurance provides path for electric current, guaranteed that the semiconductor device of whole inverter was less; Volume is less; Cost is lower, and loss simultaneously is less, and efficient is higher.

With reference to Figure 24; It shows the topological diagram of a kind of five-electrical level inverter embodiment six that the application provides; Based on above-mentioned the application embodiment one or the application embodiment three, the application embodiment six comprise three like the topology unit of Figure 20 or three like the described topology unit of Figure 21: first topology unit, second topology unit and the 3rd topology unit;

The first direct current positive level PV1+ links to each other with each first direct-flow input end M1 of first topology unit, second topology unit and the 3rd topology unit; The first direct current negative level PV1-links to each other with each second direct-flow input end M2 of first topology unit, second topology unit and the 3rd topology unit;

The second direct current positive level PV2+ links to each other with each the 3rd direct-flow input end M3 of first topology unit, second topology unit and the 3rd topology unit; The second direct current negative level PV2-links to each other with each the 4th direct-flow input end M4 of first topology unit, second topology unit and the 3rd topology unit;

Each AC exit in first topology unit, second topology unit and the 3rd topology unit links to each other with first ac output end, second ac output end and the 3rd ac output end of this inverter respectively.

Wherein, With reference to Figure 25, it shows another topological diagram of the application embodiment six, based on above-mentioned like the described embodiment of Figure 24; Said five-electrical level inverter also comprises inductance L 2501, inductance L 2502, inductance L 2503, capacitor C 2501, capacitor C 2502 and capacitor C 2503, wherein:

The AC exit of first topology unit links to each other with the AC exit of second topology unit through inductance L 2501, capacitor C 2501, capacitor C 2502 and the inductance L 2502 of series connection successively;

The AC exit of the 3rd topology unit links to each other with the connecting line of capacitor C 2501 with capacitor C 2502 with capacitor C 2503 through the inductance L 2503 of series connection successively;

The connecting line of inductance L 2501 and capacitor C 2501 links to each other with first ac output end of this inverter; The connecting line of capacitor C 2502 and inductance L 2502 links to each other with second ac output end of this inverter, and the connecting line of inductance L 2503 and capacitor C 2503 links to each other with the 3rd ac output end of this inverter.

Have and above-mentionedly know; All press measure and bigger RC absorption circuit to prevent the two ends overvoltage of part diode and cause the problem that inverter is bulky, cost increases, loss is more and efficient is lower that the five level inverse conversion topology unit that the application provides when assurance provides path for electric current, guarantee that the semiconductor device of whole inverter is less when realizing three-phase applications with respect to adopting in the prior art; Volume is less; Cost is lower, and loss simultaneously is less, and efficient is higher.

Need to prove that above-mentioned five-electrical level inverter embodiment six is three-phase three-wire system (three a brachium pontis) five-electrical level inverter.

With reference to Figure 26, it shows the another kind of topological diagram of the application embodiment six, based on above-mentioned like the described embodiment of Figure 25, wherein:

The connecting line of capacitor C 2501, capacitor C 2502 and capacitor C 2503 links to each other with direct current zero level PV0.Need to prove that five-electrical level inverter shown in figure 26 is three-phase four-wire system (three a brachium pontis) five-electrical level inverter.

With reference to Figure 27; It shows the topological diagram of a kind of five-electrical level inverter embodiment seven that the application provides; Based on above-mentioned the application embodiment one or the application embodiment three, the application embodiment seven comprise four like the topology unit of Figure 20 or four like the described topology unit of Figure 21: first topology unit, second topology unit, the 3rd topology unit and the 4th topology unit;

AC exit in first topology unit, second topology unit, the 3rd topology unit and the 4th topology unit links to each other with first ac output end, second ac output end, the 3rd ac output end and the 4th ac output end of this inverter respectively.

Wherein, With reference to Figure 28, it shows another topological diagram of the application embodiment seven, based on above-mentioned like the described embodiment of Figure 27; Said five-electrical level inverter also comprises inductance L 2801, inductance L 2802, inductance L 2803, capacitor C 2801, capacitor C 2802 and capacitor C 2803, wherein:

The AC exit of second topology unit links to each other with the AC exit of the 3rd topology unit through inductance L 2801, capacitor C 2801, capacitor C 2802 and the inductance L 2802 of series connection successively; The AC exit of the 4th topology unit links to each other with the connecting line of capacitor C 2801 with capacitor C 2802 with capacitor C 2803 through the inductance L 2803 of series connection successively;

The connecting line of capacitor C 2801, capacitor C 2802 and capacitor C 2803 links to each other with the AC exit of first topology unit; The connecting line of inductance L 2801 and capacitor C 2801 links to each other with first ac output end of this inverter; The connecting line of capacitor C 2802 and inductance L 2802 links to each other with second ac output end of this inverter, and the connecting line of inductance L 2803 and capacitor C 2803 links to each other with the 3rd ac output end of this inverter.

Have and above-mentionedly know; All press measure and bigger RC absorption circuit to prevent the two ends overvoltage of part diode and cause the problem that inverter is bulky, cost increases, loss is more and efficient is lower with respect to adopting in the prior art, the five level inverse conversion topology unit that the application provides are realizing that four corresponding times spent when assurance provides path for electric current, guaranteed that the semiconductor device of whole inverter was less; Volume is less; Cost is lower, and loss simultaneously is less, and efficient is higher.Need to prove that above-mentioned five-electrical level inverter embodiment seven is three-phase four-wire system (four a brachium pontis) five-electrical level inverter.

Need to prove that each embodiment in this specification all adopts the mode of going forward one by one to describe, what each embodiment stressed all is and the difference of other embodiment that identical similar part is mutually referring to getting final product between each embodiment.

At last; Also need to prove; In this article; Relational terms such as first and second grades only is used for an entity or operation are made a distinction with another entity or operation, and not necessarily requires or hint relation or the order that has any this reality between these entities or the operation.And; Term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability; Thereby make and comprise that process, method, article or the equipment of a series of key elements not only comprise those key elements; But also comprise other key elements of clearly not listing, or also be included as this process, method, article or equipment intrinsic key element.Under the situation that do not having much more more restrictions, the key element that limits by statement " comprising ... ", and be not precluded within process, method, article or the equipment that comprises said key element and also have other identical element.

More than a kind of five level inverse conversion topology unit and five-electrical level inverter that the application provided have been carried out detailed introduction; Used concrete example among this paper the application's principle and execution mode are set forth, the explanation of above embodiment just is used to help to understand the application's method and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to the application's thought, the part that on embodiment and range of application, all can change, in sum, this description should not be construed as the restriction to the application.

Claims

1. a level inverse conversion topology unit is characterized in that, comprises switch transistor T 1, switch transistor T A1, switch transistor T A2, switch transistor T 2, switch transistor T B1, switch transistor T B2, diode D1, diode DA1, diode DB1 and diode D2;

Diode of the equal reverse parallel connection of each said switching tube;

2. five level inverse conversion topology unit according to claim 1 is characterized in that, eight corresponding operation modes of this five level inverse conversions topology unit are respectively:

First operation mode: switch transistor T 1 conducting, rest switch Guan Jun ends;

Second operation mode: switch transistor T 1 and switch transistor T A1 conducting, rest switch Guan Jun ends;

The 3rd operation mode: switch transistor T A2 conducting, rest switch Guan Jun ends; Or switch transistor T A2, switch transistor T 1 and switch transistor T A1 conducting, rest switch Guan Jun ends;

The 4th operation mode: switch transistor T 2 conductings, rest switch Guan Jun ends;

The 5th operation mode: switch transistor T 2 and switch transistor T B1 conducting, rest switch Guan Jun ends;

The 6th operation mode: switch transistor T B2 conducting, rest switch Guan Jun ends; Or switch transistor T B2, switch transistor T 2 and switch transistor T B1 conducting, rest switch Guan Jun ends;

The 7th operation mode: switch transistor T 1 conducting, switch transistor T 1 and switch transistor T A1 conducting or switch transistor T 1 and switch transistor T A1 and switch transistor T A2 conducting, rest switch Guan Jun ends;

The 8th operation mode: switch transistor T 2 conductings, switch transistor T 2 and switch transistor T B1 conducting or switch transistor T 2 and switch transistor T B1 and switch transistor T B2 conducting, rest switch Guan Jun ends.

3. a five-electrical level inverter is characterized in that, comprises one as power 1 or weigh 2 described topology unit, wherein:

4. a level inverse conversion topology unit is characterized in that, comprises switch transistor T 1, switch transistor T A1, switch transistor T A2, switch transistor T 2, switch transistor T B1, switch transistor T B2, diode D1, diode DA1, diode DB1, diode D2;

Diode of the equal reverse parallel connection of each said switching tube;

5. five level inverse conversion topology unit according to claim 4 is characterized in that, eight corresponding operation modes of this five level inverse conversions topology unit are respectively:

First operation mode: switch transistor T A1 conducting, rest switch Guan Jun ends;

Second operation mode: switch transistor T A1 and switch transistor T 1 conducting, rest switch Guan Jun ends;

The 3rd operation mode: switch transistor T A2 conducting, rest switch Guan Jun ends; Or switch transistor T A1, switch transistor T 1 and switch transistor T A2 conducting, rest switch Guan Jun ends;

The 4th operation mode: switch transistor T B1 conducting, rest switch Guan Jun ends;

The 5th operation mode: switch transistor T B1 and switch transistor T 2 conductings, rest switch Guan Jun ends;

The 6th operation mode: switch transistor T B2 conducting, rest switch Guan Jun ends; Or switch transistor T B1, switch transistor T 2 and switch transistor T B2 conducting, rest switch Guan Jun ends;

The 7th operation mode: switch transistor T A1 conducting, switch transistor T A1 and switch transistor T 1 conducting or switch transistor T A1 and switch transistor T 1 and switch transistor T A2 conducting, rest switch Guan Jun ends;

The 8th mode: switch transistor T B1 conducting, switch transistor T B1 and switch transistor T 2 conductings or switch transistor T B1 and switch transistor T 2 and switch transistor T B2 conducting, rest switch Guan Jun ends.

6. a five-electrical level inverter is characterized in that, comprises one as power 4 or weigh 5 described topology unit, wherein:

7. a five-electrical level inverter is characterized in that, comprises two as power 1 or weighs 2 described topology unit or two as power 4 or weigh 5 described topology unit: first topology unit and second topology unit;

8. a five-electrical level inverter is characterized in that, comprises three as power 1 or weighs 2 described topology unit or three as power 4 or weigh 5 described topology unit: first topology unit, second topology unit and the 3rd topology unit;

The first direct current positive level PV1+ links to each other with each first direct-flow input end M1 of first topology unit, second topology unit and the 3rd topology unit;

The first direct current negative level PV1-links to each other with each second direct-flow input end M2 of first topology unit, second topology unit and the 3rd topology unit;

9. a five-electrical level inverter is characterized in that, comprises four as power 1 or weighs 2 described topology unit or four as power 4 or weigh 5 described topology unit: first topology unit, second topology unit, the 3rd topology unit and the 4th topology unit;