CN102638191A

CN102638191A - Seven-level inversion topology unit and seven-level inverter

Info

Publication number: CN102638191A
Application number: CN2012101093733A
Authority: CN
Inventors: 宋炀; 汪洪亮
Original assignee: Sungrow Power Supply Co Ltd
Current assignee: Sungrow Power Supply Co Ltd
Priority date: 2012-04-13
Filing date: 2012-04-13
Publication date: 2012-08-15

Abstract

The invention provides a seven-level inversion topology unit and a seven-level inverter, wherein the seven-level inversion topology unit comprises eight switching tubes and six diodes connected with the eight switching tubes in series. In the prior art, a voltage-sharing manner and a larger RC (remote control) absorbing circuit are used to solve problems that the inverter has huge volume, cost increase, large loss and low efficiency because of overvoltage at two ends of a part of diodes; and the seven-level inversion topology unit has the advantages that a passage is provided for current for sure when single-phase and multiple-phase applications are realized, and the whole inverter has fewer semiconductor devices, smaller volume and higher efficiency and is low in cost and loss; simultaneously, different voltages are provided for the direct current of the seven-level inverter by seven levels so that the current conversion precision is improved.

Description

A kind of seven level inverse conversion topology unit and seven electrical level inverters

Technical field

The application relates to electric and electronic technical field, particularly a kind of seven level inverse conversion topology unit and seven electrical level inverters.

Background technology

The big capacity occasion of middle pressure, multi-electrical level inverter is widely used, and present five-electrical level inverter mainly is a diode-clamped.Introduce in the face of the diode-clamped five-level inverter down.

Referring to Fig. 1, this figure is the five-electrical level inverter topological diagram of the diode-clamped that provides in the prior art.

Shown in Figure 1 is the topological structure of half-bridge five-electrical level inverter.Diode is used to each switching tube and carries out voltage clamp.For example, the first diode DB1 is used for the voltage clamp of switch transistor T 1 lower end is positioned at the lower end of first capacitor C 1; The second diode DB2 is used for the voltage clamp of switch transistor T 5 lower ends is positioned at the lower end of first capacitor C 1.Other diodes DB3, DB4, DB5 and DB6 are similar, repeat no more at this.

Because clamping diode need be blocked many times of level voltages, need the diode series connection of a plurality of same nominal values usually, these diodes are together in series and bear the voltage that diode DB2 bears among Fig. 1 jointly.Because the dispersiveness of diode and the influence of stray parameter, the pressure that the diode that nominal value is identical can bear be difference to some extent also, being together in series like this to cause the diode two ends overvoltage that has.Therefore, need all press measure and very big RC to absorb circuit, but will cause systems bulky like this, cost increases, and loss is more, and efficient is lower.Simultaneously, because the direct current of existing five-electrical level inverter provides different voltages by five level, make that thus the current conversion precision is lower.

Summary of the invention

The application's technical problem to be solved provides a kind of seven level inverse conversion topology unit and seven electrical level inverters; Bulky in order to inverter system in the solution prior art, cost increases, and loss is more; The technical problem that efficient is lower, the current conversion precision is lower; Simultaneously, also in order to solve because the direct current of existing five-electrical level inverter provides different voltages by five level, make the technical problem that the current conversion precision is lower thus.

The application provides a kind of seven level inverse conversion topology unit, comprises switch transistor T A1, switch transistor T A2, switch transistor T A3, switch transistor T 1, switch transistor T B1, switch transistor T B2, switch transistor T B3, switch transistor T 2, diode DA1, diode DA2, diode D1, diode DB1, diode DB2 and diode D2;

Switch transistor T A1, switch transistor T A2, switch transistor T A3, switch transistor T B1, switch transistor T B2 and switch transistor T B3 be diode of reverse parallel connection respectively;

The first direct-flow input end M1 of this topology unit links to each other with the second direct-flow input end M2 of this topology unit through switch transistor T A1, diode DA1, diode DB1 and the switch transistor T B1 of series connection successively;

The 3rd direct-flow input end M3 of this topology unit links to each other with the 4th direct-flow input end M4 of this topology unit through switch transistor T A2, diode DA2, diode DB2 and the switch transistor T B2 of series connection successively;

The 5th direct-flow input end M5 of this topology unit links to each other with the 6th direct-flow input end M6 of this topology unit with switch transistor T B3 through the switch transistor T A3 of series connection successively;

The connecting line of the connecting line of diode DA1 and diode DB1, diode DA2 and diode DB2 links to each other with the connecting line of switch transistor T B3 with switch transistor T A3, and links to each other with the 7th direct-flow input end M7 of this topology unit with diode D2 through the switch transistor T 1 of series connection successively;

The 7th direct-flow input end M7 of this topology unit links to each other with the connecting line of diode DB1 with diode DA1 with diode D1 through the switch transistor T 2 of series connection successively;

The connecting line of diode DA1 and diode DB1 links to each other with first ac output end of this topology unit, and the connecting line of diode D2 and switch transistor T 2 links to each other with second ac output end of this topology unit.

The application also provides a kind of seven electrical level inverters, comprises one as above-mentioned topology unit, wherein:

The first direct current positive level PV1+ links to each other with the first direct-flow input end M1; The second direct current positive level PV2+ links to each other with the 3rd direct-flow input end M3; The 3rd direct current positive level PV3+ links to each other with the 5th direct-flow input end M5, and direct current zero level PV0 links to each other with the 7th direct-flow input end M7, and the first direct current negative level PV1-links to each other with the second direct-flow input end M2; The second direct current negative level PV2-links to each other with the 4th direct-flow input end M4, and the 3rd direct current negative level PV3-links to each other with the 6th direct-flow input end M6;

The connecting line of the first direct current positive level PV1+ and the first direct-flow input end M1 links to each other with the connecting line of the first direct current negative level PV1-and the second direct-flow input end M2 with capacitor C B1 through the capacitor C A1 of series connection successively;

The connecting line of the second direct current positive level PV2+ and the 3rd direct-flow input end M3 links to each other with the connecting line of the second direct current negative level PV2-and the 4th direct-flow input end M4 with capacitor C B2 through the capacitor C A2 of series connection successively;

The connecting line of the 3rd direct current positive level PV3+ and the 5th direct-flow input end M5 links to each other with the connecting line of the 3rd direct current negative level PV3-and the 6th direct-flow input end M6 with capacitor C B3 through the capacitor C A3 of series connection successively;

The connecting line of the connecting line of capacitor C A1 and capacitor C B1, capacitor C A2 and capacitor C B2 links to each other with the connecting line of capacitor C B3 with capacitor C A3, and links to each other with the 7th direct-flow input end M7;

First ac output end of topology unit links to each other with first ac output end of this inverter, and second ac output end of topology unit links to each other with second ac output end of this inverter.

The application also provides a kind of seven electrical level inverters, comprises two above topology unit: first topology unit and second topology unit, wherein:

The first direct current positive level PV1+ links to each other with each first direct-flow input end M1 of first topology unit and second topology unit;

The first direct current negative level PV1-links to each other with each second direct-flow input end M2 of first topology unit and second topology unit;

The connecting line of the first direct current positive level PV1+ and the first direct-flow input end M1 of first topology unit or second topology unit links to each other with second direct-flow input end M2 of first topology unit or second topology unit and the connecting line of the first direct current negative level PV1-with capacitor C B1 through the capacitor C A1 of series connection successively;

The second direct current positive level PV2+ links to each other with each the 3rd direct-flow input end M3 of first topology unit and second topology unit;

The second direct current negative level PV2-links to each other with each the 4th direct-flow input end M4 of first topology unit and second topology unit;

The connecting line of the second direct current positive level PV2+ and the 3rd direct-flow input end M3 of first topology unit or second topology unit links to each other with the 4th direct-flow input end M4 of first topology unit or second topology unit and the connecting line of the second direct current negative level PV2-with capacitor C B2 through the capacitor C A2 of series connection successively;

The 3rd direct current positive level PV3+ links to each other with each the 5th direct-flow input end M5 of first topology unit and second topology unit;

The 3rd direct current negative level PV3-links to each other with each the 6th direct-flow input end M6 of first topology unit and second topology unit;

The connecting line of the 3rd direct current positive level PV3+ and the 5th direct-flow input end M5 of first topology unit or second topology unit links to each other with the 6th direct-flow input end M6 of first topology unit or second topology unit and the connecting line of the 3rd direct current negative level PV3-with capacitor C B3 through the capacitor C A3 of series connection successively;

Direct current zero level PV0 links to each other with each the 7th direct-flow input end M7 of first topology unit and second topology unit;

The connecting line of the connecting line of capacitor C A1 and capacitor C B1, capacitor C A2 and capacitor C B2 links to each other with the connecting line of capacitor C B3 with capacitor C A3, and links to each other with the 7th direct-flow input end M7 of first topology unit or second topology unit;

Each first ac output end in first topology unit and second topology unit links to each other with second ac output end with first ac output end of this inverter respectively.

The application also provides a kind of seven electrical level inverters, comprises three above topology unit: first topology unit, second topology unit and the 3rd topology unit;

The first direct current positive level PV1+ links to each other with each first direct-flow input end M1 of first topology unit, second topology unit and the 3rd topology unit;

The first direct current negative level PV1-links to each other with each second direct-flow input end M2 of first topology unit, second topology unit and the 3rd topology unit;

The connecting line of the first direct current positive level PV1+ and the first direct-flow input end M1 of first topology unit, second topology unit or the 3rd topology unit links to each other with second direct-flow input end M2 of first topology unit, second topology unit or the 3rd topology unit and the connecting line of the first direct current negative level PV1-with capacitor C B1 through the capacitor C A1 of series connection successively;

The second direct current positive level PV2+ links to each other with each the 3rd direct-flow input end M3 of first topology unit, second topology unit and the 3rd topology unit;

The second direct current negative level PV2-links to each other with each the 4th direct-flow input end M4 of first topology unit, second topology unit and the 3rd topology unit;

The connecting line of the second direct current positive level PV2+ and the 3rd direct-flow input end M3 of first topology unit, second topology unit or the 3rd topology unit links to each other with the 4th direct-flow input end M4 of first topology unit, second topology unit or the 3rd topology unit and the connecting line of the second direct current negative level PV2-with capacitor C B2 through the capacitor C A2 of series connection successively;

The 3rd direct current positive level PV3+ links to each other with each the 5th direct-flow input end M5 of first topology unit, second topology unit and the 3rd topology unit;

The 3rd direct current negative level PV3-links to each other with each the 6th direct-flow input end M6 of first topology unit, second topology unit and the 3rd topology unit;

The connecting line of the 3rd direct current positive level PV3+ and the 5th direct-flow input end M5 of first topology unit, second topology unit or the 3rd topology unit links to each other with the 6th direct-flow input end M6 of first topology unit, second topology unit or the 3rd topology unit and the connecting line of the 3rd direct current negative level PV3-with capacitor C B3 through the capacitor C A3 of series connection successively;

Direct current zero level PV0 links to each other with each the 7th direct-flow input end M7 of first topology unit, second topology unit and the 3rd topology unit;

The connecting line of the connecting line of capacitor C A1 and capacitor C B1, capacitor C A2 and capacitor C B2 links to each other with the connecting line of capacitor C B3 with capacitor C A3, and links to each other with the 7th direct-flow input end M7 of first topology unit, second topology unit or the 3rd topology unit;

Each first ac output end in first topology unit, second topology unit and the 3rd topology unit links to each other with three ac output ends of this inverter respectively.

The application also provides a kind of seven electrical level inverters, comprises four above topology unit: first topology unit, second topology unit, the 3rd topology unit and the 4th topology unit;

The first direct current positive level PV1+ links to each other with each first direct-flow input end M1 of first topology unit, second topology unit, the 3rd topology unit and the 4th topology unit;

The first direct current negative level PV1-links to each other with each second direct-flow input end M2 of first topology unit, second topology unit, the 3rd topology unit and the 4th topology unit;

The connecting line of the first direct current positive level PV1+ and the first direct-flow input end M1 of first topology unit, second topology unit, the 3rd topology unit or the 4th topology unit links to each other with second direct-flow input end M2 of first topology unit, second topology unit, the 3rd topology unit or the 4th topology unit and the connecting line of the first direct current negative level PV1-with capacitor C B1 through the capacitor C A1 of series connection successively;

The second direct current positive level PV2+ links to each other with each the 3rd direct-flow input end M3 of first topology unit, second topology unit, the 3rd topology unit and the 4th topology unit;

The second direct current negative level PV2-links to each other with each the 4th direct-flow input end M4 of first topology unit, second topology unit, the 3rd topology unit and the 4th topology unit;

The connecting line of the second direct current positive level PV2+ and the 3rd direct-flow input end M3 of first topology unit, second topology unit, the 3rd topology unit or the 4th topology unit links to each other with the 4th direct-flow input end M4 of first topology unit, second topology unit, the 3rd topology unit or the 4th topology unit and the connecting line of the second direct current negative level PV2-with capacitor C B2 through the capacitor C A2 of series connection successively;

The 3rd direct current positive level PV3+ links to each other with each the 5th direct-flow input end M5 of first topology unit, second topology unit, the 3rd topology unit and the 4th topology unit;

The 3rd direct current negative level PV3-links to each other with each the 6th direct-flow input end M6 of first topology unit, second topology unit, the 3rd topology unit and the 4th topology unit;

The connecting line of the 3rd direct current positive level PV3+ and the 5th direct-flow input end M5 of first topology unit, second topology unit, the 3rd topology unit or the 4th topology unit links to each other with the 6th direct-flow input end M6 of first topology unit, second topology unit, the 3rd topology unit or the 4th topology unit and the connecting line of the 3rd direct current negative level PV3-with capacitor C B3 through the capacitor C A3 of series connection successively;

Direct current zero level PV0 links to each other with each the 7th direct-flow input end M7 of first topology unit, second topology unit, the 3rd topology unit and the 4th topology unit;

The connecting line of the connecting line of capacitor C A1 and capacitor C B1, capacitor C A2 and capacitor C B2 links to each other with the connecting line of capacitor C B3 with capacitor C A3, and links to each other with the 7th direct-flow input end M7 of first topology unit, second topology unit, the 3rd topology unit or the 4th topology unit;

Each first ac output end in first topology unit, second topology unit, the 3rd topology unit and the 4th topology unit links to each other with first ac output end, second ac output end, the 3rd ac output end and the 4th ac output end of this inverter respectively.

From the above; The seven level inverse conversion topology unit that the application provides comprise eight switching tubes and six and switching tube diode in series; All press measure and bigger RC absorption circuit to prevent the two ends overvoltage of part diode and cause the problem that inverter is bulky, cost increases, loss is more and efficient is lower that the seven level inverse conversion topology unit that the application provides when assurance provides path for electric current, guarantee that the semiconductor device of whole inverter is less when realizing single-phase and heterogeneous application with respect to adopting in the prior art; Volume is less; Cost is lower, and loss simultaneously is less, and efficient is higher.Simultaneously, the direct current of seven electrical level inverters that the application provides provides different voltages by seven level, has improved the current conversion precision thus.

Certainly, arbitrary product of enforcement the application might not reach above-described all advantages simultaneously.

Description of drawings

In order to be illustrated more clearly in the technical scheme among the application embodiment; The accompanying drawing of required use is done to introduce simply in will describing embodiment below; Obviously, the accompanying drawing in describing below only is some embodiment of the application, for those of ordinary skills; Under the prerequisite of not paying creative work property, can also obtain other accompanying drawing according to these accompanying drawings.

Fig. 1 is diode-clamped five-level inverter topology figure in the prior art;

The topological diagram of a kind of seven level inverse conversion topology unit embodiment one that Fig. 2 provides for the application;

The topological diagram of a kind of seven electrical level inverter embodiment two that Fig. 3 provides for the application;

Another topological diagram of a kind of seven electrical level inverter embodiment two that Fig. 4 provides for the application;

Another topological diagram of a kind of seven electrical level inverter embodiment two that Fig. 5 provides for the application;

Another topological diagram of a kind of seven electrical level inverter embodiment two that Fig. 6 provides for the application;

A kind of seven electrical level inverter embodiment two that Fig. 7 provides for the application are in the topological diagram of first operation mode;

A kind of seven electrical level inverter embodiment two that Fig. 8 provides for the application are in the topological diagram of second operation mode;

A kind of seven electrical level inverter embodiment two that Fig. 9 provides for the application are in the topological diagram of the 3rd operation mode;

A kind of seven electrical level inverter embodiment two that Figure 10 provides for the application are in the topological diagram of the 4th operation mode;

A kind of seven electrical level inverter embodiment two that Figure 11 provides for the application are in the topological diagram of the 5th operation mode;

A kind of seven electrical level inverter embodiment two that Figure 12 provides for the application are in the topological diagram of the 6th operation mode;

A kind of seven electrical level inverter embodiment two that Figure 13 provides for the application are in the topological diagram of the 7th operation mode;

A kind of seven electrical level inverter embodiment two that Figure 14 provides for the application are in the topological diagram of the 8th operation mode;

A kind of seven electrical level inverter embodiment two that Figure 15 provides for the application are in the topological diagram of the 9th operation mode;

A kind of seven electrical level inverter embodiment two that Figure 16 provides for the application are in the topological diagram of the tenth operation mode;

The isoboles of a kind of seven level inverse conversion topology unit embodiment one that Figure 17 provides for the application;

The topological diagram of a kind of seven electrical level inverter embodiment three that Figure 18 passes through for the application;

Another topological diagram of a kind of seven electrical level inverter embodiment three that Figure 19 passes through for the application;

The topological diagram of a kind of seven electrical level inverter embodiment four that Figure 20 passes through for the application;

Another topological diagram of a kind of seven electrical level inverter embodiment four that Figure 21 passes through for the application;

Another topological diagram of a kind of seven electrical level inverter embodiment four that Figure 22 passes through for the application;

The topological diagram of a kind of seven electrical level inverter embodiment five that Figure 23 passes through for the application;

Another topological diagram of a kind of seven electrical level inverter embodiment five that Figure 24 passes through for the application.

Embodiment

To combine the accompanying drawing among the application embodiment below, the technical scheme among the application embodiment is carried out clear, intactly description, obviously, described embodiment only is the application's part embodiment, rather than whole embodiment.Based on the embodiment among the application, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the application's protection.

With reference to figure 2; It shows the topological diagram of a kind of seven level inverse conversion topology unit embodiment one that the application provides, and said seven level inverse conversion topology unit comprise switch transistor T A1, switch transistor T A2, switch transistor T A3, switch transistor T 1, switch transistor T B1, switch transistor T B2, switch transistor T B3, switch transistor T 2, diode DA1, diode DA2, diode D1, diode DB1, diode DB2 and diode D2;

Wherein, the above-mentioned switching tube of above topology unit can be managed for IGBT, MOSFET manages, IGCT manages or the IEGT pipe.It is understandable that above switching tube also can be selected the switching tube of other types.More than can be diode independently with the diode of switching tube reverse parallel connection, also can be the diode that integrates with the switching tube encapsulation.

Wherein, Among the application embodiment one; The order of connection of the order of connection of the order of connection of the order of connection of the order of connection of the order of connection of switch transistor T A1 and diode DA1, switch transistor T A2 and diode DA2, switch transistor T B2 and diode DB2, switch transistor T B1 and diode DB1, switch transistor T 2 and diode D1 and switch transistor T 1 and diode D2 all can be changed; Above-mentioned change based on the order of connection between the components and parts of series connection principle does not all break away from invention thought of the present invention, belongs to protection scope of the present invention.

Wherein, In above-mentioned seven level inverse conversion topology unit embodiment one; The connecting line of switch transistor T 1 and diode D2 can link to each other with the connecting line of switch transistor T 2 with diode D1; At this moment, when changing as if the order of connection of switch transistor T 1 and diode D2, the order of connection of switch transistor T 2 and diode D1 must be changed.

With reference to figure 3, it shows the topological diagram of a kind of seven electrical level inverter embodiment two that the application provides, and based on the application embodiment one, the application embodiment two comprises one like embodiment one described topology unit, wherein:

Wherein, As shown in Figure 4, above-mentioned seven level can add that four DC/DC booster circuits obtain through two DC power supply PVM and PVN, and are concrete; Two DC power supply PVM and the positive and negative butt joint of PVN; Generate the first direct current positive level PV1+, the first direct current negative level PV1-and direct current zero level PV0, two DC power supply PVM respectively are connected a DC/DC booster circuit S1 and S2 with PVN, generate the second direct current positive level PV2+ and the second direct current negative level PV2-; Two DC/DC booster circuit S1 respectively are connected a DC/DC booster circuit S3 and S4 with S2, generate the 3rd direct current positive level PV3+ and the 3rd direct current negative level PV3-.

With reference to figure 5, the another kind of structural representation that it shows the application embodiment two has above-mentioned embodiment as shown in Figure 4, and seven electrical level inverters that the application provides also comprise inductance L 501 and capacitor C 501, wherein;

The connecting line of diode D2 and switch transistor T 2 links to each other in inductance L 501 and the capacitor C 501 of first ac output end of said topology unit through series connection successively and this topology unit;

The connecting line of inductance L 501 and capacitor C 501 links to each other with first ac output end of this inverter.

Above-mentioned seven level as shown in Figure 4 can also be through obtaining like the described mode of Fig. 6; DC power supply PVS produces the first direct current positive level PV1+ and the first direct current negative level PV1-; Dividing potential drop effect through capacitor C A1 and capacitor C B1 produces direct current zero level PV0; DC power supply PVS two ends respectively connect a DC/DC booster circuit H1 and H2; Generate the second direct current positive level PV2+ and the second direct current negative level PV2-, two DC/DC booster circuit H1 respectively are connected a DC/DC booster circuit H3 and H4 with H2, generate the 3rd direct current positive level PV3+ and the 3rd direct current negative level PV3-.

From the above, the application realizes the practical application of the application embodiment two through increasing inductance and electric capacity, reduces the harmonic wave of the output current of the application embodiment two, improves the accuracy of the application embodiment two when carrying out current conversion.

The syndeton of the filtration module that the syndeton of the filtration module that seven electrical level inverters shown in Figure 5 and inductance and electric capacity form and seven electrical level inverters as shown in Figure 6 and inductance and electric capacity form is similar, repeats no more at this.

From the above; All press measure and bigger RC absorption circuit to prevent the two ends overvoltage of part diode and cause the problem that inverter is bulky, cost increases, loss is more and efficient is lower with respect to needing in the prior art to adopt; The seven electrical level inverter embodiment two that the application provides, promptly the application embodiment one when assurance provides path for electric current, guarantees that the semiconductor device of whole inverter is less when realization is single-phase; Volume is less; Cost is lower, and loss simultaneously is less, and efficient is higher.Simultaneously, the direct current of the application embodiment two provides different voltages by seven level, has improved the current conversion precision thus.

Wherein, the seven electrical level inverter embodiment two that the application provides comprise ten operation modes when realizing the conversion of direct current and alternating current, come ten operation modes of seven electrical level inverters shown in Fig. 5 are carried out labor below in conjunction with accompanying drawing.

Wherein, diode DA3 and switch transistor T A3 reverse parallel connection, diode DB3 and switch transistor T B3 reverse parallel connection.The operation mode of the application embodiment two forms and can realize through SECO.

With reference to figure 7, it shows the topological diagram of first operation mode of the seven electrical level inverter embodiment two that the application provides, first operation mode:

Switch transistor T 2 conductings, rest switch Guan Jun ends; Wherein, the path of not conducting illustrates with fine line in the drawings, and the path of conducting illustrates with heavy line.

Current path is: T2-D1-L501-V _G-T2.

With reference to figure 8, it shows the topological diagram of seven electrical level inverter embodiment, 2 second operation modes that the application provides.Second operation mode: switch transistor T A1 conducting, the rest switch pipe ends; Wherein, the path of not conducting illustrates with fine line in the drawings, and the path of conducting illustrates with heavy line.

Current path is: PV1+-TA1-DA1-L501-V _G-PV0.

Wherein, Said second operation mode can also be: switch transistor T 2 and switch transistor T A1 conducting; Rest switch Guan Jun ends, and promptly after first operation mode finished, switch transistor T 2 can be selected not give closing; This moment second operation mode with have only switch transistor T A1 conductive current path consistent, the loss in the time of can reducing switching tube thus and between conducting and closure, operate.

With reference to figure 9, it shows the topological diagram of the 3rd operation mode of the seven electrical level inverter embodiment two that the application provides.The 3rd operation mode: switch transistor T A2 conducting, the rest switch pipe ends; Wherein, the path of not conducting illustrates with fine line in the drawings, and the path of conducting illustrates with heavy line.

Current path is: PV2+-TA2-DA2-L501-V _G-PV0.

Wherein, said the 3rd operation mode can also for: at least one the switching tube conducting in switch transistor T A1 and the switch transistor T 2, and switch transistor T A2 conducting, rest switch Guan Jun ends.For example: switch transistor T A2 and switch transistor T 2 conductings, rest switch Guan Jun ends; Or switch transistor T A2 and switch transistor T A1 conducting, rest switch Guan Jun ends; Or switch transistor T A2, switch transistor T A1 and switch transistor T 2 conductings; Rest switch Guan Jun ends; Promptly after second operation mode finishes, can select not give closing to the switching tube of conducting when second operation mode, or the part switching tube is selected to close; This moment the 3rd operation mode with have only switch transistor T A2 conductive current path consistent, the loss in the time of can reducing switching tube thus and between conducting and closure, operate.

With reference to Figure 10, it shows the topological diagram of the 4th operation mode of the seven electrical level inverter embodiment two that the application provides.The 4th operation mode: switch transistor T A3 conducting, the rest switch pipe ends; Wherein, the path of not conducting illustrates with fine line in the drawings, and the path of conducting illustrates with heavy line.

Current path is: PV3+-TA3-L501-V _G-PV0.

Wherein, said the 4th operation mode can also for: at least one the switching tube conducting in switch transistor T A2, switch transistor T A1 and the switch transistor T 2, and switch transistor T A3 conducting, rest switch Guan Jun ends.For example: switch transistor T A3 and switch transistor T 2 conductings, rest switch Guan Jun ends; Or switch transistor T A3, switch transistor T A2 and switch transistor T A1 conducting, rest switch Guan Jun ends; Or switch transistor T A3, switch transistor T 2 and switch transistor T A2 conducting, rest switch Guan Jun ends; Or switch transistor T A3, switch transistor T 2, switch transistor T A1 and switch transistor T A2 conducting; Rest switch Guan Jun ends etc., promptly after the 3rd operation mode finishes, can select not give closing to the switching tube of conducting when the 3rd operation mode; Or the part switching tube is selected to close; At this moment, the 4th operation mode with have only switch transistor T A3 conductive current path consistent, can reduce switching tube loss during operation and between closing thus in conducting.

With reference to Figure 11, it shows the topological diagram of the 5th operation mode of the seven electrical level inverter embodiment two that the application provides, the 5th operation mode:

Switch transistor T 1 conducting, rest switch Guan Jun ends; Wherein, the path of not conducting illustrates with fine line in the drawings, and the path of conducting illustrates with heavy line.

Current path is: T1-D2-V _G-L501-T1.

With reference to Figure 12, it shows the topological diagram of seven electrical level inverter embodiment 2 the 6th operation mode that the application provides.The 6th operation mode: switch transistor T B1 conducting, the rest switch pipe ends; Wherein, the path of not conducting illustrates with fine line in the drawings, and the path of conducting illustrates with heavy line.

Current path is: PV0-V _G-L501-DB1-TB1-PV1-.

Wherein, Said the 6th operation mode can also be: switch transistor T 1 and switch transistor T B1 conducting; Rest switch Guan Jun ends, and promptly after the 5th operation mode finished, switch transistor T 1 can be selected not give closing; This moment the 6th operation mode with have only switch transistor T B1 conductive current path consistent, the loss in the time of can reducing switching tube thus and between conducting and closure, operate.

With reference to Figure 13, it shows the topological diagram of the 7th operation mode of the seven electrical level inverter embodiment two that the application provides.The 7th operation mode: switch transistor T B2 conducting, the rest switch pipe ends; Wherein, the path of not conducting illustrates with fine line in the drawings, and the path of conducting illustrates with heavy line.

Current path is: PV0-V _G-L501-DB2-TB2-PV2-.

Wherein, said the 7th operation mode can also for: or at least one switching tube conducting in switch transistor T B1 and the switch transistor T 1, and switch transistor T B2 conducting, rest switch Guan Jun ends.For example: switch transistor T B2 and switch transistor T 1 conducting, rest switch Guan Jun ends; Or switch transistor T B2, switch transistor T 1 and switch transistor T B1 conducting; Rest switch Guan Jun ends; Promptly after the 6th operation mode finishes, can select not give closing to the switching tube of conducting when the 6th operation mode, or the part switching tube is selected to close; This moment the 7th operation mode with have only switch transistor T B2 conductive current path consistent, the loss in the time of can reducing switching tube thus and between conducting and closure, operate.

With reference to Figure 14, it shows the topological diagram of the 8th operation mode of the seven electrical level inverter embodiment two that the application provides.The 8th operation mode: switch transistor T B3 conducting, the rest switch pipe ends; Wherein, the path of not conducting illustrates with fine line in the drawings, and the path of conducting illustrates with heavy line.

Current path is: PV0-V _G-L501-TB3-PV3-.

Wherein, said the 8th operation mode can also be at least one the switching tube conducting in switch transistor T B2, switch transistor T B1 and the switch transistor T 1, and switch transistor T B3 conducting.For example: switch transistor T B3 and switch transistor T 1 conducting, rest switch Guan Jun ends; Or switch transistor T B3, switch transistor T B1 and switch transistor T B2 conducting, rest switch Guan Jun ends; Switch transistor T B3, switch transistor T B2 and switch transistor T 1 conducting, rest switch Guan Jun ends; Or switch transistor T B3, switch transistor T 1, switch transistor T B1 and switch transistor T B2 all end; Rest switch Guan Jun ends etc., promptly after the 7th operation mode finishes, can select not give closing to the switching tube of conducting when the 7th operation mode; Or the part switching tube is selected to close; At this moment, the 8th operation mode with have only switch transistor T A3 conductive current path consistent, the loss in the time of can reducing switching tube thus and between conducting and closure, operate.

With reference to Figure 15, it shows the topological diagram of seven electrical level inverter embodiment 2 the 9th operation mode that the application provides.The 9th operation mode: switch transistor T 2 conductings, rest switch Guan Jun end; The path of not conducting illustrates with fine line in the drawings, and the path of conducting illustrates with heavy line.

Current path is: CA3-V _G-L501-DA3-CA3.

Wherein, said the 9th operation mode can also for: at least one the switching tube conducting among switch transistor T A1, switch transistor T A2 and the switch transistor T A3, and switch transistor T 2 conductings, rest switch Guan Jun ends.Be switch transistor T 2 conductings, rest switch Guan Jun ends; Switch transistor T 2 and switch transistor T A1 conducting, rest switch Guan Jun ends; Switch transistor T 2 and switch transistor T A1 and switch transistor T A2 conducting, rest switch Guan Jun ends; Or switch transistor T 2 and switch transistor T A1 and switch transistor T A2 and switch transistor T A3 conducting, rest switch Guan Jun ends etc.Promptly the switching tube of conducting can be selected not give closing before the 9th operation mode begins, at this moment, the 9th operation mode with have only switch transistor T 2 conductive current path consistent, the loss in the time of can reducing switching tube thus and between conducting and closure, operate.

With reference to Figure 16, it shows the topological diagram of the tenth operation mode of the seven electrical level inverter embodiment two that the application provides.The tenth operation mode: switch transistor T 1 conducting, rest switch Guan Jun end; The path of not conducting illustrates with fine line in the drawings, and the path of conducting illustrates with heavy line.

Current path is: CB3-DB3-L501-V _G-CB3.

Wherein, said the tenth operation mode can also for: at least one the switching tube conducting among switch transistor T B1, switch transistor T B2 and the switch transistor T B3, and switch transistor T 1 conducting, rest switch Guan Jun ends.Be switch transistor T 1 and switch transistor T B1 conducting, switch transistor T 1 and switch transistor T B1 and switch transistor T B2 conducting or switch transistor T 1 and switch transistor T B1 and switch transistor T B2 and switch transistor T B3 conducting, rest switch Guan Jun ends etc.Promptly the switching tube of conducting can be selected not give closing before the tenth operation mode begins, at this moment, the tenth operation mode with have only switch transistor T 1 conductive current path consistent, the loss in the time of can reducing switching tube thus and between conducting and closure, operate.

Have and above-mentionedly know, the seven electrical level inverter embodiment two that the application provides adopt the sinusoidal wave thinking of seven Level Technology matches, and common-mode voltage is little with respect to prior art, and the ripple loss is lower, and conversion efficiency is higher.

Wherein, ten operation modes of the seven level inverse conversion topology unit embodiment one that the application provides when realizing the conversion of direct current and alternating current, similar with Fig. 7 among the application embodiment two to operation mode shown in Figure 16, repeat no more at this.

With reference to Figure 17, it shows seven level inverse conversion topology unit embodiment, one isoboles that the application provides.In said isoboles, first ac output end of said seven level inverse conversion topology unit embodiment one is defined as the AC exit of topology unit.

With reference to Figure 18, it shows the topological diagram of a kind of seven electrical level inverter embodiment three that the application provides, and based on above-mentioned the application embodiment one, the application embodiment three comprises two topology unit shown in figure 17: first topology unit and second topology unit;

Wherein, with reference to Figure 19, it shows another topological diagram of the application embodiment three, and like the described embodiment of Figure 18, said seven electrical level inverters also comprise first inductance L 1901, second inductance L 1902 and capacitor C 1901 based on above-mentioned, wherein:

The AC exit of first topology unit links to each other with the AC exit of second topology unit with second inductance L 1902 through first inductance L 1901, the capacitor C 1901 of series connection successively;

The connecting line of first inductance L 1901 and capacitor C 1901 links to each other with first ac output end of this inverter, and the connecting line of the capacitor C 1901 and second inductance L 1902 links to each other with second ac output end of this inverter.

Have and above-mentionedly know; All press measure and bigger RC absorption circuit to prevent the two ends overvoltage of part diode and cause the problem that inverter is bulky, cost increases, loss is more and efficient is lower with respect to adopting in the prior art, the seven level inverse conversion topology unit that the application provides are realizing that two corresponding times spent when assurance provides path for electric current, guaranteed that the semiconductor device of whole inverter was less; Volume is less; Cost is lower, and loss simultaneously is less, and efficient is higher.Simultaneously, the direct current of the application embodiment three provides different voltages by seven level, has improved the current conversion precision thus.

With reference to Figure 20; It shows the topological diagram of a kind of seven electrical level inverter embodiment four that the application provides; Based on above-mentioned the application embodiment one, the application embodiment four comprises three topology unit like Figure 17: first topology unit, second topology unit and the 3rd topology unit;

Wherein, With reference to Figure 21; It shows another topological diagram of the application embodiment four; Like the described embodiment of Figure 20, said seven electrical level inverters also comprise first inductance L 2101, second inductance L 2102, the 3rd inductance L 2103, first capacitor C 2101, second capacitor C 2102 and the 3rd capacitor C 2103 based on above-mentioned, wherein:

First inductance L 2101 of the AC exit of first topology unit through series connection successively, first capacitor C 2101, second capacitor C 2102 link to each other with the AC exit of second topology unit with second inductance L 2102;

The AC exit of the 3rd topology unit links to each other with the connecting line of the 3rd capacitor C 2103 with first capacitor C 2101 and first capacitor C 2102 through the 3rd inductance L 2103 of series connection successively;

The connecting line of first inductance L 2101 and first capacitor C 2101 links to each other with first ac output end of this inverter; The connecting line of second capacitor C 2102 and second inductance L 2102 links to each other with second ac output end of this inverter, and the connecting line of the 3rd inductance L 2103 and the 3rd capacitor C 2103 links to each other with the 3rd ac output end of this inverter.

Have and above-mentionedly know; All press measure and bigger RC absorption circuit to prevent the two ends overvoltage of part diode and cause the problem that inverter is bulky, cost increases, loss is more and efficient is lower that the seven level inverse conversion topology unit that the application provides when assurance provides path for electric current, guarantee that the semiconductor device of whole inverter is less when realizing three-phase applications with respect to adopting in the prior art; Volume is less; Cost is lower, and loss simultaneously is less, and efficient is higher.Simultaneously, the direct current of the application embodiment four provides different voltages by seven level, has improved the current conversion precision thus.

Need to prove that above-mentioned seven electrical level inverter embodiment four are three-phase three-wire system (three brachium pontis) seven electrical level inverters.

With reference to Figure 22, it shows the another kind of topological diagram of the application embodiment four, based on above-mentioned like the described embodiment of Figure 21, wherein:

The connecting line of first capacitor C 2101, second capacitor C 2102 and the 3rd capacitor C 2103 links to each other with direct current zero level PV0.Need to prove that seven electrical level inverters shown in figure 22 are three-phase four-wire system (three brachium pontis) seven electrical level inverters.

With reference to Figure 23; It shows the topological diagram of a kind of seven electrical level inverter embodiment five that the application provides; Based on above-mentioned the application embodiment one, the application embodiment five comprises four topology unit like Figure 17: first topology unit, second topology unit, the 3rd topology unit and the 4th topology unit;

Wherein, With reference to Figure 24; It shows another topological diagram of the application embodiment five; Like the described embodiment of Figure 23, said seven electrical level inverters also comprise first inductance L 2401, second inductance L 2402, the 3rd inductance L 2403, first capacitor C 2401, second capacitor C 2402 and the 3rd capacitor C 2403 based on above-mentioned, wherein:

First inductance L 2401 of the AC exit of second topology unit through series connection successively, first capacitor C 2401, second capacitor C 2402 link to each other with the AC exit of the 3rd topology unit with second inductance L 2402; The AC exit of the 4th topology unit links to each other with the connecting line of the 3rd capacitor C 2403 with first capacitor C 2401 and second capacitor C 2402 through the 3rd inductance L 2403 of series connection successively;

The connecting line of first capacitor C 2401, second capacitor C 2402 and the 3rd capacitor C 2403 links to each other with the AC exit of first topology unit; The connecting line of inductance the one L2401 and first capacitor C 2401 links to each other with first ac output end of this inverter; The connecting line of second capacitor C 2402 and second inductance L 2402 links to each other with second ac output end of this inverter, and the connecting line of the 3rd inductance L 2403 and the 3rd capacitor C 2403 links to each other with the 3rd ac output end of this inverter.

Have and above-mentionedly know; All press measure and bigger RC absorption circuit to prevent the two ends overvoltage of part diode and cause the problem that inverter is bulky, cost increases, loss is more and efficient is lower with respect to adopting in the prior art, the seven level inverse conversion topology unit that the application provides are realizing that four corresponding times spent when assurance provides path for electric current, guaranteed that the semiconductor device of whole inverter was less; Volume is less; Cost is lower, and loss simultaneously is less, and efficient is higher.Need to prove that above-mentioned seven electrical level inverter embodiment five are three-phase four-wire system (four brachium pontis) seven electrical level inverters.Simultaneously, the direct current of the application embodiment five provides different voltages by seven level, has improved the current conversion precision thus.

Need to prove that each embodiment in this specification all adopts the mode of going forward one by one to describe, what each embodiment stressed all is and the difference of other embodiment that identical similar part is mutually referring to getting final product between each embodiment.

At last; Also need to prove; In this article; Relational terms such as first and second grades only is used for an entity or operation are made a distinction with another entity or operation, and not necessarily requires or hint relation or the order that has any this reality between these entities or the operation.And; Term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability; Thereby make and comprise that process, method, article or the equipment of a series of key elements not only comprise those key elements; But also comprise other key elements of clearly not listing, or also be included as this process, method, article or equipment intrinsic key element.Under the situation that do not having much more more restrictions, the key element that limits by statement " comprising ... ", and be not precluded within process, method, article or the equipment that comprises said key element and also have other identical element.

More than a kind of seven level inverse conversion topology unit and seven electrical level inverters that the application provided have been carried out detailed introduction; Used concrete example among this paper the application's principle and execution mode are set forth, the explanation of above embodiment just is used to help to understand the application's method and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to the application's thought, the part that on embodiment and range of application, all can change, in sum, this description should not be construed as the restriction to the application.

Claims

1. level inverse conversion topology unit; It is characterized in that, comprise switch transistor T A1, switch transistor T A2, switch transistor T A3, switch transistor T 1, switch transistor T B1, switch transistor T B2, switch transistor T B3, switch transistor T 2, diode DA1, diode DA2, diode D1, diode DB1, diode DB2 and diode D2;

2. seven level inverse conversion topology unit according to claim 1 is characterized in that, the connecting line of switch transistor T 1 and diode D2 links to each other with the connecting line of switch transistor T 2 with diode D1.

3. seven level inverse conversion topology unit according to claim 1 and 2 is characterized in that, ten corresponding operation modes of this seven level inverse conversions topology unit are respectively:

First operation mode: switch transistor T 2 conductings, rest switch Guan Jun ends;

Second operation mode: switch transistor T A1 conducting, rest switch Guan Jun ends; Or switch transistor T 2 and switch transistor T A1 conducting, rest switch Guan Jun ends;

The 3rd operation mode: switch transistor T A2 conducting, rest switch Guan Jun ends; Or at least one the switching tube conducting in switch transistor T A1 and the switch transistor T 2, and switch transistor T A2 conducting, rest switch Guan Jun ends;

The 4th operation mode: switch transistor T A3 conducting, rest switch Guan Jun ends; Or at least one the switching tube conducting in switch transistor T A2, switch transistor T A1 and the switch transistor T 2, and switch transistor T A3 conducting, rest switch Guan Jun ends;

The 5th operation mode: switch transistor T 1 conducting, rest switch Guan Jun ends;

The 6th operation mode: switch transistor T B1 conducting, rest switch Guan Jun ends; Or switch transistor T 1 and switch transistor T B1 conducting, rest switch Guan Jun ends;

The 7th operation mode: switch transistor T B2 conducting, rest switch Guan Jun ends; Or at least one the switching tube conducting in switch transistor T B1 and the switch transistor T 1, and switch transistor T B2 conducting, rest switch Guan Jun ends;

The 8th operation mode: switch transistor T B3 conducting, rest switch Guan Jun ends; Or at least one the switching tube conducting in switch transistor T B2, switch transistor T B1 and the switch transistor T 1, and switch transistor T B3 conducting, rest switch Guan Jun ends;

The 9th operation mode: switch transistor T 2 conductings, rest switch Guan Jun end; Perhaps at least one switching tube conducting among switch transistor T A1, switch transistor T A2 and the switch transistor T A3, and switch transistor T 2 conductings, rest switch Guan Jun ends;

The tenth operation mode: switch transistor T 1 conducting, rest switch Guan Jun end; Perhaps at least one switching tube conducting among switch transistor T B1, switch transistor T B2 and the switch transistor T B3, and switch transistor T 1 conducting, rest switch Guan Jun ends.

4. an electrical level inverter is characterized in that, comprise one as power 1 or weigh 2 or weigh 3 described topology unit, wherein:

5. an electrical level inverter is characterized in that, comprises two as power 1 or weighs 2 or weigh 3 described topology unit: first topology unit and second topology unit, wherein:

6. seven electrical level inverters according to claim 5 is characterized in that, also comprise first inductance, second inductance and electric capacity;

First ac output end of said first topology unit links to each other with first ac output end of said second topology unit through first inductance, electric capacity and second inductance of series connection successively;

The connecting line of first inductance and electric capacity links to each other with first ac output end of this inverter, and the connecting line of second inductance and electric capacity links to each other with second ac output end of this inverter.

7. an electrical level inverter is characterized in that, comprises three as power 1 or weighs 2 or weigh 3 described topology unit: first topology unit, second topology unit and the 3rd topology unit;

8. seven electrical level inverters according to claim 7 is characterized in that, also comprise first inductance, second inductance, the 3rd inductance, first electric capacity, second electric capacity and the 3rd electric capacity;

First ac output end of first topology unit links to each other with first ac output end of second topology unit through first inductance, first electric capacity, second electric capacity and second inductance of series connection successively;

First ac output end of the 3rd topology unit links to each other with the connecting line of first electric capacity with second electric capacity with the 3rd electric capacity through the 3rd inductance of series connection successively;

The connecting line of first inductance and first electric capacity links to each other with first ac output end of this inverter; The connecting line of second inductance and second electric capacity links to each other with second ac output end of this inverter, and the connecting line of the 3rd inductance and the 3rd electric capacity links to each other with the 3rd ac output end of this inverter.

9. an electrical level inverter is characterized in that, comprises four as power 1 or weighs 2 or weigh 3 described topology unit: first topology unit, second topology unit, the 3rd topology unit and the 4th topology unit;

10. seven electrical level inverters according to claim 9 is characterized in that, also comprise first inductance, second inductance, the 3rd inductance, first electric capacity, second electric capacity and the 3rd electric capacity;

First ac output end of second topology unit links to each other with first ac output end of the 3rd topology unit through first inductance, first electric capacity, second electric capacity and second inductance of series connection successively;

First ac output end of the 4th topology unit links to each other with the connecting line of first electric capacity with second electric capacity with the 3rd electric capacity through the 3rd inductance of series connection successively;

First ac output end of first topology unit links to each other with the connecting line of first electric capacity with second electric capacity;