CN102761286B - Four-level inverter topological unit and four-level inverter - Google Patents
Four-level inverter topological unit and four-level inverter Download PDFInfo
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- CN102761286B CN102761286B CN201210255932.1A CN201210255932A CN102761286B CN 102761286 B CN102761286 B CN 102761286B CN 201210255932 A CN201210255932 A CN 201210255932A CN 102761286 B CN102761286 B CN 102761286B
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Abstract
The invention provides a four-level inverter topological unit. The four-level inverter topological unit comprises four switching tubes of diodes in reverse parallel connection and two diodes; and relative to the technical problems that a large number of semiconductor devices are arranged in the conventional four-level inverter, the cost for the inverter and reference circuits thereof is increased, and the packaging difficulty of the inverter and application circuits thereof is increased as a large number of semiconductor devices are arranged in the four-level inverter, the four-level inverter topological unit provided by the invention reduces the number of the semiconductor devices in the entire inverter while realizing single-phase and multi-phase applications and ensuring that direct current is inverted into alternating current, the size is small, the cost is low, and the packaging difficulty of the application circuits of the four-level inverter topological unit is reduced at the same time.
Description
Technical field
The application relates to electric and electronic technical field, particularly a kind of four level inverse conversion topology unit and four electrical level inverters.
Background technology
Inverter is direct current to be changed into the equipment of alternating current.Along with development and the progress of technology, the improving constantly of people's living standard, inverter also becomes a kind of visual plant that people are emergent and go out.Current inverter mostly is diode clamp type inverter or striding capacitance type inverter.
Fig. 1 and Fig. 2 show respectively the part-structure of traditional four electrical level inverters.Wherein, Fig. 1 is the part-structure of diode clamp type four electrical level inverters, and Fig. 2 is the part-structure of striding capacitance type four electrical level inverters.In inverter structure shown in Fig. 1, by capacitor C 1, C2 and C3, produce the signal of telecommunication of four different potentials, and each four level topology unit comprises six switching tubes and ten diodes; In inverter structure shown in Fig. 2, each four level topology unit comprises six switching tubes and six diodes, and in inverter, by capacitor C 1, C2, C3, C4, C5 and C6 are set, produces the signal of telecommunication of four different potentials.
From the above, in traditional diode clamp type four electrical level inverters and striding capacitance type four electrical level inverters, semiconductor device quantity is more, strengthen thus the cost of inverter and application circuit thereof, meanwhile, increased the encapsulation difficulty of inverter and application circuit thereof.
Summary of the invention
The application's technical problem to be solved is to provide a kind of four level inverse conversion topology unit and four electrical level inverters, more in order to solve in existing four electrical level inverters semiconductor device quantity, strengthen thus inverter and quoted the technical problem of the cost of circuit, avoided causing because semiconductor device quantity in four electrical level inverters is more increasing the technical problem of the encapsulation difficulty of inverter and application circuit thereof simultaneously.
The application provides a kind of four level inverse conversion topology unit, comprises switch transistor T 1, switch transistor T 2, switch transistor T 3, switch transistor T 4, diode DF1 and diode DF2;
Diode of each switching tube reverse parallel connection;
The first direct-flow input end M1 of this topology unit is connected with the second direct-flow input end M2 of this topology unit by diode DF1, switch transistor T 2, switch transistor T 3 and the diode DF2 connecting successively;
The 3rd direct-flow input end M3 of this topology unit is connected with the connecting line of switch transistor T 2 with diode DF1 by switch transistor T 1;
The connecting line of switch transistor T 3 and diode DF2 is connected with the 4th direct-flow input end M4 of this topology unit by switch transistor T 4;
The connecting line of switch transistor T 2 and switch transistor T 3 is connected with the ac output end AC of this topology unit.
Above-mentioned four level inverse conversion topology unit, preferably, six operational modules corresponding to this four level inverse conversions topology unit are respectively:
The first operation mode: switch transistor T 2 conductings, rest switch pipe all ends;
The second operation mode: switch transistor T 1 and switch transistor T 2 conductings, rest switch pipe all ends;
The 3rd operation mode: switch transistor T 2 conductings, or switch transistor T 1 and switch transistor T 2 conductings, rest switch pipe all ends;
The 4th operation mode: switch transistor T 3 conductings, rest switch pipe all ends;
The 5th operation mode: switch transistor T 3 and switch transistor T 4 conductings, rest switch pipe all ends;
The 6th operation mode: switch transistor T 3 conductings, or switch transistor T 3 and switch transistor T 4 conductings, rest switch pipe all ends.
The application also provides a kind of four electrical level inverters, comprises that continuous input cell and one are as above-mentioned topology unit as described in any one, wherein:
The first direct current positive level PV1+ of described continuous input cell is connected with the first direct-flow input end M1 of this inversion unit, the second direct current positive level PV2+ of described continuous input cell is connected with the 3rd direct-flow input end M3 of this inversion unit, the first direct current negative level PV1-of described continuous input cell is connected with the second direct-flow input end M2 of this inversion unit, and the second direct current negative level PV2-of described continuous input cell is connected with the 4th direct-flow input end M4 of this inversion unit;
The ac output end AC of this inversion unit is connected with the ac output end of this inverter.
The application also provides a kind of four electrical level inverters, comprises that continuous input cell and two are as above-mentioned topology unit as described in any one: the first topology unit and the second topology unit;
The first direct current positive level PV1+ of continuous input cell is connected with each first direct-flow input end M1 of the first topology unit and the second topology unit;
The first direct current negative level PV1-of continuous input cell is connected with each second direct-flow input end M2 of the first topology unit and the second topology unit;
The second direct current positive level PV2+ of continuous input cell is connected with each the 3rd direct-flow input end M3 of the first topology unit and the second topology unit;
The second direct current negative level PV2-of continuous input cell is connected with each the 4th direct-flow input end M4 of the first topology unit and the second topology unit;
The ac output end AC of the first topology unit is connected with the first ac output end of this inverter, and the ac output end AC of the second topology unit is connected with the second ac output end of this inverter.
The application also provides a kind of four electrical level inverters, comprises that continuous input cell and three are as above-mentioned topology unit as described in any one: the first topology unit, the second topology unit and the 3rd topology unit;
The first direct current positive level PV1+ of continuous input cell and the first topology unit are connected with each first direct-flow input end M1 of, the second topology unit and the 3rd topology unit;
The first direct current negative level PV1-of continuous input cell is connected with each second direct-flow input end M2 of the first topology unit, the second topology unit and the 3rd topology unit;
The second direct current positive level PV2+ of continuous input cell is connected with each the 3rd direct-flow input end M3 of the first topology unit, the second topology unit and the 3rd topology unit;
The second direct current negative level PV2-of continuous input cell is connected with each the 4th direct-flow input end M4 of the first topology unit, the second topology unit and the 3rd topology unit;
The ac output end AC of the first topology unit is connected with the first ac output end of this inverter, the ac output end AC of the second topology unit is connected with the second ac output end of this inverter, and the ac output end AC of the 3rd topology unit is connected with the 3rd ac output end of this inverter.
The application also provides a kind of four electrical level inverters, comprises that continuous input cell and four are as above-mentioned topology unit as described in any one: the first topology unit, the second topology unit, the 3rd topology unit and the 4th topology unit;
The first direct current positive level PV1+ of continuous input cell and the first topology unit are connected with each first direct-flow input end M1 of, the second topology unit, the 3rd topology unit and the 4th topology unit;
The first direct current negative level PV1-of continuous input cell is connected with each second direct-flow input end M2 of the first topology unit, the second topology unit, the 3rd topology unit and the 4th topology unit;
The second direct current positive level PV2+ of continuous input cell is connected with each the 3rd direct-flow input end M3 of the first topology unit, the second topology unit, the 3rd topology unit and the 4th topology unit;
The second direct current negative level PV2-of continuous input cell is connected with each the 4th direct-flow input end M4 of the first topology unit, the second topology unit, the 3rd topology unit and the 4th topology unit;
The ac output end AC of the first topology unit is connected with the first ac output end of this inverter, the ac output end AC of the second topology unit is connected with the second ac output end of this inverter, the ac output end AC of the 3rd topology unit is connected with the 3rd ac output end of this inverter, and the ac output end AC of the 4th topology unit is connected with the 4th ac output end of this inverter.
Above-mentioned four electrical level inverters described in any one, preferably, described continuous input cell comprises capacitor C A1, capacitor C A2, capacitor C A3, inductance L 1, inductance L 2, switch transistor T B1, switch transistor T B2, diode DB1 and diode DB2, wherein:
The anode of DC power supply is connected with the first end of capacitor C A1, and the negative terminal of DC power supply is connected with the second end of capacitor C A1;
The first end of capacitor C A1 is connected with the second end of capacitor C A1 and the connecting line of DC power supply with switch transistor T B1 by the inductance L 1 of connecting successively with the connecting line of DC power supply;
The first end of capacitor C A1 is connected with the second end of capacitor C A1 and the connecting line of DC power supply with inductance L 2 by the switch transistor T B2 connecting successively with the connecting line of DC power supply;
The connecting line of inductance L 1 and switch transistor T B1 is connected with the second end of capacitor C A1 and the connecting line of DC power supply with capacitor C A2 by the diode DB1 connecting successively;
The first end of capacitor C A1 is connected with the connecting line of inductance L 2 with switch transistor T B2 with diode DB2 by the capacitor C A3 connecting successively with the connecting line of DC power supply;
The connecting line of diode DB1 and capacitor C A2 is connected with the second direct current positive level PV2+ of this continuous input cell, the first end of capacitor C A1 is connected with the first direct current positive level PV1+ of this continuous input cell with the connecting line of DC power supply, the second end of capacitor C A1 and the connecting line of DC power supply are connected with the first direct current negative level PV1-of this continuous input cell, and the connecting line of capacitor C A3 and diode DB2 is connected with the second direct current negative level PV2-of this continuous input cell.
Above-mentioned four electrical level inverters described in any one, preferably, described continuous input cell comprises capacitor C A1, capacitor C A2, capacitor C A3, inductance L 1, inductance L 2, switch transistor T B1, switch transistor T B2, diode DB1 and diode DB2, wherein:
The anode of DC power supply is connected with the first end of capacitor C A1, and the negative terminal of DC power supply is connected with the second end of capacitor C A1;
The first end of capacitor C A1 is connected with the second end of capacitor C A1 and the connecting line of DC power supply with switch transistor T B1 by the inductance L 1 of connecting successively with the connecting line of DC power supply;
The first end of capacitor C A1 is connected with the second end of capacitor C A1 and the connecting line of DC power supply with inductance L 2 by the switch transistor T B2 connecting successively with the connecting line of DC power supply;
The connecting line of inductance L 1 and switch transistor T B1 is connected with the first end of capacitor C A1 and the connecting line of DC power supply with capacitor C A2 by the diode DB1 connecting successively;
The second end of capacitor C A1 and the connecting line of DC power supply are connected with the connecting line of inductance L 2 with switch transistor T B2 with diode DB2 by the capacitor C A3 connecting successively;
The connecting line of diode DB1 and capacitor C A2 is connected with the second direct current positive level PV2+ of this continuous input cell, the first end of capacitor C A1 is connected with the first direct current positive level PV1+ of this continuous input cell with the connecting line of DC power supply, the second end of capacitor C A1 and the connecting line of DC power supply are connected with the first direct current negative level PV1-of this continuous input cell, and the connecting line of capacitor C A3 and diode DB2 is connected with the second direct current negative level PV2-of this continuous input cell.
Above-mentioned four electrical level inverters described in any one, preferably, described continuous input cell comprises capacitor C B1, capacitor C B2, capacitor C A2, capacitor C A3, inductance L 1, inductance L 2, switch transistor T B1, switch transistor T B2, diode DB1 and diode DB2, wherein:
The anode of DC power supply is connected with the negative terminal of DC power supply with capacitor C B2 by the capacitor C B1 connecting successively;
The connecting line of capacitor C B1 and DC power supply is connected with the connecting line of capacitor C B2 and DC power supply by inductance L 1, switch transistor T B1, switch transistor T B2 and the inductance L 2 of connecting successively;
The connecting line of capacitor C B1 and capacitor C B2 is connected with the connecting line of switch transistor T B2 with switch transistor T B1;
The connecting line of inductance L 1 and switch transistor T B1 is connected with the connecting line of capacitor C B1 and DC power supply with capacitor C A2 by the diode DB1 connecting successively;
The connecting line of capacitor C B2 and DC power supply is connected with the connecting line of inductance L 2 with switch transistor T B2 with diode DB2 by the capacitor C A3 connecting successively;
The connecting line of diode DB1 and capacitor C A2 is connected with the second direct current positive level PV2+ of this continuous input cell, the connecting line of capacitor C B1 and DC power supply is connected with the first direct current positive level PV1+ of this continuous input cell, the connecting line of capacitor C B2 and DC power supply is connected with the first direct current negative level PV1-of this continuous input cell, and the connecting line of capacitor C A3 and diode DB2 is connected with the second direct current negative level PV2-of this continuous input cell.
From the above, the four level inverse conversion topology unit that the application provides comprise switching tube and two diodes of four reverse parallel connection diodes, more with respect to semiconductor device quantity in existing four electrical level inverters, strengthen thus inverter and quoted the cost of circuit, and because semiconductor device quantity in four electrical level inverters is more, cause increasing the technical problem of the encapsulation difficulty of inverter and application circuit thereof, the four level inverse conversion topology unit that the application provides are when realizing single-phase and heterogeneous application, guaranteeing DC inversion as when exchanging, reduced the quantity of the semiconductor components and devices of whole inverter, small volume, cost is lower, simultaneously, reduced the encapsulation difficulty of its application circuit.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme in the embodiment of the present application, below the accompanying drawing of required use during embodiment is described is briefly described, apparently, accompanying drawing in the following describes is only some embodiment of the application, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the topological diagram of diode clamp type four electrical level inverters of the prior art;
Fig. 2 is the topological diagram of striding capacitance type four electrical level inverters of the prior art;
The topological diagram of a kind of four level inverse conversion topology unit embodiment mono-that Fig. 3 provides for the application;
The topological diagram of a kind of four level inverse conversion topology unit embodiment mono-in the first operation mode that Fig. 4 provides for the application;
The topological diagram of a kind of four level inverse conversion topology unit embodiment mono-in the second operation mode that Fig. 5 provides for the application;
The topological diagram of a kind of four level inverse conversion topology unit embodiment mono-in the 3rd operation mode that Fig. 6 provides for the application;
The topological diagram of a kind of four level inverse conversion topology unit embodiment mono-in the 4th operation mode that Fig. 7 provides for the application;
The topological diagram of a kind of four level inverse conversion topology unit embodiment mono-in the 5th operation mode that Fig. 8 provides for the application;
The topological diagram of a kind of four level inverse conversion topology unit embodiment mono-in the 6th operation mode that Fig. 9 provides for the application;
In a kind of four level inverse conversion topology unit embodiment mono-that Figure 10 provides for the application, sequential generates sinusoidal wave a kind of sequential modulation figure;
In a kind of four level inverse conversion topology unit embodiment mono-that Figure 11 provides for the application, sequential generates sinusoidal wave another kind of sequential modulation figure;
The topological diagram of a kind of four electrical level inverter embodiment bis-that Figure 12 provides for the application;
Another topological diagram of a kind of four electrical level inverter embodiment bis-that Figure 13 provides for the application;
Another topological diagram of a kind of four electrical level inverter embodiment bis-that Figure 14 provides for the application;
Another topological diagram of a kind of four electrical level inverter embodiment bis-that Figure 15 provides for the application;
The isoboles of a kind of four level inverse conversion topology unit embodiment mono-that Figure 16 provides for the application;
The topological diagram of a kind of four electrical level inverter embodiment tri-that Figure 17 provides for the application;
Another topological diagram of a kind of four electrical level inverter embodiment tri-that Figure 18 provides for the application;
Another topological diagram of a kind of four electrical level inverter embodiment tri-that Figure 19 provides for the application;
Another topological diagram of a kind of four electrical level inverter embodiment tri-that Figure 20 provides for the application;
Another topological diagram of a kind of four electrical level inverter embodiment tri-that Figure 21 provides for the application;
The topological diagram of a kind of four electrical level inverter embodiment tetra-that Figure 22 provides for the application;
Another topological diagram of a kind of four electrical level inverter embodiment tetra-that Figure 23 provides for the application;
Another topological diagram of a kind of four electrical level inverter embodiment tetra-that Figure 24 provides for the application;
Another topological diagram of a kind of four electrical level inverter embodiment tetra-that Figure 25 provides for the application;
Another topological diagram of a kind of four electrical level inverter embodiment tetra-that Figure 26 provides for the application.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present application, the technical scheme in the embodiment of the present application is clearly and completely described, obviously, described embodiment is only the application's part embodiment, rather than whole embodiment.Embodiment based in the application, those of ordinary skills are not making the every other embodiment obtaining under creative work prerequisite, all belong to the scope of the application's protection.
With reference to figure 3, it shows the topological diagram of a kind of four level inverse conversion topology unit embodiment mono-that the application provides, and described four level inverse conversion topology unit comprise switch transistor T 1, switch transistor T 2, switch transistor T 3, switch transistor T 4, diode DF1 and diode DF2;
Diode of each switching tube reverse parallel connection;
The first direct-flow input end M1 of this topology unit is connected with the second direct-flow input end M2 of this topology unit by diode DF1, switch transistor T 2, switch transistor T 3 and the diode DF2 connecting successively;
The 3rd direct-flow input end M3 of this topology unit is connected with the connecting line of switch transistor T 2 with diode DF1 by switch transistor T 1;
The connecting line of switch transistor T 3 and diode DF2 is connected with the 4th direct-flow input end M4 of this topology unit by switch transistor T 4;
The connecting line of switch transistor T 2 and switch transistor T 3 is connected with the ac output end AC of this topology unit.
Wherein, the switching tube of above topology unit can be managed for IGBT, MOSFET manages, IGCT manages or IEGT pipe.Be understandable that, above switching tube also can be selected the switching tube of other types.
From such scheme, the four level inverse conversion topology unit that Benshen please provide comprise switching tube and two diodes of four reverse parallel connection diodes, more with respect to semiconductor device quantity in existing four electrical level inverters, strengthen thus inverter and quoted the cost of circuit, and because semiconductor device quantity in four electrical level inverters is more, cause increasing the technical problem of the encapsulation difficulty of inverter and application circuit thereof, the four level inverse conversion topology unit that the application provides are guaranteeing DC inversion as when exchanging, reduced the quantity of the semiconductor components and devices of whole inverter, small volume, cost is lower, simultaneously, reduced the encapsulation difficulty of its application circuit.
Wherein, the four level inverse conversion topology unit embodiment mono-that the application provides, when realizing the conversion of direct current and alternating current, comprise six operation modes, below in conjunction with accompanying drawing, six of the five-electrical level inverter shown in Fig. 3 kinds of operation modes are carried out to labor.
Wherein, diode D1 and switch transistor T 1 reverse parallel connection, diode D2 and switch transistor T 2 reverse parallel connections, diode D3 and switch transistor T 3 reverse parallel connections, diode D4 and switch transistor T 4 reverse parallel connections.
With reference to figure 4, it shows the topological diagram of the first operation mode of the four level inverse conversion topology unit embodiment mono-that the application provides.
The first operation mode: switch transistor T 2 conductings, rest switch pipe all ends;
Wherein, the path of not conducting illustrates with fine line in the drawings, and the path of conducting illustrates with heavy line.
The path of electric current is: M1-DF1-T2-AC.
With reference to figure 5, it shows the topological diagram of the second operation mode of the four level inverse conversion topology unit embodiment mono-that the application provides.
The second operation mode: switch transistor T 1 and switch transistor T 2 conductings simultaneously, rest switch pipe all ends;
Wherein, the path of not conducting illustrates with fine line in the drawings, and the path of conducting illustrates with heavy line.
Current path is: M3-T1-T2-AC.
With reference to figure 6, it shows the topological diagram of the 3rd operation mode of the four level inverse conversion topology unit embodiment mono-that the application provides.
The 3rd operation mode: switch transistor T 2 conductings, or switch transistor T 1 and switch transistor T 2 conductings simultaneously, rest switch pipe all ends;
Wherein, the path of not conducting illustrates with fine line in the drawings, and the path of conducting illustrates with heavy line.
Current path is: AC-D2-D1-M3.
With reference to figure 7, it shows the topological diagram of the 4th operation mode of the four level inverse conversion topology unit embodiment mono-that the application provides.
The 4th operation mode: switch transistor T 3 conductings, rest switch pipe all ends;
Wherein, the path of not conducting illustrates with fine line in the drawings, and the path of conducting illustrates with heavy line.
Current path is: AC-T3-DF2-M2.
With reference to figure 8, it shows the topological diagram of the 5th operation mode of the four level inverse conversion topology unit embodiment mono-that the application provides.
The 5th operation mode: switch transistor T 3 and switch transistor T 4 conductings, rest switch pipe all ends;
Wherein, the path of not conducting illustrates with fine line in the drawings, and the path of conducting illustrates with heavy line.
Current path is: AC-T3-T4-M4.
With reference to figure 9, it shows the topological diagram of the 6th operation mode of the four level inverse conversion topology unit embodiment mono-that the application provides.
The 6th operation mode: switch transistor T 3 conductings, or switch transistor T 3 and switch transistor T 4 conductings simultaneously, rest switch pipe all ends;
Wherein, the path of not conducting illustrates with fine line in the drawings, and the path of conducting illustrates with heavy line.
Current path is: M4-D4-D3-AC.
By the sequential of the operation mode shown in above-mentioned Fig. 4, Fig. 5, Fig. 7, Fig. 8 is controlled, just can obtain the sinusoidal ac of needs, Figure 10, Figure 11 are sequencing control figure, wherein, u is the voltage waveform of inverter output.
For example: four direct-flow input end M1, M2 of supposition above topology unit, the input voltage of M3, M4 are respectively :+V1 ,-V1 ,+V2 ,-V2, the first operation mode can obtain voltage V1, the second operation mode obtains voltage V2, the 4th operation mode obtains voltage-V1, the 5th operation mode obtains voltage-V2, and establishing the minimal reverse time variant voltage that meets inversion requirement is Vm.
When V1<Vm<V2, by the sequential shown in Figure 10, control, i.e. the t0 moment～t1 moment, t
2constantly～t
4the moment and t
5constantly～t
6constantly, the first operation mode and the 4th operation mode alternation, the t1 moment～t
2constantly, the first operation mode and the second operation mode alternation, t
4constantly～t
5constantly, the 4th operation mode and the 5th operation mode alternation;
When Vm<V1<V2, by the sequential shown in Figure 11, to control, concrete sequencing control is referring to Figure 11, then this is not repeating.
From the above, the four level inverse conversion topology unit embodiment mono-that the application provides adopt the thinking of four Level Technology matching sine waves, and with respect to prior art, common-mode voltage is little, and ripple loss is lower, and conversion efficiency is higher.
With reference to Figure 12, it shows the topological diagram of a kind of four electrical level inverter embodiment bis-that the application provides, and described four electrical level inverter embodiment bis-comprise continuous input cell 1201 and a topology unit as described in embodiment mono-, wherein:
The first direct current positive level PV1+ of described continuous input cell 1201 is connected with the first direct-flow input end M1 of this inversion unit, the second direct current positive level PV2+ of described continuous input cell 1201 is connected with the 3rd direct-flow input end M3 of this inversion unit, the first direct current negative level PV1-of described continuous input cell 1201 is connected with the second direct-flow input end M2 of this inversion unit, and the second direct current negative level PV2-of described continuous input cell 1201 is connected with the 4th direct-flow input end M4 of this inversion unit;
The ac output end AC of this inversion unit is connected with the ac output end of this inverter.
Wherein, the implementation of described continuous input cell 1201 has multiple:
Preferably, with reference to Figure 13, it shows another topological diagram of a kind of four electrical level inverter embodiment bis-that the application provides, wherein, described continuous input cell 1201 comprises capacitor C A1, capacitor C A2, capacitor C A3, inductance L 1, inductance L 2, switch transistor T B1, switch transistor T B2, diode DB1 and diode DB2, wherein:
The anode of DC power supply PV is connected with the first end of capacitor C A1, and the negative terminal of DC power supply PV is connected with the second end of capacitor C A1;
The connecting line of the first end of capacitor C A1 and DC power supply PV is connected with the connecting line of DC power supply PV with the second end of capacitor C A1 with switch transistor T B1 by the inductance L 1 of connecting successively;
The connecting line of the first end of capacitor C A1 and DC power supply PV is connected with the connecting line of DC power supply PV with the second end of capacitor C A1 with inductance L 2 by the switch transistor T B2 connecting successively;
The connecting line of inductance L 1 and switch transistor T B1 is connected with the connecting line of DC power supply PV with the second end of capacitor C A1 with capacitor C A2 by the diode DB1 connecting successively;
The connecting line of the first end of capacitor C A1 and DC power supply PV is connected with the connecting line of inductance L 2 with switch transistor T B2 with diode DB2 by the capacitor C A3 connecting successively;
The connecting line of diode DB 1 and capacitor C A2 is connected with the second direct current positive level PV2+ of this continuous input cell, the connecting line of the first end of capacitor C A1 and DC power supply PV is connected with the first direct current positive level PV1+ of this continuous input cell, the second end of capacitor C A1 is connected with the first direct current negative level PV1-of this continuous input cell with the connecting line of DC power supply PV, and the connecting line of capacitor C A3 and diode DB2 is connected with the second direct current negative level PV2-of this continuous input cell.
Preferably, with reference to Figure 14, it shows another topological diagram of a kind of four electrical level inverter embodiment bis-that the application provides, wherein, described continuous input cell 1201 comprises capacitor C A1, capacitor C A2, capacitor C A3, inductance L 1, inductance L 2, switch transistor T B1, switch transistor T B2, diode DB1 and diode DB2, wherein:
The anode of DC power supply PV is connected with the first end of capacitor C A1, and the negative terminal of DC power supply PV is connected with the second end of capacitor C A1;
The connecting line of the first end of capacitor C A1 and DC power supply PV is connected with the connecting line of DC power supply PV with the second end of capacitor C A1 with switch transistor T B 1 by the inductance L 1 of connecting successively;
The connecting line of the first end of capacitor C A1 and DC power supply PV is connected with the connecting line of DC power supply PV with the second end of capacitor C A1 with inductance L 2 by the switch transistor T B2 connecting successively;
The connecting line of inductance L 1 and switch transistor T B 1 is connected with the connecting line of DC power supply PV with the first end of capacitor C A1 with capacitor C A2 by the diode DB1 connecting successively;
The second end of capacitor C A1 is connected with the connecting line of inductance L 2 with switch transistor T B2 with diode DB2 by the capacitor C A3 connecting successively with the connecting line of DC power supply PV;
The connecting line of diode DB1 and capacitor C A2 is connected with the second direct current positive level PV2+ of this continuous input cell, the connecting line of the first end of capacitor C A1 and DC power supply PV is connected with the first direct current positive level PV1+ of this continuous input cell, the second end of capacitor C A1 is connected with the first direct current negative level PV1-of this continuous input cell with the connecting line of DC power supply PV, and the connecting line of capacitor C A3 and diode DB2 is connected with the second direct current negative level PV2-of this continuous input cell.
Preferably, with reference to Figure 15, it shows another topological diagram of a kind of four electrical level inverter embodiment bis-that the application provides, wherein, described continuous input cell 1201 comprises capacitor C B1, capacitor C B2, capacitor C A2, capacitor C A3, inductance L 1, inductance L 2, switch transistor T B1, switch transistor T B2, diode DB1 and diode DB2, wherein:
The anode of DC power supply PV is connected with the negative terminal of DC power supply PV with capacitor C B2 by the capacitor C B1 connecting successively;
The connecting line of capacitor C B1 and DC power supply PV is connected with the connecting line of DC power supply PV with capacitor C B2 by inductance L 1, switch transistor T B1, switch transistor T B2 and the inductance L 2 of connecting successively;
The connecting line of capacitor C B1 and capacitor C B2 is connected with the connecting line of switch transistor T B2 with switch transistor T B1;
The connecting line of inductance L 1 and switch transistor T B1 is connected with the connecting line of DC power supply PV with capacitor C B1 with capacitor C A2 by the diode DB1 connecting successively;
The connecting line of capacitor C B1 and DC power supply PV is connected with the connecting line of inductance L 2 with switch transistor T B2 with diode DB2 by the capacitor C A3 connecting successively;
The connecting line of diode DB1 and capacitor C A2 is connected with the second direct current positive level PV2+ of this continuous input cell, the connecting line of capacitor C B1 and DC power supply PV is connected with the first direct current positive level PV1+ of this continuous input cell, the connecting line of capacitor C B2 and DC power supply PV is connected with the first direct current negative level PV1-of this continuous input cell, and the connecting line of capacitor C A3 and diode DB2 is connected with the second direct current negative level PV2-of this continuous input cell.
From such scheme, more with respect to semiconductor device quantity in existing four electrical level inverters, strengthen thus inverter and quoted the cost of circuit, and because semiconductor device quantity in four electrical level inverters is more, cause increasing the technical problem of the encapsulation difficulty of inverter and application circuit thereof, the four electrical level inverter embodiment bis-that the application provides, being the embodiment of the present application one is realizing when single-phase, guaranteeing DC inversion as when exchanging, reduced the quantity of the semiconductor components and devices of whole inverter, small volume, cost is lower.
It should be noted that, the operation mode of the four level inverse conversion topology unit embodiment mono-that above-mentioned the application provides is described the operation mode that is applicable to the four electrical level inverter embodiment bis-that the application provides, by adopting the sinusoidal wave thinking of four Level Technology matchings, with respect to prior art, common-mode voltage is little, ripple loss is lower, and conversion efficiency is higher.
With reference to Figure 16, it shows the isoboles of the four level inverse conversion topology unit embodiment mono-that the application provides.
With reference to Figure 17, it shows the topological diagram of a kind of four electrical level inverter embodiment tri-that the application provides, for single-phase full bridge four electrical level inverters, described four electrical level inverters comprise continuous input cell 1701 and two topology unit as shown in figure 16: the first topology unit and the second topology unit;
1,701 first direct current positive level PV1+ of continuous input cell are connected with each first direct-flow input end M1 of the first topology unit ` and the second topology unit;
The first direct current negative level PV1-of continuous input cell 1701 is connected with each second direct-flow input end M2 of the first topology unit and the second topology unit;
The second direct current positive level PV2+ of continuous input cell 1701 is connected with each the 3rd direct-flow input end M3 of the first topology unit and the second topology unit;
The second direct current negative level PV2-of continuous input cell 1701 is connected with each the 4th direct-flow input end M4 of the first topology unit and the second topology unit;
The ac output end AC of the first topology unit is connected with the first ac output end O1 of this inverter, and the ac output end AC of the second topology unit is connected with the second ac output end O2 of this inverter.
It should be noted that, for reducing the harmonic content of the alternating current of the embodiment of the present application three outputs, can increase filter unit at inverter as shown in figure 17, by inductance and electric capacity are set, realize the filtering of alternating current.With reference to Figure 18, it shows another topological diagram of a kind of four electrical level inverter embodiment tri-that the application provides, and wherein, described four electrical level inverters also comprise inductance L 1801, capacitor C 1801 and inductance L 1802, wherein:
The ac output end AC of the first topology unit is connected with the ac output end AC of the second topology unit by inductance L 1801, capacitor C 1801 and the inductance L 1802 of connecting successively;
The connecting line of inductance L 1801 and capacitor C 1801 is connected with the first ac output end O1 of this inverter, and the connecting line of capacitor C 1801 and inductance L 1802 is connected with the second ac output end O2 of this inverter.
Wherein, described continuous input cell 1701 is by multiple implementation:
With reference to Figure 19, it shows another topological diagram of a kind of four electrical level inverter embodiment tri-that the application provides, wherein, the composition of described continuous input cell 1701, with consistent described in continuous input cell 1201 described in syndeton and the embodiment of the present application two as shown in figure 13, is no longer set forth at this;
With reference to Figure 20, it shows another topological diagram of a kind of four electrical level inverter embodiment tri-that the application provides, wherein, the composition of described continuous input cell 1701, with consistent described in continuous input cell 1201 described in syndeton and the embodiment of the present application two as shown in figure 14, is no longer set forth at this;
With reference to Figure 21, it shows another topological diagram of a kind of four electrical level inverter embodiment tri-that the application provides, wherein, the composition of described continuous input cell 1701, with consistent described in continuous input cell 1201 described in syndeton and the embodiment of the present application two as shown in figure 15, is no longer set forth at this.
It should be noted that, the above-mentioned filter unit being comprised of a plurality of inductance and electric capacity is as shown in figure 18 equally applicable to four electrical level inverters as shown in Figure 19, Figure 20, Figure 21, at this, is not described in detail.
From such scheme, more with respect to semiconductor device quantity in existing four electrical level inverters, strengthen thus inverter and quoted the cost of circuit, and because semiconductor device quantity in four electrical level inverters is more, cause increasing the technical problem of the encapsulation difficulty of inverter and application circuit thereof, the four electrical level inverter embodiment tri-that the application provides, be that the embodiment of the present application one is when realizing two-phase application, guaranteeing DC inversion as when exchanging, reduced the quantity of the semiconductor components and devices of whole inverter, small volume, cost is lower.
It should be noted that, the operation mode of the four level inverse conversion topology unit embodiment mono-that above-mentioned the application provides is described the operation mode that is applicable to the four electrical level inverter embodiment tri-that the application provides, by adopting the sinusoidal wave thinking of four Level Technology matchings, with respect to prior art, common-mode voltage is little, ripple loss is lower, and conversion efficiency is higher.
With reference to Figure 22, it shows the topological diagram of a kind of four electrical level inverter embodiment tetra-that the application provides, and described four electrical level inverters comprise continuous input cell 2201 and three topology unit as described in Figure 16: the first topology unit, the second topology unit and the 3rd topology unit;
The first direct current positive level PV1+ of continuous input cell 2201 and the first topology unit are connected with each first direct-flow input end M1 of, the second topology unit and the 3rd topology unit;
The first direct current negative level PV1-of continuous input cell 2201 is connected with each second direct-flow input end M2 of the first topology unit, the second topology unit and the 3rd topology unit;
The second direct current positive level PV2+ of continuous input cell 2201 is connected with each the 3rd direct-flow input end M3 of the first topology unit, the second topology unit and the 3rd topology unit;
The second direct current negative level PV2-of continuous input cell 2201 is connected with each the 4th direct-flow input end M4 of the first topology unit, the second topology unit and the 3rd topology unit;
The ac output end AC of the first topology unit is connected with the first ac output end O1 of this inverter, the ac output end AC of the second topology unit is connected with the second ac output end O2 of this inverter, and the ac output end AC of the 3rd topology unit is connected with the 3rd ac output end O3 of this inverter.
It should be noted that, for reducing the harmonic content of the alternating current of the embodiment of the present application four outputs, can increase filter unit at inverter as shown in figure 22, by inductance and electric capacity are set, realize the filtering of alternating current.With reference to Figure 23, it shows another topological diagram of a kind of four electrical level inverter embodiment tetra-that the application provides, for phase three-wire three four electrical level inverters, wherein, described four electrical level inverters also comprise inductance L 2301, inductance L 2302, inductance L 2303, capacitor C 2301, capacitor C 2302 and capacitor C 2303, wherein:
The ac output end AC of the first topology unit is connected with the ac output end AC of the second topology unit by inductance L 2301, capacitor C 2301, capacitor C 2302 and the inductance L 2302 of connecting successively;
The ac output end AC of the 3rd topology unit is connected with the connecting line of capacitor C 2302 with capacitor C 2301 with capacitor C 2303 by the inductance L 2303 of connecting successively;
The connecting line of inductance L 2301 and capacitor C 2301 is connected with the first ac output end O1 of this inverter, the connecting line of capacitor C 2302 and inductance L 2302 is connected with the second ac output end O2 of this inverter, and the connecting line of inductance L 2303 and capacitor C 2303 is connected with the 3rd ac output end O3 of this inverter.
Wherein, described continuous input cell 2201 is by multiple implementation:
With reference to Figure 24, it shows another topological diagram of a kind of four electrical level inverter embodiment tetra-that the application provides, wherein, the composition of described continuous input cell 2201, with consistent described in continuous input cell 1201 described in syndeton and the embodiment of the present application two as shown in figure 13, is no longer set forth at this;
With reference to Figure 25, it shows another topological diagram of a kind of four electrical level inverter embodiment tetra-that the application provides, wherein, the composition of described continuous input cell 2201, with consistent described in continuous input cell 1201 described in syndeton and the embodiment of the present application two as shown in figure 14, is no longer set forth at this;
With reference to Figure 26, it shows another topological diagram of a kind of four electrical level inverter embodiment tetra-that the application provides, wherein, the composition of described continuous input cell 2201, with consistent described in continuous input cell 1201 described in syndeton and the embodiment of the present application two as shown in figure 15, is no longer set forth at this.
It should be noted that, the above-mentioned filter unit being comprised of a plurality of inductance and electric capacity is as shown in figure 23 equally applicable to four electrical level inverters as shown in Figure 24, Figure 25, Figure 26, at this, is not described in detail.
Further, in the execution mode shown in Figure 26, the common port of capacitor C 2301, capacitor C 2302 and capacitor C 2303 can also be connected with the common port of capacitor C B2 with capacitor C B1, is three-phase and four-line formula five-electrical level inverter.
From such scheme, more with respect to semiconductor device quantity in existing four electrical level inverters, strengthen thus inverter and quoted the cost of circuit, and because semiconductor device quantity in four electrical level inverters is more, cause increasing the technical problem of the encapsulation difficulty of inverter and application circuit thereof, the four electrical level inverter embodiment tetra-that the application provides, be that the embodiment of the present application one is when realizing three-phase applications, guaranteeing DC inversion as when exchanging, reduced the quantity of the semiconductor components and devices of whole inverter, small volume, cost is lower.
It should be noted that, the operation mode of the four level inverse conversion topology unit embodiment mono-that above-mentioned the application provides is described the operation mode that is applicable to the four electrical level inverter embodiment tetra-that the application provides, by adopting the sinusoidal wave thinking of four Level Technology matchings, with respect to prior art, common-mode voltage is little, ripple loss is lower, and conversion efficiency is higher.
Same, the scheme of the application's four level inverse conversion topology unit, be equally applicable to three-phase and four-line formula inverter, described three-phase and four-line formula inverter comprises continuous input cell and four inversion topological unit as shown in figure 16, its mode of connection is similar with four electrical level inverter embodiment tetra-to above-mentioned four electrical level inverter embodiment bis-, four electrical level inverter embodiment tri-, at this, is not repeating.
It should be noted that, each embodiment in this specification all adopts the mode of going forward one by one to describe, and each embodiment stresses is the difference with other embodiment, between each embodiment identical similar part mutually referring to.
Finally, also it should be noted that, in this article, relational terms such as the first and second grades is only used for an entity or operation to separate with another entity or operating space, and not necessarily requires or imply and between these entities or operation, have the relation of any this reality or sequentially.And, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thereby the process, method, article or the equipment that make to comprise a series of key elements not only comprise those key elements, but also comprise other key elements of clearly not listing, or be also included as the intrinsic key element of this process, method, article or equipment.The in the situation that of more restrictions not, the key element being limited by statement " comprising ... ", and be not precluded within process, method, article or the equipment that comprises described key element and also have other identical element.
A kind of four level inverse conversion topology unit and four electrical level inverters that above the application are provided are described in detail, applied specific case herein the application's principle and execution mode are set forth, the explanation of above embodiment is just for helping to understand the application's method and core concept thereof; Meanwhile, for one of ordinary skill in the art, the thought according to the application, all will change in specific embodiments and applications, and in sum, this description should not be construed as the restriction to the application.
Claims (9)
1. four level inverse conversion topology unit, is characterized in that, comprise switch transistor T 1, switch transistor T 2, switch transistor T 3, switch transistor T 4, diode DF1 and diode DF2;
Diode of each switching tube reverse parallel connection;
The first direct-flow input end M1 of this topology unit is connected with the second direct-flow input end M2 of this topology unit by diode DF1, switch transistor T 2, switch transistor T 3 and the diode DF2 connecting successively;
The 3rd direct-flow input end M3 of this topology unit is connected with the connecting line of switch transistor T 2 with diode DF1 by switch transistor T 1;
The connecting line of switch transistor T 3 and diode DF2 is connected with the 4th direct-flow input end M4 of this topology unit by switch transistor T 4;
The connecting line of switch transistor T 2 and switch transistor T 3 is connected with the ac output end AC of this topology unit.
2. four level inverse conversion topology unit according to claim 1, is characterized in that, six operational modules corresponding to this four level inverse conversions topology unit are respectively:
The first operation mode: switch transistor T 2 conductings, rest switch pipe all ends;
The second operation mode: switch transistor T 1 and switch transistor T 2 conductings, rest switch pipe all ends;
The 3rd operation mode: switch transistor T 2 conductings, or switch transistor T 1 and switch transistor T 2 conductings, rest switch pipe all ends;
The 4th operation mode: switch transistor T 3 conductings, rest switch pipe all ends;
The 5th operation mode: switch transistor T 3 and switch transistor T 4 conductings, rest switch pipe all ends;
The 6th operation mode: switch transistor T 3 conductings, or switch transistor T 3 and switch transistor T 4 conductings, rest switch pipe all ends.
3. four electrical level inverters, is characterized in that, comprise that continuous input cell and one are as claim 1 or topology unit claimed in claim 2, wherein:
The first direct current positive level PV1+ of described continuous input cell is connected with the first direct-flow input end M1 of this topology unit, the second direct current positive level PV2+ of described continuous input cell is connected with the 3rd direct-flow input end M3 of this topology unit, the first direct current negative level PV1-of described continuous input cell is connected with the second direct-flow input end M2 of this topology unit, and the second direct current negative level PV2-of described continuous input cell is connected with the 4th direct-flow input end M4 of this topology unit;
The ac output end AC of this topology unit is connected with the ac output end of this inverter.
4. four electrical level inverters, is characterized in that, comprise that continuous input cell and two are as claim 1 or topology unit claimed in claim 2: the first topology unit and the second topology unit;
The first direct current positive level PV1+ of continuous input cell is connected with each first direct-flow input end M1 of the first topology unit and the second topology unit;
The first direct current negative level PV1-of continuous input cell is connected with each second direct-flow input end M2 of the first topology unit and the second topology unit;
The second direct current positive level PV2+ of continuous input cell is connected with each the 3rd direct-flow input end M3 of the first topology unit and the second topology unit;
The second direct current negative level PV2-of continuous input cell is connected with each the 4th direct-flow input end M4 of the first topology unit and the second topology unit;
The ac output end AC of the first topology unit is connected with the first ac output end of this inverter, and the ac output end AC of the second topology unit is connected with the second ac output end of this inverter.
5. four electrical level inverters, is characterized in that, comprise that continuous input cell and three are as claim 1 or topology unit claimed in claim 2: the first topology unit, the second topology unit and the 3rd topology unit;
The first direct current positive level PV1+ of continuous input cell and the first topology unit are connected with each first direct-flow input end M1 of, the second topology unit and the 3rd topology unit;
The first direct current negative level PV1-of continuous input cell is connected with each second direct-flow input end M2 of the first topology unit, the second topology unit and the 3rd topology unit;
The second direct current positive level PV2+ of continuous input cell is connected with each the 3rd direct-flow input end M3 of the first topology unit, the second topology unit and the 3rd topology unit;
The second direct current negative level PV2-of continuous input cell is connected with each the 4th direct-flow input end M4 of the first topology unit, the second topology unit and the 3rd topology unit;
The ac output end AC of the first topology unit is connected with the first ac output end of this inverter, the ac output end AC of the second topology unit is connected with the second ac output end of this inverter, and the ac output end AC of the 3rd topology unit is connected with the 3rd ac output end of this inverter.
6. four electrical level inverters, is characterized in that, comprise that continuous input cell and four are as claim 1 or topology unit claimed in claim 2: the first topology unit, the second topology unit, the 3rd topology unit and the 4th topology unit;
The first direct current positive level PV1+ of continuous input cell and the first topology unit are connected with each first direct-flow input end M1 of, the second topology unit, the 3rd topology unit and the 4th topology unit;
The first direct current negative level PV1-of continuous input cell is connected with each second direct-flow input end M2 of the first topology unit, the second topology unit, the 3rd topology unit and the 4th topology unit;
The second direct current positive level PV2+ of continuous input cell is connected with each the 3rd direct-flow input end M3 of the first topology unit, the second topology unit, the 3rd topology unit and the 4th topology unit;
The second direct current negative level PV2-of continuous input cell is connected with each the 4th direct-flow input end M4 of the first topology unit, the second topology unit, the 3rd topology unit and the 4th topology unit;
The ac output end AC of the first topology unit is connected with the first ac output end of this inverter, the ac output end AC of the second topology unit is connected with the second ac output end of this inverter, the ac output end AC of the 3rd topology unit is connected with the 3rd ac output end of this inverter, and the ac output end AC of the 4th topology unit is connected with the 4th ac output end of this inverter.
7. according to four electrical level inverters described in claim 3,4,5 and 6 any one, it is characterized in that, described continuous input cell comprises capacitor C A1, capacitor C A2, capacitor C A3, inductance L 1, inductance L 2, switch transistor T B1, switch transistor T B2, diode DB1 and diode DB2, wherein:
The anode of DC power supply is connected with the first end of capacitor C A1, and the negative terminal of DC power supply is connected with the second end of capacitor C A1;
The first end of capacitor C A1 is connected with the second end of capacitor C A1 and the connecting line of DC power supply with switch transistor T B1 by the inductance L 1 of connecting successively with the connecting line of DC power supply;
The first end of capacitor C A1 is connected with the second end of capacitor C A1 and the connecting line of DC power supply with inductance L 2 by the switch transistor T B2 connecting successively with the connecting line of DC power supply;
The connecting line of inductance L 1 and switch transistor T B1 is connected with the second end of capacitor C A1 and the connecting line of DC power supply with capacitor C A2 by the diode DB1 connecting successively;
The first end of capacitor C A1 is connected with the connecting line of inductance L 2 with switch transistor T B2 with diode DB2 by the capacitor C A3 connecting successively with the connecting line of DC power supply;
The connecting line of diode DB1 and capacitor C A2 is connected with the second direct current positive level PV2+ of this continuous input cell, the first end of capacitor C A1 is connected with the first direct current positive level PV1+ of this continuous input cell with the connecting line of DC power supply, the second end of capacitor C A1 and the connecting line of DC power supply are connected with the first direct current negative level PV1-of this continuous input cell, and the connecting line of capacitor C A3 and diode DB2 is connected with the second direct current negative level PV2-of this continuous input cell.
8. according to four electrical level inverters described in claim 3,4,5 and 6 any one, it is characterized in that, described continuous input cell comprises capacitor C A1, capacitor C A2, capacitor C A3, inductance L 1, inductance L 2, switch transistor T B1, switch transistor T B2, diode DB1 and diode DB2, wherein:
The anode of DC power supply is connected with the first end of capacitor C A1, and the negative terminal of DC power supply is connected with the second end of capacitor C A1;
The first end of capacitor C A1 is connected with the second end of capacitor C A1 and the connecting line of DC power supply with switch transistor T B1 by the inductance L 1 of connecting successively with the connecting line of DC power supply;
The first end of capacitor C A1 is connected with the second end of capacitor C A1 and the connecting line of DC power supply with inductance L 2 by the switch transistor T B2 connecting successively with the connecting line of DC power supply;
The connecting line of inductance L 1 and switch transistor T B1 is connected with the first end of capacitor C A1 and the connecting line of DC power supply with capacitor C A2 by the diode DB1 connecting successively;
The second end of capacitor C A1 and the connecting line of DC power supply are connected with the connecting line of inductance L 2 with switch transistor T B2 with diode DB2 by the capacitor C A3 connecting successively;
The connecting line of diode DB1 and capacitor C A2 is connected with the second direct current positive level PV2+ of this continuous input cell, the first end of capacitor C A1 is connected with the first direct current positive level PV1+ of this continuous input cell with the connecting line of DC power supply, the second end of capacitor C A1 and the connecting line of DC power supply are connected with the first direct current negative level PV1-of this continuous input cell, and the connecting line of capacitor C A3 and diode DB2 is connected with the second direct current negative level PV2-of this continuous input cell.
9. according to four electrical level inverters described in claim 3,4,5 and 6 any one, it is characterized in that, described continuous input cell comprises capacitor C B1, capacitor C B2, capacitor C A2, capacitor C A3, inductance L 1, inductance L 2, switch transistor T B1, switch transistor T B2, diode DB1 and diode DB2, wherein:
The anode of DC power supply is connected with the negative terminal of DC power supply with capacitor C B2 by the capacitor C B1 connecting successively;
The connecting line of capacitor C B1 and DC power supply is connected with the connecting line of capacitor C B2 and DC power supply by inductance L 1, switch transistor T B1, switch transistor T B2 and the inductance L 2 of connecting successively;
The connecting line of capacitor C B1 and capacitor C B2 is connected with the connecting line of switch transistor T B2 with switch transistor T B1;
The connecting line of inductance L 1 and switch transistor T B1 is connected with the connecting line of capacitor C B1 and DC power supply with capacitor C A2 by the diode DB1 connecting successively;
The connecting line of capacitor C B2 and DC power supply is connected with the connecting line of inductance L 2 with switch transistor T B2 with diode DB2 by the capacitor C A3 connecting successively;
The connecting line of diode DB1 and capacitor C A2 is connected with the second direct current positive level PV2+ of this continuous input cell, the connecting line of capacitor C B1 and DC power supply is connected with the first direct current positive level PV1+ of this continuous input cell, the connecting line of capacitor C B2 and DC power supply is connected with the first direct current negative level PV1-of this continuous input cell, and the connecting line of capacitor C A3 and diode DB2 is connected with the second direct current negative level PV2-of this continuous input cell.
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| US10389271B2 (en) * | 2015-11-06 | 2019-08-20 | Hongliang Wang | Single-phase four-level inverter circuit topology and three-phase four-level inverter circuit topology |
| CN108377106B (en) * | 2018-05-11 | 2023-12-05 | 易事特集团股份有限公司 | Four-level topological unit and application circuit thereof |
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