CN102623452B - Electrostatic protection device and manufacturing process thereof - Google Patents
Electrostatic protection device and manufacturing process thereof Download PDFInfo
- Publication number
- CN102623452B CN102623452B CN201210102462.5A CN201210102462A CN102623452B CN 102623452 B CN102623452 B CN 102623452B CN 201210102462 A CN201210102462 A CN 201210102462A CN 102623452 B CN102623452 B CN 102623452B
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- China
- Prior art keywords
- silicon
- injection zone
- electrostatic protection
- trap
- controlled device
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Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 42
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 42
- 239000010703 silicon Substances 0.000 claims abstract description 42
- 239000004065 semiconductor Substances 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000002347 injection Methods 0.000 claims description 34
- 239000007924 injection Substances 0.000 claims description 34
- 239000012535 impurity Substances 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 3
- 150000001875 compounds Chemical class 0.000 claims 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims 1
- 238000007599 discharging Methods 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 abstract description 13
- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- 238000012423 maintenance Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 2
- 230000012447 hatching Effects 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- JCALBVZBIRXHMQ-UHFFFAOYSA-N [[hydroxy-(phosphonoamino)phosphoryl]amino]phosphonic acid Chemical compound OP(O)(=O)NP(O)(=O)NP(O)(O)=O JCALBVZBIRXHMQ-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/87—Thyristor diodes, e.g. Shockley diodes, break-over diodes
Abstract
The invention relates to the semiconductor manufacturing field, and discloses an electrostatic protection device, which comprises a silicon controlled rectifier (SCR) unit and a metal oxide semiconductor (MOS) tube unit; the SCR unit and the MOS tube unit are in series connection. The invention further discloses a manufacturing process of the electrostatic protection device, which includes manufacturing the SCR unit on a semiconductor substrate; manufacturing the MOS tube unit nearby the SCR; and connecting the SCR unit and the MOS tube unit in series. The electrostatic protection device has both a character of tiny parasitic capacitance of the SCR unit and a character of high sustaining voltage of the MOS tube unit, and is capable of being applied in high voltage radio frequency electronic circuits or the electrostatic protection of devices and the like.
Description
Technical field
The application relates to field of semiconductor manufacture, particularly a kind of electrostatic protection device and manufacturing process thereof.
Background technology
Static all existed in the nature moment, when the external environment condition of chip or the electrostatic charge of chip internal accumulation, when flowing into or flow out chip internal by the pin of chip, electric current (peak value can reach several amperes) or voltage that moment produces, will damage integrated circuit, chip functions was lost efficacy.Along with the development of semicon industry, characteristic size is further dwindled, and component density is increasing, and electronic devices and components suffer the possibility of electrostatic damage increasing, and industrialization electronic device must design qualified electrostatic protection.
In power amplifying device, the high power devices such as VDMOS, LDMOS, IGBT can bear high voltage, its electrostatic protection design requirement maintain also corresponding increasing of voltage.Meanwhile, as LDMOS is widely used in again high frequency wireless transmission field, the minimum parasitic capacitance of its electrostatic protection designing requirement opens and noise coupling to avoid opening by mistake.
Controllable silicon is as the electrostatic protection device of extensive use, its bleed off electrostatic charge ability excellence, and required area is little, and parasitic capacitance is little.But the dark hysteretic characteristic causing due to its positive feedback makes it maintain voltage and be limited near 1.7V, for fear of breech lock risk, it is limited to use in the circuit of low voltage.
Summary of the invention
Technical problems to be solved in this application are to provide a kind of have high maintenance voltage and minimum electrostatic protection device and the manufacturing process thereof of parasitic capacitance.
For addressing the above problem, the application provides a kind of electrostatic protection device, comprising: silicon-controlled device, metal-oxide-semiconductor device; Described silicon-controlled device is connected with described metal-oxide-semiconductor device.
The application also provides a kind of manufacturing process of electrostatic protection device, comprises the following steps:
On semiconductor base, make silicon-controlled device;
Near described silicon-controlled device, make metal-oxide-semiconductor;
Silicon-controlled device is connected with metal-oxide-semiconductor device.
The electrostatic protection device that the application provides, not only has the minimum parasitic capacitance of controllable silicon, also has the flexibly adjustable voltage that maintains, and it maintains voltage and can meet the electrostatic defending requirement of high-tension circuit and device.
Brief description of the drawings
The cutaway view of the electrostatic protection device that Fig. 1 provides for the embodiment of the present application.
The vertical view one of the electrostatic protection device that Fig. 2 provides for the embodiment of the present application.
The vertical view two of the electrostatic protection device that Fig. 3 provides for the embodiment of the present application.
The schematic equivalent circuit of the electrostatic protection device that Fig. 4 provides for the embodiment of the present application.
Embodiment
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing, embodiments of the invention are described in detail.
A kind of electrostatic protection device that the embodiment of the present application provides, comprises silicon-controlled device, metal-oxide-semiconductor device; Described silicon-controlled device is connected with described metal-oxide-semiconductor.The structure of silicon-controlled device comprises PNPN, PNPNP or NPNPN structure.The number of metal-oxide-semiconductor is at least one; When the number of metal-oxide-semiconductor is while being multiple, between metal-oxide-semiconductor, connect.
Referring to Fig. 1, the parasitic MOS electrostatic protection device that the application one embodiment provides, its manufacturing process is: the N trap 14 that forms debita spissitudo in the P of body silicon type substrate or extension 16; Form P+ injection zone 12 and N+ injection zone 11 in the interior injection of N trap 14 P type or N-type impurity, in P type substrate or extension 16, inject N-type impurity and form N+ injection zone 13 by the autoregistration of grid 15; P+ injection zone 12, N trap 14, P type substrate or extension 16, N+ injection zone 13 form the controllable silicon 42 of PNPN structure.And N+ injection zone 13 forms NMOS pipe 43 with grid 15.Controllable silicon 42 is serially connected in the electrostatic protection device with negative electrode and positive electrode with NMOS pipe 43.This device has the feature of the minimum parasitic capacitance of controllable silicon and metal-oxide-semiconductor or series connection metal-oxide-semiconductor high maintenance voltage concurrently, can be applicable to the electrostatic protection field of high-voltage radio-frequency electronic circuit or device.
As shown in Figure 2, in the P of body silicon type substrate or extension 16, form the N trap 14 of debita spissitudo; Form P+ injection zone 12 and N+ injection zone 11 in the interior injection of N trap 14 P type or N-type impurity, in P type substrate or extension 16, inject N-type impurity and form N+ injection zone 13 by the autoregistration of grid 15; N trap 14, P+ injection zone 12, N+ injection zone 11, grid 15 and N+ injection zone 13 are concentric circles distribution, as shown in the figure.Along its hatching line, A can obtain the semiconductor device structure shown in Fig. 2.P+ injection zone 12, N trap 14, P type substrate or extension 16, N+ injection zone 13 form the controllable silicon of PNPN structure, and N+ injection zone 13 forms NMOS pipe with grid 15, controllable silicon and NMOS pipe string connection.This concentric structure evenly flows out electric current, reduces the current density under equal current conditions, has strengthened the effect of heat dissipation, has strengthened device electrostatic protection ability.
As shown in Figure 3, in the P of body silicon type substrate or extension 16, form the N trap 14 of debita spissitudo; Form P+ injection zone 12 and N+ injection zone 11 in the interior injection of N trap 14 P type or N-type impurity, in P type substrate or extension 16, inject N-type impurity and form N+ injection zone 13 by the autoregistration of grid 15; P+ injection zone 12, N trap 14, P type substrate or extension 16, N+ injection zone 13 form the controllable silicon of PNPN structure, and N+ injection zone 13 forms NMOS pipe with grid 15.Along its hatching line, B can obtain the semiconductor device structure shown in Fig. 1.Different due to metal-oxide-semiconductor and controllable silicon bleed off electric charge ability, four times of the effective width that the effective grid width suggestion of NMOS pipe is controllable silicon, obtain controllable silicon and NMOS pipe string connection to have improved the device that maintains voltage and reduced parasitic capacitance in maintenance antistatic capacity.
The schematic equivalent circuit of the electrostatic protection device that Fig. 4 provides for the embodiment of the present invention.As shown in Figure 4, controllable silicon 42 is connected and is obtained electrostatic protection device 41 with the NMOS pipe 43 of grounded-grid.The NMOS pipe 43 of grounded-grid is different from controllable silicon 42 bleed off electric charge abilities, suppose to reach under the condition of HBM 4kV at antistatic capacity, approximately 50 microns of the effective widths of controllable silicon 42, and effective grid width of the NMOS of grounded-grid pipe 43 is advised 200 microns of left and right, and do not limit controllable silicon 42 and make the optimal design such as low-voltage triggering, the unlatching of grid coupled voltages or substrate current injection unlatching.To be controllable silicon 42 parasitic capacitances manage the 43 parasitic capacitances sum of connecting, C with the NMOS of grounded-grid to the total capacitance of device 41
total=C
sCR× C
mOS/ (C
sCR+ C
mOS).Usually, the parasitic capacitance of controllable silicon 42 is less much smaller than NMOS pipe 11 and controllable silicon 42 sizes of grounded-grid, so total parasitic capacitance of device 41 is very little, is applicable to application and high-frequency circuit and radio-frequency devices.The voltage that maintains of supposing controllable silicon 42 is V
sCR, the voltage that maintains of the NMOS pipe 43 of grounded-grid is V
mOS, device 41 always maintain voltage V
total=V
sCR+ V
mOS, can be used in the electrostatic protection design of higher point volt circuit and device.In addition, if the NMOS of grounded-grid pipe 43 be n the metal-oxide-semiconductor of connecting, device 41 always maintain voltage V
total=V
sCR+ V
mOS1+ V
mOS2+ ...+V
mOSn, the high maintenance Voltage Static electric protective component obtaining can meet the electrostatic protection demand of high tension apparatus.
A kind of electrostatic protection device that the application proposes has following beneficial effect:
1, there is high maintenance voltage and parasitic capacitance minimum, can be applicable to the electrostatic protection field of high-voltage radio-frequency electronic circuit or device.
2, simple in structure, cost is lower, higher in the feasibility of industrial enforcement.
3, can make electric current evenly flow out, reduce the current density under equal current conditions, strengthen the effect of heat dissipation, strengthen device electrostatic protection ability.
It should be noted last that, above embodiment is only in order to the application's technical scheme to be described and unrestricted, although the application is had been described in detail with reference to example, those of ordinary skill in the art is to be understood that, can modify or be equal to replacement the application's technical scheme, and not departing from the spirit and scope of present techniques scheme, it all should be encompassed in the middle of the application's claim scope.
Claims (3)
1. a manufacturing process for electrostatic protection device, is characterized in that, comprising:
On semiconductor base, make silicon-controlled device; The described silicon-controlled device of making on semiconductor base comprises: in the P of body silicon type substrate, form N trap; In N trap, inject p type impurity and form P+ injection zone; In N trap, inject N-type impurity and form a N+ injection zone; Formed the silicon-controlled device of PNPN structure by described P+ injection zone, N trap, P type substrate, a N+ injection zone;
Near described silicon-controlled device, make NMOS pipe; Describedly comprise making NMOS pipe near described silicon-controlled device: in P type substrate, inject N-type impurity and form the 2nd N+ injection zone by the autoregistration of grid; Form NMOS tube device by described the 2nd N+ injection zone and grid; Described N trap, P+ injection zone, the 2nd N+ injection zone, grid and a N+ injection zone are that concentric circles distributes;
Silicon-controlled device is connected with NMOS tube device.
2. technique according to claim 1, is characterized in that, described silicon-controlled device is connected with NMOS tube device is
The anode of silicon controlled negative electrode and NMOS tube device is merged, make complete connection of charge discharging resisting path of controllable silicon and NMOS tube device.
3. according to the technique described in claim 1-2 any one, it is characterized in that:
Described semiconductor base is body silicon or SOI or III-V compounds of group; Described III-V compounds of group is GaN or GaAs.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210102462.5A CN102623452B (en) | 2012-04-09 | 2012-04-09 | Electrostatic protection device and manufacturing process thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210102462.5A CN102623452B (en) | 2012-04-09 | 2012-04-09 | Electrostatic protection device and manufacturing process thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102623452A CN102623452A (en) | 2012-08-01 |
| CN102623452B true CN102623452B (en) | 2014-12-03 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210102462.5A Active CN102623452B (en) | 2012-04-09 | 2012-04-09 | Electrostatic protection device and manufacturing process thereof |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103258814B (en) * | 2013-05-15 | 2015-07-29 | 电子科技大学 | LDMOS SCR device is used in a kind of integrated circuit (IC) chip ESD protection |
| CN105097795B (en) | 2014-05-04 | 2018-03-16 | 无锡华润上华科技有限公司 | Has the semiconductor devices of esd protection structure |
| CN113675832B (en) * | 2021-10-22 | 2022-02-08 | 武汉市聚芯微电子有限责任公司 | Electrostatic protection method, electrostatic protection circuit and chip |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1396662A (en) * | 2001-07-09 | 2003-02-12 | 联华电子股份有限公司 | Low voltage triggered SCR containing Si in insulating layer and protecting circuit for electrostatic discharge |
| US7719026B2 (en) * | 2007-04-11 | 2010-05-18 | Fairchild Semiconductor Corporation | Un-assisted, low-trigger and high-holding voltage SCR |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6838707B2 (en) * | 2002-05-06 | 2005-01-04 | Industrial Technology Research Institute | Bi-directional silicon controlled rectifier for electrostatic discharge protection |
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2012
- 2012-04-09 CN CN201210102462.5A patent/CN102623452B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1396662A (en) * | 2001-07-09 | 2003-02-12 | 联华电子股份有限公司 | Low voltage triggered SCR containing Si in insulating layer and protecting circuit for electrostatic discharge |
| US7719026B2 (en) * | 2007-04-11 | 2010-05-18 | Fairchild Semiconductor Corporation | Un-assisted, low-trigger and high-holding voltage SCR |
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| Publication number | Publication date |
|---|---|
| CN102623452A (en) | 2012-08-01 |
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Owner name: BEIJING YANDONG MICROELECTRNIC CO.,LTD. Free format text: FORMER OWNER: INST OF MICROELECTRONICS, C. A. S Effective date: 20150720 |
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| TR01 | Transfer of patent right |
Effective date of registration: 20150720 Address after: 100015 Beijing city Chaoyang District Dongzhimen West eight room Wanhong No. 2 West Street Patentee after: Beijing Yandong Microelectronic Co., Ltd. Address before: 100029 Beijing city Chaoyang District Beitucheng West Road No. 3 Patentee before: Institute of Microelectronics, Chinese Academy of Sciences |
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| CP02 | Change in the address of a patent holder |
Address after: 100020 West eight rooms, dongzhimenwai, Chaoyang District, Beijing Patentee after: Beijing Yandong Microelectronic Co., Ltd. Address before: 100015 Beijing city Chaoyang District Dongzhimen West eight room Wanhong No. 2 West Street Patentee before: Beijing Yandong Microelectronic Co., Ltd. |
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