CN102593799B

CN102593799B - Relay protection circuit

Info

Publication number: CN102593799B
Application number: CN201210065401.6A
Authority: CN
Inventors: 刘建华
Original assignee: GUANGZHOU FINEART LIGHTING CO Ltd
Current assignee: Guangzhou Caiyi Light Co Ltd
Priority date: 2012-03-14
Filing date: 2012-03-14
Publication date: 2014-02-19
Anticipated expiration: 2032-03-14
Also published as: CN102593799A

Abstract

The invention discloses a relay protection circuit, which comprises a controller, a first nand gate, a second nand gate, a first delay circuit, a second delay circuit, a signal drive circuit, a triode Q2, a photoelectric isolator, a silicon controlled rectifier, a first relay RLY 1 and a second relay RLY 2, wherein the elements are connected to form the circuit. The relay protection circuit has the advantages that as two delay circuits are arranged in the circuit to be matched with other elements, the electricity-passing-time of contacts of the relays is delayed relative to the closing time of the contacts, so that the phenomena that the contacts of the relays are electrified immediately when the relays are in contact and contact splashing matters are produced are avoided.

Description

A kind of relay protection circuit

Technical field

The present invention relates to the protective circuit of a kind of intelligent lighting system controller the inside relay.

Background technology

In the equipment such as motor or light are controlled, a lot of loops are to be together in parallel by some load units, and bearing power is very large like this, all up to 2000W-3000W power.Due to break-make, easily produce contact splash during compared with heavy load, they can be attached on contact, and electric current is larger, more easily cause contact bonding and can not disconnect.

A lot of light fixtures are when cold conditions, and resistance is very little, almost approaches instantaneous short circuit, and it is big that during startup, electric current has 5 times-10 times of normal operations, with regard to being easy to, the relay contact in control circuit caused to damage like this in moment, causes the controller lost of life, lost efficacy.Especially motor load, to start moment larger, is easy to damage relay like this.

Summary of the invention

Goal of the invention of the present invention is to overcome the defect of prior art, and a kind of relay protection circuit is provided, and this protective circuit can effectively avoid relay to burn, and improves the useful life of relay.

For achieving the above object, the present invention adopts following technical scheme: a kind of relay protection circuit, comprising: controller, the first NAND gate, the second NAND gate, the first delay circuit, the second delay circuit, signal drive circuit, triode Q2, photoisolator, controllable silicon, the first relay R LY1 and the second relay R LY2, the input of described the first NAND gate and output are connected with the input of the first delay circuit with one of output of controller respectively, the input of signal drive circuit is connected with the base stage of triode Q2 with the output of the first delay circuit respectively with output, the collector electrode of triode Q2 is connected with control circuit one end of the first relay R LY1, the grounded emitter of triode Q2,12 volts of voltages of another termination of the control circuit of the first relay, the input of described the second delay circuit is connected with the input of the second NAND gate with the input of the first NAND gate respectively with output, the output of the second NAND gate is connected with the input of photoisolator, two outputs of photoisolator are connected with the zero line of silicon controlled input and working power respectively, the operating circuit end of the first relay R LY1 is connected with working power live wire with controllable silicon output respectively, the control circuit end of the second relay R LY2 connects respectively another output of 12 volts of voltages and controller, the operating circuit end of the second relay R LY2 connects respectively live wire and the zero line of working power.

Described delay circuit comprises resistance R, diode D and capacitor C, one end of described resistance R is connected with the positive pole of diode D, the other end is connected with the negative pole of diode D, the positive pole of capacitor C connects the negative pole of diode D, the minus earth of electric capacity, the input of the just very delay circuit of diode D wherein, the output that negative pole is delay circuit.

Described drive signal circuit comprises the 3rd NAND gate and the 4th NAND gate, the input of the 3rd NAND gate is connected with the input of the 4th NAND gate with the output of the first delay circuit respectively with output, and the output of the 4th NAND gate is connected with the base stage of triode Q2.

The invention has the beneficial effects as follows: by two delay circuits are set in circuit, coordinate other components and parts, it's electricity relative time of closing contact of time make past the contact of relay and delay, while avoiding relay contact contact, switch on, produce contact splash.

Accompanying drawing explanation

Fig. 1 is fundamental diagram of the present invention;

Fig. 2 is circuit diagram of the present invention;

Fig. 3 is the present invention's oscillogram that a, b, c are ordered while working.

Embodiment

Shown in Fig. 1, relay protection circuit of the present invention comprises a controller, the first NAND gate, the second NAND gate, the first delay circuit, the second delay circuit, triode Q2, photoisolator, controllable silicon, relay R LY1 and relay R LY2, described delay circuit comprises resistance R, diode D and capacitor C, one end of described resistance R is connected with the positive pole of diode D, the other end is connected with the negative pole of diode D, the positive pole of capacitor C connects the negative pole of diode D, the minus earth of electric capacity, the input of the just very delay circuit of diode D wherein, the output that negative pole is delay circuit, described drive signal circuit comprises the 3rd NAND gate and the 4th NAND gate, the input of the 3rd NAND gate is connected with the input of the 4th NAND gate with the output of the first delay circuit respectively with output, and the output of the 4th NAND gate is connected with the base stage of triode Q2, the input of described the first NAND gate and output are connected with the input of the first delay circuit with one of output of controller respectively, the input of signal drive circuit is connected with the base stage of triode Q2 with the output of the first delay circuit respectively with output, the collector electrode of triode Q2 is connected with control circuit one end of the first relay R LY1, the grounded emitter of triode Q2,12 volts of voltages of another termination of the control circuit of the first relay, the input of described the second delay circuit is connected with the input of the second NAND gate with the input of the first NAND gate respectively with output, the output of the second NAND gate is connected with the input of photoisolator, two outputs of photoisolator are connected with the zero line of silicon controlled input and working power respectively, the operating circuit end of the first relay R LY1 is connected with working power live wire with controllable silicon output respectively, the control circuit end of the second relay R LY2 connects respectively another output of 12 volts of voltages and controller, the operating circuit end of the second relay R LY2 connects respectively live wire and the zero line of working power.

The specific works flow process of relay protection circuit of the present invention is as follows:

As shown in Figure 2, the process that load is opened: controller is first from signal input DO1 end input low level signal, due to the former high level before this of capacitor C 1 anode, through R2 electric discharge, discharge time 220ms, C point need to just reach high level through 220ms, could conducting controllable silicon.And the former low level before this of capacitor C 2, when D01 end input low level, through X1A NAND gate, become high level, through diode D2, directly to C2 charging, there is no resistance current limliting, be full of fast, become high level, through NAND gate X1C, X1D strengthens signal driver ability, at b point output high level, drives triode Q2, give the control circuit energising of relay R LY1, the contact adhesive of relay R LY1, now due to not yet conducting of controllable silicon, RLY1 upper contact closure does not have electric arc to produce.At D01 end input low level simultaneously, C1 is directly through R2 electric discharge, after discharge time 220ms, by X1B NAND gate output high level, drives photoisolator U1, and rfpa output signal triggers controllable silicon, the upper energising of relay R LY1, and load is started working.Controller postpones 300ms after D01 end output low level signal, through RY1, hold output low level signal to relay R LY2, relay R LY2 connects, due to RLY2 now, RLY1, the equal conducting of controllable silicon, triode Q1 in controllable silicon can generate heat, in order not increase radiator, so controller also needs a DO1 signal to disconnect after load is started working, a point becomes high level, through D1 diode, directly to C1, charging becomes high level, through an X1B NAND gate, C point becomes low level, through light-coupled isolation output low level signal, controllable silicon disconnects, a point becomes low level through X1A NAND gate at the same time, C2 is through R1 electric discharge, need 220ms to be discharged, through two NAND gate, strengthen driving force again, b point becomes low level, triode Q2 cut-off, RLY1 disconnects, to this action of opening load, all complete.This process had both been protected RLY2, had solved again the problem of controllable silicon heat radiation by RLY1.

Load closing process: controller is first from DO1 end input low level signal, due to the former high level before this of C1 anode, so through R2 electric discharge, discharge time, 220ms, just reach high level, conducting controllable silicon so C point need to pass through 220ms.And the former low level before this of C2, when D01 end input low level, is directly charged to C2 through D2, do not postpone, be full of very soon, become high level, then through two NAND gate X1C, X1D strengthens driving force, at b point output high level, drives Q2 triode turn-on relay RLY1.Controller postpones 300ms from RY1 input high level signal, and relay R LY2 disconnects, and load quits work.For cut-off protection circuit, now DO1 signal needs to disconnect, and a point becomes high level; C1 charging becomes high level; through an X1B NAND gate, C point becomes low level, and controllable silicon disconnects; a point becomes low level through X1A NAND gate; C2, through R1 electric discharge, needs 220ms to be discharged, and b point becomes low level; RLY1 disconnects, and closes load action all complete to this switch.This process has protected RLY2 in disconnection process, prevents that electric arc from burning contact, has also solved the problem of controllable silicon heat radiation simultaneously.Output timing oscillogram is as Fig. 3.

Claims

1. a relay protection circuit, is characterized in that comprising: controller, the first NAND gate, the second NAND gate, the first delay circuit, the second delay circuit, signal drive circuit, triode Q2, photoisolator, controllable silicon, the first relay R LY1 and the second relay R LY2, the input of described the first NAND gate and output are connected with the input of the first delay circuit with one of output of controller respectively, the input of signal drive circuit is connected with the base stage of triode Q2 with the output of the first delay circuit respectively with output, the collector electrode of triode Q2 is connected with control circuit one end of the first relay R LY1, the grounded emitter of triode Q2,12 volts of voltages of another termination of the control circuit of the first relay R LY1, the input of described the second delay circuit is connected with the input of the second NAND gate with the input of the first NAND gate respectively with output, the output of the second NAND gate is connected with the input of photoisolator, two outputs of photoisolator are connected with the zero line of silicon controlled input and working power respectively, the operating circuit end of the first relay R LY1 is connected with working power live wire with controllable silicon output respectively, the control circuit end of the second relay R LY2 connects respectively another output of 12 volts of voltages and controller, the operating circuit end of the second relay R LY2 connects respectively live wire and the zero line of working power.

2. relay protection circuit according to claim 1; it is characterized in that: described delay circuit comprises resistance R, diode D and capacitor C; one end of described resistance R is connected with the positive pole of diode D; the other end is connected with the negative pole of diode D; the positive pole of capacitor C connects the negative pole of diode D; the minus earth of electric capacity, the input of the just very delay circuit of diode D wherein, the output that negative pole is delay circuit.

3. relay protection circuit according to claim 1; it is characterized in that: described drive signal circuit comprises the 3rd NAND gate and the 4th NAND gate; the input of the 3rd NAND gate is connected with the input of the 4th NAND gate with the output of the first delay circuit respectively with output, and the output of the 4th NAND gate is connected with the base stage of triode Q2.