CN102593198B - Manufacturing method of II-VI group laminating integrated nano photovoltaic device and - Google Patents
Manufacturing method of II-VI group laminating integrated nano photovoltaic device and Download PDFInfo
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- CN102593198B CN102593198B CN2012100536448A CN201210053644A CN102593198B CN 102593198 B CN102593198 B CN 102593198B CN 2012100536448 A CN2012100536448 A CN 2012100536448A CN 201210053644 A CN201210053644 A CN 201210053644A CN 102593198 B CN102593198 B CN 102593198B
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Abstract
The invention discloses an II-VI group laminating integrated nano photovoltaic device and a manufacturing method of the II-VI group laminating integrated nano photovoltaic device. The bottom layer of the photovoltaic device is a heavily doped silicon wafer (4), the upper layer of the heavily doped silicon wafer (4) is a PMMA (Polymethyl Methacrylate) insulating layer (2), at least one II-VI group nano material (3) is arranged in the PMMA insulating layer in an array manner; the II-VI group nano material (3) penetrates through the PMMA insulating layer (2) in the direction perpendicular to the plane of the PMMA insulating layer (2); and an electrode (1) is in ohm contact with the at least one II-VI group nano material (3). The manufacturing method of the photovoltaic device is simple and easy to operate, low in cost, more stable in performance of the photovoltaic device, can be used for manufacturing various nano structure silicon-based heterojunction photovoltaic devices and integrating the photovoltaic device in a large scale.
Description
One, technical field:
The present invention relates to a kind of photovoltaic device and preparation method thereof, more precisely be based on II-VI family/silicon heterogenous stacked integrated nanometer photovoltaic device.
Two, background technology
Solar-energy photo-voltaic cell is directly light energy conversion to be become to the device of electric energy by photoelectric effect or Photochemical effects.Owing to having zero discharge, pollution-free, environmental protection, the characteristics such as the life-span is long, be considered to alleviate energy shortage and reduce one of important technology of greenhouse gas emission, be widely used at present space flight, industrial and agricultural production, domestic life etc. multiple fields.
The accurate one dimension semiconductor of II-VI family, comprise ZnO, ZnS, ZnSe, ZnTe, CdS, CdSe and CdTe nano wire/band/pipe etc., have the excellent properties such as high-crystal quality, well transport property, and high-luminous-efficiency, be widely used at aspects such as luminous, photodetection, photovoltaic devices.Solar cell based on II-VI family nanostructure also has report in recent years, but it extensively exists photovoltaic performance poor, complicated process of preparation, and the shortcoming such as poor controllability.
Three, summary of the invention:
The present invention aims to provide stacked integrated nanometer photovoltaic device of a kind of II-VI family and preparation method thereof, and technical problem to be solved is under the prerequisite of simplifying the preparation method, to strengthen the conversion efficiency of nano photovoltaic device, increases photovoltaic device photosensitive layer area.
Technical solution problem of the present invention adopts following technical scheme:
II-VI family of the present invention stacked integrated nanometer photovoltaic device difference with the prior art is: the bottom of the described photovoltaic device doped silicon wafer 4 of attaching most importance to, the upper strata of described heavy doping silicon chip 4 is PMMA insulating barrier 2, in described PMMA insulating barrier, array arrangement has the II-VI family nano material 3 of at least one, described II-VI family nano material 3 is exposed on PMMA insulating barrier 2 surfaces, and electrode 1 is positioned at the surface of described PMMA insulating barrier 2 and described electrode 1 and is ohmic contact with at least one described II-VI family nano material 3;
Described II-VI family nano material 3 is nano wire, nanobelt or nanotube;
Described II-VI family nano material 3 is selected from ZnSe, ZnS, ZnO or CdS;
Described heavy doping silicon chip 4 is n-type doped silicon wafer or p-type doped silicon wafer;
Described II-VI family nano material 3 is p-type doped with II-VI family nano material or n-type doped with II-VI family nano material;
When described heavy doping silicon chip 4 during for n-type doped silicon wafer described II-VI family nano material be p-type doped with II-VI family nano material; When described heavy doping silicon chip 4 during for p-type doped silicon wafer described II-VI family nano material be n-type doped with II-VI family nano material;
Described electrode 1 is Au, Al, ITO, In or Graphene etc.; Being shaped as of described electrode 1 is circular, square, bar shaped etc.
The doped source of described p-type doped with II-VI family nano material is selected from one or more in N, P, As, Bi, Ag; The doped source of described N-shaped doped with II-VI family nano material is selected from one or more in Ga, In, Cl, I.When doped source was multiple, each doped source ratio was any.
The doping of doped source gets final product with the requirement met signal, and doping is low, and signal is little, and doping is high, and signal is large, by different doping regulation and control, can obtain different signals, as long as meet the n/P type character of nano photovoltaic device.
The preparation method of the stacked integrated nanometer photovoltaic device of II-VI family of the present invention is characterized in that operating according to the following steps:
A, heavy doping silicon chip 4 is placed in to mass concentration is 5% hydrofluoric acid solution etching 2-3 minute, removes the thin oxide layer on heavy doping silicon chip 4 surfaces, and after taking out, ultrasonic cleaning drying obtain pretreated heavy doping silicon chip;
B, II-VI family nano material 3 is dispersed on pretreated heavy doping silicon chip, then spin coating one deck PMMA insulating barrier 2 oven dry, the thickness of the PMMA insulating barrier 2 II-VI family nano material 3 of being annihilated fully at least, make II-VI family nano material 3 invisible on the surface of PMMA insulating barrier 2;
While preparing in batches, growth can there be is the silicon substrate of II-VI family nano material 3 to cover on pretreated heavy doping silicon chip and carry out orientation scratch, make II-VI family nano material 3 be arranged on heavy doping silicon chip 4 with array format, can control array density by the distance of adjusting 4 of silicon substrate and heavy doping silicon chips and the number of times scratched.
C, use oxygen gas plasma etching (plasma) PMMA insulating barrier 2, until the surface of PMMA insulating barrier 2 stops etching while exposing II-VI family nano material 3, now on heavy doping silicon chip 4, do not disperse the position of II-VI family nano material 3 to still have PMMA insulating barrier 2;
D, utilize electron beam technology on PMMA insulating barrier 2, to prepare electrode 1 by mask plate, and electrode 1 is ohmic contact with II-VI family nano material 3, obtains the stacked integrated nanometer photovoltaic device of II-VI family.
Photosensitive material of the present invention is II-VI family nano material, can obtain N-shaped or p-type material by adopting different doped source.
Compared with the prior art, beneficial effect of the present invention is embodied in:
1, the present invention adopts PMMA as insulating material, and method simply is easy to realize, and cost is low.
2, the present invention adopts the method for displacement that nano material is arranged into to array way, and array density is controlled, makes between electrode the II-VI family nano material that has quantity controlled, can be used for the preparation of large-scale integrated nano photovoltaic device.
3, the present invention makes the conversion efficiency of nano photovoltaic device be improved under the prerequisite of having simplified the preparation method.
Four, accompanying drawing explanation:
Fig. 1 is the structural representation of II-VI family of the present invention stacked integrated nanometer photovoltaic device individual devices.
Fig. 2 is the structural representation of the stacked integrated nanometer photovoltaic device of II-VI family of the present invention a plurality of devices while preparing in batches.
Wherein 1 is electrode, and 2 is the PMMA insulating barrier, and 3 is II-VI family nano material, 4 doped silicon wafer of attaching most importance to.
Fig. 3 is the SEM figure of the p-type-ZnSe/n type-stacked integrated nanometer photovoltaic device of Si heterojunction of the embodiment of the present invention 1 preparation, and lower right corner illustration is the arrange SEM figure of situation of nano wire.
Fig. 4 is the photovoltaic property curve of the p-type-ZnSe/n type-stacked integrated nanometer photovoltaic device of Si heterojunction of the embodiment of the present invention 1 preparation.
Fig. 5 is the p-type-ZnSe/n type-photoresponse curve of Si heterojunction under the 0V bias voltage of the embodiment of the present invention 1 preparation.
Fig. 6 is the photovoltaic property curve of the N-shaped-ZnSe/p type-stacked integrated nanometer photovoltaic device of Si heterojunction of the embodiment of the present invention 2 preparation.
Fig. 7 is the N-shaped-ZnSe/p type-photoresponse curve of Si heterojunction under the 0V bias voltage of the embodiment of the present invention 2 preparation.
Five, embodiment
Below in conjunction with accompanying drawing, describe the preparation method of the stacked integrated nanometer photovoltaic device of II-VI family of the present invention in detail, wherein II-VI family nano material adopts the ZnSe nano wire, and non-limiting examples is as follows.
Embodiment 1:
A, n-type heavy doping silicon chip is placed in to mass concentration is 5% hydrofluoric acid solution etching 2 minutes, removes the oxide layer on heavy doping silicon chip surface, uses the acetone ultrasonic cleaning after taking out, and dries up standby.
B, there is the silicon substrate of p-type Ag doped ZnS e nano wire (doping 15%) to cover on n-type heavy doping silicon chip to carry out orientation to scratch growth, make p-type Ag doped ZnS e nano wire transfer on n-type heavy doping silicon chip and arrange with array format, array density 40-42 root/cm
2.
C, the n-type heavy doping silicon chip that will be evenly equipped with p-type Ag doped ZnS e nano wire are placed on glue evenning table spin coating one deck PMMA (model 445746-25G, Aldrich) insulating barrier, and (the spin coating parameter is: low speed 600r/s, t=9s; High speed 3000r/s, t=30s), then be placed on the drying glue platform and dry (Flue curing parameter is 100 ℃, t=3min), and the thickness of the PMMA insulating barrier II-VI family nano material of being annihilated fully;
D, use oxygen plasma etching (model PDC-32G, low-grade parameter 680V DC, 10mA DC, 6.8W) the PMMA insulating barrier, until the surface of PMMA insulating barrier stops etching while II-VI family nano material occurring, etch period 4min, oxygen flow are 10sccm.Now on the heavy doping silicon chip, do not disperse the position of II-VI family nano material to still have the PMMA insulating barrier.
D, utilize electron beam technology on the PMMA insulating barrier, to prepare the Au electrode of thickness for 10nm by the circular hole mask plate, and this Au electrode and Ag doped ZnS e nano wire form ohmic contact, obtain the stacked integrated nanometer photovoltaic device of p-type-ZnSe/n type-Si.
The folded integrated nanometer photovoltaic device SEM figure of ZnSe layer prepared by the present embodiment as shown in Figure 3.Fig. 4 is is 0.35mWcm in light intensity
-2Under the white light conditions of power, the photovoltaic property curve of p-type-ZnSe/n type-stacked integrated nanometer photovoltaic device of Si heterojunction, open circuit voltage Voc is 0.25V, and short circuit current Isc is 10.87nA, and fill factor, curve factor FF is 47%, and conversion efficiency is 0.09%.Fig. 5 is the p-type-ZnSe/n type-photoresponse curve of Si heterojunction under the 0V bias voltage, shows this heterogeneous good photovoltaic property and stability of having.
Embodiment 2:
The present embodiment preparation method is with embodiment 1, different is that the heavy doping silicon chip is p-type heavy doping silicon chip, II-VI family nano material is N-shaped-I doped ZnS e nano wire (doping 20%), uses ITO (tin indium oxide) as with it, becoming the electrode material of ohmic contact.Prepare the photovoltaic property curve of N-shaped-stacked integrated nanometer photovoltaic device of ZnSe/p type-Si as shown in Figure 6, open circuit voltage Voc is 0.22V, and short circuit current Isc is 50.13nA, and fill factor, curve factor FF is 46%, and conversion efficiency is 0.12%.N-shaped-ZnSe/p type-the photoresponse curve of Si heterojunction under the 0V bias voltage as shown in Figure 7, shows this heterogeneous good photovoltaic property and stability of having.
In actual the use, can to photosensitive layer and doping, doped chemical, electrode material and shape, adjust according to demand, obtain suitable nano photovoltaic device.
Claims (2)
1. the preparation method of the stacked integrated nanometer photovoltaic device of II-VI family is characterized in that operating according to the following steps:
A, heavy doping silicon chip (4) is placed in to mass concentration is 5% hydrofluoric acid solution etching 2-3 minute, removes the thin oxide layer on heavy doping silicon chip (4) surface, and after taking out, ultrasonic cleaning drying obtain pretreated heavy doping silicon chip;
B, II-VI family nano material (3) is dispersed on pretreated heavy doping silicon chip to spin coating one deck PMMA insulating barrier (2) drying then, the thickness of PMMA insulating barrier (2) the II-VI family nano material of being annihilated fully at least;
C, with oxygen gas plasma etching PMMA insulating barrier, until the surface of PMMA insulating barrier (2) stops etching while exposing II-VI family nano material (3);
D, utilize electron beam technology on PMMA insulating barrier (2), to prepare electrode (1) by mask plate, and electrode (1) is ohmic contact with II-VI family nano material (3), obtains the stacked integrated nanometer photovoltaic device of II-VI family;
The bottom of the described photovoltaic device doped silicon wafer (4) of attaching most importance to, the upper strata of described heavy doping silicon chip (4) is PMMA insulating barrier (2), in described PMMA insulating barrier, array arrangement has the II-VI family nano material (3) of at least one, described II-VI family's nano material (3) is exposed on PMMA insulating barrier (2) surface, and surface and described electrode (1) that electrode (1) is positioned at described PMMA insulating barrier (2) are ohmic contact with at least one described II-VI family's nano material (3);
Described II-VI family's nano material (3) is nano wire, nanobelt or nanotube;
Described II-VI family's nano material (3) is selected from ZnSe, ZnS, ZnO or CdS;
Described heavy doping silicon chip (4) is n-type doped silicon wafer or p-type doped silicon wafer;
Described II-VI family's nano material (3) is p-type doped with II-VI family nano material or n-type doped with II-VI family nano material;
When described heavy doping silicon chip (4) described II-VI family nano material when the n-type doped silicon wafer is p-type doped with II-VI family nano material; When described heavy doping silicon chip (4) described II-VI family nano material when the p-type doped silicon wafer is n-type doped with II-VI family nano material;
Described electrode (1) is Au, Al, ITO, In or Graphene.
2. preparation method according to claim 1 is characterized in that:
The doped source of described p-type doped with II-VI family nano material is selected from one or more in N, P, As, Bi, Ag; The doped source of described n-type doped with II-VI family nano material is selected from one or more in Ga, In, Cl, I.
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