CN102544222A - Method for preparing sub-pixel structured planar InGaAs infrared detector chip - Google Patents

Method for preparing sub-pixel structured planar InGaAs infrared detector chip Download PDF

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CN102544222A
CN102544222A CN2012100191141A CN201210019114A CN102544222A CN 102544222 A CN102544222 A CN 102544222A CN 2012100191141 A CN2012100191141 A CN 2012100191141A CN 201210019114 A CN201210019114 A CN 201210019114A CN 102544222 A CN102544222 A CN 102544222A
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electrode
photoetching
growth
pixel
sub
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邓洪海
唐恒敬
李淘
李雪
魏鹏
朱耀明
王云姬
杨波
龚海梅
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Shanghai Institute of Technical Physics of CAS
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Shanghai Institute of Technical Physics of CAS
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Abstract

The invention discloses a method for preparing a sub-pixel structured planar InGaAs infrared detector chip, which comprises the following steps of: 1, extension material cleaning; 2, silicon nitride diffusion mask sedimentation; 3, first photoetching ; 4, sub-pixel diffuse window opening; 5, photoresist stripping; 6, closed pipe diffusion; 7, open-pipe piece taking; 8, second photoetching; 9, P electrode growing; 10, photoresist stripping; 11, silicon dioxide antireflection film sedimentation; 12, P electrode annealing; 13, third photoetching; 14, P electrode hole forming; 15, photoresist stripping; 16, fourth photoetching; 17, P electrode thickening; 18, photoresist stripping; 19, back side polishing; 20, N electrode growing; and 21, scribing. According to the invention, under the condition that the quantum efficiency of the prepared detector is not reduced, the photosensor can respond uniformly, the service life of the minority carrier is increased, and the dark current of the device is reduced; and due to the structure, as for a linear detector, the blind pixel rate can be effectively reduced, and the extension and cross talk of the photosensor are suppressed.

Description

The sub-pixel structure of a kind of plane indium-gallium-arsenide infrared detector chip preparation method
Technical field
The infrared detector chip preparation method who the present invention relates to specifically is meant a kind of positive irradiated plane type indium gallium arsenic (InGaAs) infrared detector chip preparation technology.
Background technology
Indium gallium arsenic short-wave infrared detector can at room temperature be worked, and is with a wide range of applications.At present PIN indium gallium arsenic detector mainly is divided into two types of plane and mesas.Mesa device is because side passivation difficulty, causes that device reliability reduces, dark current is bigger, this to a great extent limit the raising of device detectivity.Planar type detector is as the main flow structure of indium gallium arsenic detector, has that passivation is easy, dark current is low, the reliability advantages of higher, is highly suitable for the air remote sensing field.But there is photosensitive first enlargement phenomenon in planar device, and suppresses the cross-talk between the photosensitive unit of detector array is difficult, therefore needs a kind ofly suppress photosensitive first expansion with cross-talk, further reduce new construction, the new method of device dark electric current, raising device detectivity.
Summary of the invention
A kind of plane indium gallium arsenic detector new construction based on sub-pixel pattern has been proposed to novelty of the present invention; Promptly realize the uniform response that diffuses into knot and photosensitive unit zone of device through sub-pixel pattern; And through sub-pixel structure optimization design; Reach the purpose of effective inhibition photosensitive unit expansion and adjacent photosensitive first cross-talk, further reduce the dark current of device simultaneously, improve the detectivity of device.
Novel planar type pixel structure indium-gallium-arsenide infrared detector chip structure of the present invention is shown in accompanying drawing 2, and it comprises N type InP substrate 1, N type InP layer 2, indium gallium arsenic intrinsic absorbed layer 3, N type InP cap layer 4, silicon nitride diffusion mask layer 5, sub-pixel diffusion window oral region 6, sub-pixel PN junction district 7, charge carrier side direction collecting region 8, P electrode 9, silicon dioxide antireflection layer 10, adds thick electrode 11, N electrode 12.At first on N type InP substrate 1, be arranged in order growth N type InP layer 2, indium gallium arsenic intrinsic absorbed layer 3, N type InP cap layer 4 through epitaxy method; The thickness of indium gallium arsenic intrinsic absorbed layer is 1～3 μ m; Deposit silicon nitride diffusion mask layer 5 plays the effect of passivation layer simultaneously as the diffusion mask layer on NIN type epitaxial wafer then.Form yi word pattern pixel diffusion window oral region 6 side by side through conventional wet corrosion technique, sub-pixel diffusion window shape is rectangle, and quantity is more than or equal to 2.Under the prerequisite of doped chemical horizontal proliferation, the spacing of adjacent sub-pixel diffusion window was designed to 10～30 μ m when the side direction undercutting of diffusion mask and stopped pipe spread when considering out the diffusion window, and spacing is all identical.Stopped pipe diffuses to form sub-pixel PN junction district 7, and PN junction is a shallow junction, and junction depth is greater than thickness 0.1～0.2 μ m of N type InP cap layer, and the not diffusion zone between the sub-pixel PN junction district is as charge carrier side direction collecting region 8.As P electrode 9,, play the effect of annealing barrier layer and passivation layer simultaneously at the two ends of photosensitive unit growth individual layer Au then at the anti-reflection film of chip surface deposit silicon dioxide antireflection layer 10 as chip.Behind the rapid thermal annealing, open the P electrode hole through conventional wet corrosion technique, the Cr that grows successively, Au are as adding thick electrode 11; Adding thick electrode is the annular covering electrode; In enclose size and entire device photosensitive first size be consistent so that photosurface is defined, simultaneously the P electrode of all sub-pixels is drawn and links to each other, chip back polishing back growth individual layer Au is as N electrode 12; At last, with scribing behind the chip gluing.Shown in accompanying drawing 3, concrete chip preparing process steps flow chart is following:
1) epitaxial material cleans, and uses chloroform, ether, acetone, ethanol, washed with de-ionized water epitaxial wafer successively, and nitrogen dries up;
2) deposit silicon nitride diffusion mask, as silicon nitride diffusion mask layer 5, it is the silicon nitride of 230nm that using plasma strengthens the chemical vapor deposition method deposition thickness, underlayer temperature is that 300～330 ℃, RF power are that 40～50W, gas flow are SiH 4: N 2=50mL/min: 900mL/min;
3) positive glue photoetching is adopted in photoetching for the first time, and 50min is toasted in the back of developing on 85 ℃ of hot plates;
4) open sub-pixel diffusion window, adopt buffered hydrofluoric acid solution corroding silicon nitride film to open sub-pixel diffusion window oral region 6, the buffered hydrofluoric acid solution liquor capacity matches well than being HF: NH 4F: H 2O=3: 6: 10, the temperature of buffer solution remained on 0 ℃ during corrosion;
5) photoresist lift off, acetone floats glue, and ethanol cleans, and nitrogen dries up;
6) stopped pipe diffusion forms sub-pixel PN junction district 7 and charge carrier side direction collecting region 8, adopts Powdered Zn 3As 2As diffuse source, vacuum degree is 2～3 * 10 -4Pa, diffusion conditions is: at 300～350 ℃ of 10～12min of following retention time of temperature, under 500～550 ℃ of temperature, keep 6～13min then;
7) open pipe is got sheet, open quartz ampoule epitaxial wafer taken out, and use chloroform successively, ether, acetone, ethanol, washed with de-ionized water epitaxial wafer, nitrogen dries up;
8) positive glue photoetching is adopted in photoetching for the second time, and 30min is toasted in the back of developing on 65 ℃ of hot plates;
9) growth P electrode, as P electrode 9, adopting the ion beam sputtering process deposition thickness is the Au of 50nm, vacuum degree is 2～4 * 10 -2Pa, ion beam energy are 100eV;
10) photoresist lift off, process conditions are identical with step 5);
11) deposit antireflecting silicon dioxide film, as silicon dioxide antireflection layer 10, adopting magnetron sputtering membrane process deposition thickness is the silicon dioxide film of 280nm, and underlayer temperature is 80～100 ℃, and RF power is 350～400W;
12) P electrode annealing, annealing conditions is: nitrogen protection atmosphere, annealing temperature are 450～480 ℃, temperature hold-time is 10～15s;
13) positive glue photoetching is adopted in photoetching for the third time, and 30min is toasted in the back of developing on 85 ℃ of hot plates;
14) open the P electrode hole, adopt buffered hydrofluoric acid solution corrode silicon dioxide film to open the P electrode hole, etching condition is identical with step 4);
15) photoresist lift off, process conditions are identical with step 5);
16) positive glue photoetching is adopted in the 4th photoetching, and 10min is toasted in the back of developing on 65 ℃ of hot plates;
17) thickening P electrode, as adding thick electrode 11, adopt ion beam sputtering process successively deposition thickness be respectively Cr, the Au of 20nm, 400nm, deposition conditions is identical with step 9);
18) photoresist lift off, process conditions are identical with step 5);
19) polished backside, 30min is toasted, material thinning back side 20～30 μ m in front resist coating protection back on 65 ℃ of hot plates;
20) growth N electrode, as N electrode 12, adopting the ion beam sputtering process deposition thickness is the Au of 400nm, deposition conditions is identical with step 9);
21) scribing.
The invention has the advantages that:
A. introduce sub-pixel structure in the plane alignment indium gallium arsenic detector, can effectively reduce the blind element rate, improve filling rate, suppress expansion of photosensitive unit and cross-talk.
The spacing of B. adjacent sub-pixel diffusion window is designed to 10～30 μ m, and the photo-generated carrier that produces charge carrier side direction collecting region can be collected by adjacent sub-pixel effectively, and promptly under the prerequisite that detective quantum efficiency does not reduce, the response of photosensitive unit evenly.
C. reduced the diffusion zone of photosensitive unit, can reduce effectively and spread the diffusion heat damage that brings, and introducing dual layer passivation technology reduces surface recombination, the responsiveness and the detectivity of the life-span of increase minority carrier, the dark current that reduces device, raising detector.
Description of drawings
Fig. 1 is the vertical view of indium gallium arsenic pixel detecting device chip.
Fig. 2 is the cross-sectional view of indium gallium arsenic pixel detecting device chip any two adjacent sub-pixel P electrode contact areas along sub-pixel orientation.
Fig. 3 is the processing step flow chart.
Among the figure:
1---N type InP substrate;
2---N type InP layer;
3---indium gallium arsenic intrinsic absorbed layer;
4---N type InP cap layer;
5---silicon nitride diffusion mask layer;
6---sub-pixel diffusion window oral region;
7---sub-pixel PN junction district;
8---charge carrier side direction collecting region;
9---the P electrode;
10---the silicon dioxide antireflection layer;
11---add thick electrode;
12---the N electrode.
Embodiment
Below in conjunction with accompanying drawing and embodiment practical implementation method of the present invention is done to specify further.
Shown in accompanying drawing 2, the used epitaxial wafer of present embodiment is 300 μ m for adopting metal organic chemical vapor deposition (MOCVD) technology at thickness, carrier concentration＞3 * 10 18Cm -3N type InP substrate 1 on successively growth thickness be the N type InP layer 2 of 0.5 μ m, carrier concentration＞2 * 10 18Cm -3Thickness is the indium gallium arsenic intrinsic absorbed layer 3 of 2.5 μ m, carrier concentration 5 * 10 16Cm -3Thickness is the N type InP cap layer 4 of 1 μ m, carrier concentration 5 * 10 16Cm -3Present embodiment comprises 10 sub-pixel diffusion window oral regions 6 altogether, and each window size is 25 * 500 μ m 2, its spacing is 15 μ m.
The concrete step of preparation process of present embodiment chip is following:
1) use chloroform, ether, acetone, ethanol, washed with de-ionized water epitaxial wafer successively, nitrogen dries up then;
2) using plasma strengthens the silicon nitride diffusion mask layer 5 that the chemical vapor deposition method deposition thickness is 230nm, and underlayer temperature is that 330 ℃, RF power are 50W, gas flow SiH 4: N 2=50mL/min: 900mL/min;
3) positive glue photoetching is adopted in photoetching for the first time, and 50min is toasted in the back of developing on 85 ℃ of hot plates;
4) adopt buffered hydrofluoric acid solution at 0 ℃ of following corroding silicon nitride diffusion mask, the buffered hydrofluoric acid solution liquor capacity matches well than being HF: NH 4F: H 2O=3: 6: 10, deionized water rinsing, nitrogen dries up, and forms sub-pixel diffusion window oral region 6;
5) photoresist lift off, acetone floats glue, and ethanol cleans, and nitrogen dries up;
6) adopt Powdered Zn 3As 2Carry out the stopped pipe diffusion as diffuse source, vacuum degree is 2.4 * 10 -4Pa at 350 ℃ of 10min of following retention time of temperature, keeps 6min then under 550 ℃ of temperature, become sub-pixel PN junction district 7 and charge carrier side direction collecting region 8;
7) open quartz ampoule epitaxial wafer taken out, and use chloroform successively, ether, acetone, ethanol, washed with de-ionized water epitaxial wafer, nitrogen dries up;
8) positive glue photoetching is adopted in photoetching for the second time, and 30min is toasted in the back of developing on 65 ℃ of hot plates;
9) Au that adopts ion beam sputtering process deposition thickness 50nm is as P electrode 9, and vacuum degree is 3 * 10 -2Pa, ion beam energy are 100eV;
10) photoresist lift off, process conditions are identical with step 5);
11) adopting magnetron sputtering membrane process deposition thickness is the silicon dioxide antireflection layer 10 of 280nm, and underlayer temperature is 80 ℃, and RF power is 350～400W;
12) under nitrogen protection atmosphere, carry out rapid thermal annealing, temperature is 450 ℃, and the retention time is 10s;
13) positive glue photoetching is adopted in photoetching for the third time, and 50min is toasted in the back of developing on 85 ℃ of hot plates;
14) adopt buffered hydrofluoric acid solution to open the P electrode hole at 0 ℃ of following corrode silicon dioxide antireflection layer, etching condition is identical with step 4);
15) photoresist lift off, process conditions are identical with step 5);
16) positive glue photoetching is adopted in the 4th photoetching, and 10min is toasted in the back of developing on 65 ℃ of hot plates;
17) adopt ion beam sputtering successively deposition thickness be respectively 20nm, 400nm Cr, Au as adding thick electrode 11, deposition conditions is identical with step 9);
18) photoresist lift off, process conditions are identical with step 5);
19) 30min is toasted in resist coating protection back in front on 65 ℃ of hot plates, polished backside then, material thinning back side 20～30 μ m;
20) adopt ion beam sputter deposition thickness be the Au of 400nm as N electrode 12, deposition conditions is identical with step 9);
21) use acetone, ethanol, deionized water to clean successively after the scribing, nitrogen dries up, and sub-pixel structure devices is made and finished, and sees accompanying drawing 2, and its vertical view is shown in accompanying drawing 1.

Claims (1)

1. the sub-pixel structure of plane indium-gallium-arsenide infrared detector chip preparation method, step comprises: 1) epitaxial material cleans, 2) deposit silicon nitride diffusion mask, 3) photoetching for the first time, 4) open sub-pixel diffusion window; 5) photoresist lift off, 6) stopped pipe diffusion, 7) open pipe is got sheet, 8) photoetching for the second time, 9) growth P electrode; 10) photoresist lift off, 11) deposit antireflecting silicon dioxide film, 12) P electrode annealing, 13) photoetching for the third time, 14) open the P electrode hole; 15) photoresist lift off, 16) the 4th photoetching, 17) thickening P electrode, 18) photoresist lift off; 19) polished backside, 20) growth N electrode, 21) scribing, it is characterized in that:
A. described step 2) deposit silicon nitride diffusion mask, using plasma strengthen the chemical vapor deposition method growth, and growth conditions is: underlayer temperature is that 300～330 ℃, RF power are 40～50W, gas flow SiH 4: N 2=50mL/min: 900mL/min;
B. Powdered Zn is adopted in described step 6) stopped pipe diffusion 3As 2As diffuse source, vacuum degree is 2～3 * 10 -4Pa, diffusion conditions is: at 300～350 ℃ of 10～12min of following retention time of temperature, under 500～550 ℃ of temperature, keep 6～13min then;
C. described step 9) growth P electrode, step 17) thickening P electrode, step 20) growth N electrode all adopts the ion beam sputtering process growth, is respectively individual layer Au, double-deck Cr/Au, individual layer Au, and growth conditions is: vacuum degree is 2～4 * 10 -2Pa, ion beam energy are 100eV;
D. described step 11) deposit antireflecting silicon dioxide film adopts the growth of magnetron sputtering membrane process, and growth conditions is: underlayer temperature is 80～100 ℃, and RF power is 350～400W;
E. described step 12) P electrode annealing, in nitrogen protection atmosphere, annealing temperature is 450～480 ℃, temperature hold-time is 10～15s.
CN2012100191141A 2012-01-20 2012-01-20 Method for preparing sub-pixel structured planar InGaAs infrared detector chip Pending CN102544222A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106409939A (en) * 2016-11-14 2017-02-15 南通大学 Preparation method of planar lateral collection structure InGaAs infrared detector chip

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101170142A (en) * 2007-11-21 2008-04-30 中国科学院上海技术物理研究所 Plane indium and gallium infrared focusing plane detector and its making method

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101170142A (en) * 2007-11-21 2008-04-30 中国科学院上海技术物理研究所 Plane indium and gallium infrared focusing plane detector and its making method

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
杨集等: "InP/InGaAs PIN红外探测器增透膜的研究", 《半导体技术》 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106409939A (en) * 2016-11-14 2017-02-15 南通大学 Preparation method of planar lateral collection structure InGaAs infrared detector chip
CN106409939B (en) * 2016-11-14 2018-05-15 南通大学 The preparation method of plane lateral collection structure indium-gallium-arsenide infrared detector chip

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Application publication date: 20120704