CN102543921A - 焊垫结构及其制造方法 - Google Patents
焊垫结构及其制造方法 Download PDFInfo
- Publication number
- CN102543921A CN102543921A CN2010106102570A CN201010610257A CN102543921A CN 102543921 A CN102543921 A CN 102543921A CN 2010106102570 A CN2010106102570 A CN 2010106102570A CN 201010610257 A CN201010610257 A CN 201010610257A CN 102543921 A CN102543921 A CN 102543921A
- Authority
- CN
- China
- Prior art keywords
- passivation layer
- bed course
- metal welding
- metal
- welding pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000003466 welding Methods 0.000 title claims abstract description 45
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 238000002161 passivation Methods 0.000 claims abstract description 96
- 238000004021 metal welding Methods 0.000 claims abstract description 89
- 238000005530 etching Methods 0.000 claims abstract description 43
- 238000013459 approach Methods 0.000 claims description 11
- 229910052782 aluminium Inorganic materials 0.000 claims description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 9
- 238000000034 method Methods 0.000 abstract description 23
- 229910052751 metal Inorganic materials 0.000 abstract description 9
- 239000002184 metal Substances 0.000 abstract description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000005538 encapsulation Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 241000218202 Coptis Species 0.000 description 3
- 235000002991 Coptis groenlandica Nutrition 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 239000000428 dust Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000035882 stress Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0501—Shape
- H01L2224/05016—Shape in side view
- H01L2224/05017—Shape in side view comprising protrusions or indentations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05558—Shape in side view conformal layer on a patterned surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4845—Details of ball bonds
- H01L2224/48451—Shape
- H01L2224/48453—Shape of the interface with the bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (6)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201010610257.0A CN102543921B (zh) | 2010-12-23 | 2010-12-23 | 焊垫结构及其制造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201010610257.0A CN102543921B (zh) | 2010-12-23 | 2010-12-23 | 焊垫结构及其制造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN102543921A true CN102543921A (zh) | 2012-07-04 |
CN102543921B CN102543921B (zh) | 2015-01-07 |
Family
ID=46350443
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201010610257.0A Active CN102543921B (zh) | 2010-12-23 | 2010-12-23 | 焊垫结构及其制造方法 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN102543921B (zh) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105575829A (zh) * | 2014-10-16 | 2016-05-11 | 中芯国际集成电路制造(上海)有限公司 | 一种提高焊垫与金属线球之间键合能力的方法及结构 |
CN110223922A (zh) * | 2019-06-10 | 2019-09-10 | 武汉新芯集成电路制造有限公司 | 一种晶圆结构及其制造方法、芯片结构 |
CN112992830A (zh) * | 2019-12-02 | 2021-06-18 | 长鑫存储技术有限公司 | 半导体结构及其制备方法 |
CN115274613A (zh) * | 2021-04-30 | 2022-11-01 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW437030B (en) * | 2000-02-03 | 2001-05-28 | Taiwan Semiconductor Mfg | Bonding pad structure and method for making the same |
US20020111009A1 (en) * | 2001-02-15 | 2002-08-15 | Megic Corporation | Reliable metal bumps on top of I/O pads after removal of test probe marks |
CN1941341A (zh) * | 2005-09-21 | 2007-04-04 | 艾格瑞系统有限公司 | 用于代替互连层的焊盘下的通路 |
-
2010
- 2010-12-23 CN CN201010610257.0A patent/CN102543921B/zh active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW437030B (en) * | 2000-02-03 | 2001-05-28 | Taiwan Semiconductor Mfg | Bonding pad structure and method for making the same |
US20020111009A1 (en) * | 2001-02-15 | 2002-08-15 | Megic Corporation | Reliable metal bumps on top of I/O pads after removal of test probe marks |
CN1941341A (zh) * | 2005-09-21 | 2007-04-04 | 艾格瑞系统有限公司 | 用于代替互连层的焊盘下的通路 |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105575829A (zh) * | 2014-10-16 | 2016-05-11 | 中芯国际集成电路制造(上海)有限公司 | 一种提高焊垫与金属线球之间键合能力的方法及结构 |
CN110223922A (zh) * | 2019-06-10 | 2019-09-10 | 武汉新芯集成电路制造有限公司 | 一种晶圆结构及其制造方法、芯片结构 |
US11164834B2 (en) | 2019-06-10 | 2021-11-02 | Wuhan Xinxin Semiconductor Manufacturing Co., Ltd. | Wafer structure and method for manufacturing the same, and chip structure |
CN112992830A (zh) * | 2019-12-02 | 2021-06-18 | 长鑫存储技术有限公司 | 半导体结构及其制备方法 |
CN115274613A (zh) * | 2021-04-30 | 2022-11-01 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
CN115274613B (zh) * | 2021-04-30 | 2024-09-24 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
Also Published As
Publication number | Publication date |
---|---|
CN102543921B (zh) | 2015-01-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN100539054C (zh) | 芯片封装结构及其制作方法 | |
CN101252096B (zh) | 芯片封装结构以及其制作方法 | |
CN104350586B (zh) | 半导体装置 | |
US6242283B1 (en) | Wafer level packaging process of semiconductor | |
CN104319269B (zh) | 多级引线框架 | |
CN102543921B (zh) | 焊垫结构及其制造方法 | |
US9059004B2 (en) | Method for chip scale package and package structure thereof | |
CN103050466B (zh) | 半导体封装件及其制法 | |
CN101114600A (zh) | 防止焊垫剥离的制造方法以及防止焊垫剥离的结构 | |
TW201640635A (zh) | 封裝結構及其製作方法 | |
CN100390983C (zh) | 芯片封装体 | |
JP2007150144A (ja) | 半導体装置およびその製造方法 | |
CN103137498B (zh) | 半导体封装结构及其制作方法 | |
CN213660390U (zh) | 一种封装结构及封装芯片 | |
US9159660B2 (en) | Semiconductor package structure and method for making the same | |
CN103107145A (zh) | 半导体封装件、预制导线架及其制法 | |
TWI559470B (zh) | 無基板的半導體封裝結構及其製造方法 | |
US20080136027A1 (en) | Method of bonding wire of semiconductor package | |
US8168526B2 (en) | Semiconductor chip package and method for manufacturing thereof | |
JP5382889B2 (ja) | パッケージ構造の製造方法 | |
US20200243431A1 (en) | Structure for packaging and method for manufacturing the same | |
TWI582903B (zh) | 半導體封裝結構及其製作方法 | |
CN112736052A (zh) | 一种封装结构及其制备方法、封装芯片 | |
CN105449069B (zh) | 一种倒装led芯片结构及其制造方法 | |
CN100416810C (zh) | 半导体元件及其制造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CP03 | Change of name, title or address | ||
CP03 | Change of name, title or address |
Address after: 201203 No. 18 Zhangjiang Road, Shanghai Patentee after: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) Corp. Country or region after: China Patentee after: Wuhan Xinxin Integrated Circuit Co.,Ltd. Address before: 201203 No. 18 Zhangjiang Road, Shanghai Patentee before: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) Corp. Country or region before: China Patentee before: Wuhan Xinxin Semiconductor Manufacturing Co.,Ltd. |