CN102543819B - A kind of method taking precautions against STI-CMP scuffing - Google Patents
A kind of method taking precautions against STI-CMP scuffing Download PDFInfo
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- CN102543819B CN102543819B CN201010578016.2A CN201010578016A CN102543819B CN 102543819 B CN102543819 B CN 102543819B CN 201010578016 A CN201010578016 A CN 201010578016A CN 102543819 B CN102543819 B CN 102543819B
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- cmp
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- wedge angle
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Abstract
The present invention provides a kind of and takes precautions against the method that STI CMP scratches, and including step: the first step, is ground off by the HDP OX (high-density plasma silicon oxide) of wafer surfaces of active regions, and at this time wafer surface can form the wedge angle outwelled；Second step, carries out the grinding of SiN and SiN grinds off certain thickness, adds the wedge angle that high-pressure wash step drops to removing, thus prevent wafer surface from scratching between the first step and second step.Compared with prior art, high-pressure wash step can wash away the wedge angle outwelled in time, reaches to clean the effect of wafer surface, thus prevents STI CMP to scratch.
Description
[technical field]
The present invention relates to production process of semiconductor technical field, the STI-CMP particularly relating to a kind of improvement is (shallow
Trench isolations planarizes) method.
[background technology]
STI (shallow trench isolation) has become the key technology of isolation between device at present, and replaces
LOCOS (local oxidation of silicon) technology.Its key step is included on pure silicon sheet etching shallow trench, carries out
Silica deposit, finally carry out surface planarisation by CMP (chemically mechanical polishing) technology.CMP (chemistry
Mechanical polishing) technique introduced IC manufacturing industry by IBM in 1984, and was first utilized in postchannel process
The planarization of IMD (dielectric between metal), then by equipment and the planarization being modified to tungsten of technique,
It is used subsequently to the planarization of STI and copper.CMP grows up the soonest in IC processing procedure in recent years, the most valued one
Item technology.It is primarily due to super large-scale integration and produces along with continuous tinyization of live width flat
The tight demand of smoothization.The process goal of STI-CMP is to grind off the institute's aerobic than SiN (silicon nitride) floor height
Changing layer, the technique otherwise carried out after STI polishing cannot peel off SiN with hot phosphoric acid, thus realize planarization.
The most traditional STI-CMP is carried out generally according to following two steps: the first step is by active area
HDP-OX (high-density plasma silicon oxide) grinds off, and second step is that the SiN of active area is ground off appointment
Thickness (such as 400A), and this two step is carried out continuously, as shown in Figure 1.But, in quasiconductor system
Making in flow process, also have the precipitation process of a HDP-OX before STI-CMP operation, this step can complete STI
The filling of groove, but wedge angle can be formed in surfaces of active regions after filling.Therefore when STI-CMP grinds
Wait and likely form wafer surface scuffing because the wedge angle of surface bulk outwells, and due to STI-CMP's
Process of lapping is carried out continuously, and the bulk wedge angle outwelled is present in the middle of wafer and grinding pad, it is impossible to by clearly
Remove, so being readily formed scuffing after Yan Moing.
In order to solve the problems referred to above, the STI-CMP method of a kind of improvement of necessary offer.
[summary of the invention]
For the deficiencies in the prior art, present invention solves the technical problem that the STI-CMP being to provide a kind of improvement
Method, it can take precautions against and alleviate the scuffing to wafer surface of the wedge angle of HDP-OX formation.
The purpose of the present invention realizes by providing techniques below scheme:
A kind of method taking precautions against STI-CMP scuffing, including step: the first step, by wafer surfaces of active regions
HDP-OX (high-density plasma silicon oxide) grind off, at this time wafer surface can form the point outwelled
Angle；Second step, carries out the grinding of SiN and SiN grinds off certain thickness, the first step and second step it
Between add high-pressure wash step with the wedge angle that drops to of removing, thus prevent wafer surface from scratching.
Further, the scuffing that wafer surface can accidentally be formed by the grinding of SiN is removed.
Yet further, the certain thickness described in the grinding steps of SiN is 400A.
Yet further, described first step, second step and high-pressure wash step between the two are even
Continuous carry out.
Further, the wedge angle outwelled described in is HDP-OX (high-density plasma silicon oxide).
Compared with prior art, the invention has the beneficial effects as follows: high-pressure wash step can wash away in time outwells
Wedge angle, reach to clean the effect of wafer surface, thus prevent STI-CMP to scratch.
[accompanying drawing explanation]
The invention will be further described below in conjunction with the accompanying drawings:
Fig. 1 is the flow chart of the STI-CMP of prior art.
Fig. 2 is the flow chart that the present invention takes precautions against the method that STI-CMP scratches.
[detailed description of the invention]
The preferred forms of the present invention is described referring to the drawings.
As in figure 2 it is shown, the present invention provides a kind of STI-CMP's of strick precaution (shallow trench isolation planarization scratches)
Method.In semiconductor manufacture flow path, before STI-CMP operation, also have a HDP-OX (high density etc.
Gas ions silicon oxide) precipitation process, this step can complete the filling of sti trench groove, but at crystalline substance after filling
The surfaces of active regions of sheet can form wedge angle.First step of the present invention is by wafer surfaces of active regions
HDP-OX grinds off, and at this time the wedge angle of wafer surfaces of active regions will be outwelled, and the most also can form other secondary
Product.These wedge angles outwelled and by-product are between wafer surface and grinding pad, if clearing up not in time,
The scuffing of wafer surface will be caused in ensuing process of lapping.And the present invention is just first step
Complete to be provided with a high-pressure wash step afterwards, will be by by high-pressure wash, the wedge angle outwelled and by-product
Washing away, wafer surface is also cleaned.Subsequently, it will carry out the grinding steps of SiN, and according to appointment
Thickness be persistently ground, scuffing that wafer surface can accidentally be formed by this step weakens and even removes,
Now, the thickness that SiN is worn away is typically at 400A.It is pointed out that above-mentioned steps is carried out continuously.
Compared with prior art, the invention has the beneficial effects as follows: high-pressure wash step can wash away in time outwells
Wedge angle and other by-products, reach to clean the effect of wafer surface, thus prevent STI-CMP to scratch.
Although being example purpose, having been disclosed for the preferred embodiment of the present invention, but this area is common
Skilled artisan will appreciate that, without departing from by scope and spirit of the present invention disclosed in appending claims
In the case of, various improvement, to increase and replace be possible.
Claims (4)
1. take precautions against the method that STI-CMP scratches, including step: the first step, by the HDP-OX of wafer surfaces of active regions
(high-density plasma silicon oxide) grinds off, and at this time wafer surface can form the wedge angle outwelled；Second step, carries out SiN
Grinding and SiN is ground off the thickness of 400 angstroms, it is characterised in that: between the first step and second step, add high-pressure wash step
Suddenly the wedge angle dropped to removing, thus prevent wafer surface from scratching.
The method that strick precaution STI-CMP the most according to claim 1 scratches, it is characterised in that: the grinding of SiN can be by
The scuffing that wafer surface is accidentally formed is removed.
The method that strick precaution STI-CMP the most according to claim 1 and 2 scratches, it is characterised in that: described first step,
Second step and high-pressure wash step between the two are carried out continuously.
The method that strick precaution STI-CMP the most according to claim 3 scratches, it is characterised in that the wedge angle outwelled described in:
It is HDP-OX (high-density plasma silicon oxide).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010578016.2A CN102543819B (en) | 2010-12-08 | 2010-12-08 | A kind of method taking precautions against STI-CMP scuffing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010578016.2A CN102543819B (en) | 2010-12-08 | 2010-12-08 | A kind of method taking precautions against STI-CMP scuffing |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102543819A CN102543819A (en) | 2012-07-04 |
| CN102543819B true CN102543819B (en) | 2016-08-17 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201010578016.2A Active CN102543819B (en) | 2010-12-08 | 2010-12-08 | A kind of method taking precautions against STI-CMP scuffing |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6261158B1 (en) * | 1998-12-16 | 2001-07-17 | Speedfam-Ipec | Multi-step chemical mechanical polishing |
| US7300877B2 (en) * | 2004-01-13 | 2007-11-27 | Nec Electronics Corporation | Method of manufacturing a semiconductor device |
| CN101425477A (en) * | 2007-10-29 | 2009-05-06 | 联华电子股份有限公司 | Forming method of shallow groove isolation and grinding method of semiconductor structure |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020187595A1 (en) * | 1999-08-04 | 2002-12-12 | Silicon Evolution, Inc. | Methods for silicon-on-insulator (SOI) manufacturing with improved control and site thickness variations and improved bonding interface quality |
| JP2009206141A (en) * | 2008-02-26 | 2009-09-10 | Fujitsu Microelectronics Ltd | Manufacturing method of semiconductor device |
-
2010
- 2010-12-08 CN CN201010578016.2A patent/CN102543819B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6261158B1 (en) * | 1998-12-16 | 2001-07-17 | Speedfam-Ipec | Multi-step chemical mechanical polishing |
| US7300877B2 (en) * | 2004-01-13 | 2007-11-27 | Nec Electronics Corporation | Method of manufacturing a semiconductor device |
| CN101425477A (en) * | 2007-10-29 | 2009-05-06 | 联华电子股份有限公司 | Forming method of shallow groove isolation and grinding method of semiconductor structure |
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| Publication number | Publication date |
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| CN102543819A (en) | 2012-07-04 |
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