CN102543703A - Manufacturing method of nanocrystalline flash memory grid - Google Patents
Manufacturing method of nanocrystalline flash memory grid Download PDFInfo
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- CN102543703A CN102543703A CN2010106203088A CN201010620308A CN102543703A CN 102543703 A CN102543703 A CN 102543703A CN 2010106203088 A CN2010106203088 A CN 2010106203088A CN 201010620308 A CN201010620308 A CN 201010620308A CN 102543703 A CN102543703 A CN 102543703A
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- flash memory
- nanocrystalline
- silicide layer
- metal silicide
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Abstract
The invention provides a manufacturing method of a nanocrystalline flash memory grid. The method comprises the following steps of: providing a silicon substrate; depositing a tunneling oxide layer on the silicon substrate; depositing a metal silicide layer on the tunneling oxide layer; depositing a barrier layer on the metal silicide layer; performing a fluorine ion injection process on the metal silicide layer; performing a quick thermal annealing process in an oxygen environment to transform the metal silicide layer into a floating gate, wherein the floating gate comprises an insulating medium and metal nanocrystalline isolated by the insulating medium; and forming a control gate on the barrier layer. According to the manufacturing method of the nanocrystalline flash memory grid provided by the invention, the formed metal nanocrystalline is isolated effectively, the metal nanocrystalline is distributed uniformly, and the charge capturing and storing capabilities of the floating gate are enhanced; and furthermore, the erasing voltage of the grid is reduced, and the reliability of the nanocrystalline flash memory grid is enhanced.
Description
Technical field
The present invention relates to integrated circuit fabrication process, particularly a kind of manufacturing approach of nanocrystalline flash memory grid electrode.
Background technology
In more than ten years in the past, the market of flash memory (Flash) rapidly enlarges, and the flash memory size constantly reduces, and device just develops towards the direction of high speed, low-power consumption and high storage density, to satisfy the demand in market.This physical size that will seek quickness the flash memory unit further dwindles.Flash memory in the market adopts continuous multi-crystal silicon floating bar to come stored charge mostly.Yet along with the device size of flash memory constantly reduces, the tunnel oxide that is formed on the silicon substrate also needs further attenuate.Trapped charges is easy to turn back in the substrate through tunnel oxide in floating boom with regard to causing for this, thereby the data hold capacity of device is degenerated, and can't satisfy requirement of actual application.
In order to address the above problem, one of method is to adopt discrete electric charge memory technology, promptly nanocrystalline charge storage technology.Because be insulated dielectric isolation between nanocrystalline, charge stored can not move freely, thereby solved the problems that cause electric charge to run off in a large number because of local defective in the continuous floating boom between nanocrystalline, so improve the holding time of electric charge greatly.
Please refer to Figure 1A～1F, it is the sketch map of the manufacturing approach of existing nanocrystalline flash memory grid electrode.
At first, shown in Figure 1A, a silicon substrate 10 is provided;
Secondly, shown in Figure 1B, deposition one tunnel oxide 11 on said silicon substrate 10;
Once more, shown in Fig. 1 C, deposition one metal silicide layer 12 on said tunnel oxide 11;
Then, shown in Fig. 1 D, deposition one barrier layer 13 on said metal silicide layer 12;
Then, shown in Fig. 1 E, in oxygen atmosphere, carry out rapid thermal anneal process, make said metal silicide layer 12 be transformed into to contain the floating boom 16 that is insulated the metallic nano crystal 15 that medium 14 isolates;
At last, shown in Fig. 1 F, on said barrier layer 13, form control grid 17, thus, just obtained the grid 1 of nanocrystalline flash memory.
But the grid 1 of the nanocrystalline flash memory that the manufacturing approach through existing nanocrystalline flash memory grid electrode obtains wherein, plays the skewness of the metallic nano crystal 15 of electric charge capture and memory action.Please refer to Fig. 1 E and 1F body shows as and is not insulated medium 14 between each metallic nano crystal 15 and keeps apart one by one; Thus; Charge stored will move freely between the metallic nano crystal that is connecting 15, reduce the electric charge capture and the storage capacity of floating boom 16, further; Improve the erasable voltage of grid 1, reduced the reliability of the grid 1 of nanocrystalline flash memory.
The research and analysis of process inventor's theory and practice are found; Causing not being insulated between each metallic nano crystal 15 reason that medium 14 keeps apart one by one is: in oxygen atmosphere, carry out rapid thermal anneal process; Make said metal silicide layer 12 be transformed into to contain in the process of the floating boom 16 that is insulated the metallic nano crystal 15 that medium 14 isolates; Oxygen atom can not form reaction fast and effectively with the silicon in the metal silicide, can't combine to generate enough silicon dioxide (SiO
2), thereby with keeping apart one by one between each metallic nano crystal 15.
Summary of the invention
The object of the present invention is to provide a kind of manufacturing approach of nanocrystalline flash memory grid electrode; In order to metallic nano crystal skewness in the manufacturing approach that solves existing nanocrystalline flash memory grid electrode, thereby the electric charge capture of floating boom and the problem of storage capacity have been reduced.
For solving the problems of the technologies described above, the present invention provides a kind of manufacturing approach of nanocrystalline flash memory grid electrode, comprising: a silicon substrate is provided; Deposition one tunnel oxide on said silicon substrate; Deposition one metal silicide layer on said tunnel oxide; Deposition one barrier layer on said metal silicide layer; Said metal silicide layer is carried out the fluorine ion injection technology; In oxygen atmosphere, carry out rapid thermal anneal process, make said metal silicide layer be transformed into floating boom, the metallic nano crystal that said floating boom comprises dielectric and is insulated dielectric isolation; On said barrier layer, form control grid.
Optional, on said silicon substrate, before formation one tunnel oxide, said silicon substrate is carried out cleaning surfaces handle.
Optional, the technology that on said silicon substrate, forms a tunnel oxide comprises: deposit a silicide layer; Carry out first rapid thermal anneal process.
Optional, the thickness of said silicide layer is 30 dusts～150 dusts.
Optional, the annealing temperature of said first rapid thermal anneal process is 1000 ℃～1200 ℃.
Optional, the thickness of said metal silicide layer is 40 dusts～150 dusts.
Optional, the thickness on said barrier layer is 20 dusts～120 dusts, material is an amorphous silicon.
Optional, the injection rate of said fluorine ion is 10
13Cm
-3～10
15Cm
-3
Optional, the annealing temperature of said rapid thermal anneal process is 800 ℃～1000 ℃.
Optional, the thickness of said control grid is 600 dusts～1200 dusts, material is a polysilicon.
The manufacturing approach of nanocrystalline flash memory grid electrode provided by the invention carries out having increased the step of said metal silicide layer being carried out the fluorine ion injection technology before the rapid thermal anneal process in oxygen atmosphere; Because fluorine atom can form reaction fast and effectively with silicon in the metal silicide layer, combine generation fluorine chemistry of silicones key, and follow-up when in oxygen atmosphere, carrying out rapid thermal anneal process; Oxygen atom very easily replaces the fluorine in the fluorine chemistry of silicones key; Combine to generate enough silicon dioxide with silicon, thereby effectively the metallic nano crystal that forms is separated, make metallic nano crystal be evenly distributed; Thereby the electric charge capture and the storage capacity of floating boom have been improved; Further, reduce the erasable voltage of grid, improved the reliability of the grid of nanocrystalline flash memory.
Description of drawings
Figure 1A～1F is the sketch map of the manufacturing approach of existing nanocrystalline flash memory grid electrode;
Fig. 2 is the flow chart of manufacturing approach of the nanocrystalline flash memory grid electrode of the embodiment of the invention;
Fig. 3 A～3G is the sketch map of manufacturing approach of the nanocrystalline flash memory grid electrode of the embodiment of the invention.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment the manufacturing approach of the nanocrystalline flash memory grid electrode of the present invention's proposition is done further explain.According to following explanation and claims, advantage of the present invention and characteristic will be clearer.What need explanation is, accompanying drawing all adopts the form of simplifying very much and all uses non-ratio accurately, only in order to convenient, the purpose of the aid illustration embodiment of the invention lucidly.
Core concept of the present invention is, a kind of manufacturing approach of nanocrystalline flash memory grid electrode is provided, and in oxygen atmosphere, carries out before the rapid thermal anneal process; Increased the step of said metal silicide layer being carried out the fluorine ion injection technology, because fluorine atom can form reaction fast and effectively with the silicon in the metal silicide layer, in conjunction with producing fluorine chemistry of silicones key; And follow-up when in oxygen atmosphere, carrying out rapid thermal anneal process, oxygen atom very easily replaces the fluorine in the fluorine chemistry of silicones key, combines to generate enough silicon dioxide with silicon; Thereby effectively the metallic nano crystal that forms is separated; Make metallic nano crystal be evenly distributed, thereby improved the electric charge capture and the storage capacity of floating boom, further; Reduce the erasable voltage of grid, improved the reliability of the grid of nanocrystalline flash memory.
Please refer to Fig. 2 and Fig. 3 A～3G, wherein, Fig. 2 is the flow chart of manufacturing approach of the nanocrystalline flash memory grid electrode of the embodiment of the invention, and Fig. 3 A～3G is the sketch map of manufacturing approach of the nanocrystalline flash memory grid electrode of the embodiment of the invention.In conjunction with this Fig. 2 and Fig. 3 A～3G, this method may further comprise the steps:
At first, execution in step S20 provides a silicon substrate.Specifically shown in Fig. 3 A, a silicon substrate 20 is provided, in the present embodiment, the material of said silicon substrate 20 is a polysilicon.
Secondly, execution in step S21, deposition one tunnel oxide on said silicon substrate.Shown in Fig. 3 B, deposition one tunnel oxide 21 on silicon substrate 20.
Further, on said silicon substrate 20, before formation one tunnel oxide 21, can carry out cleaning surfaces to silicon substrate 20 and handle.Handle through said silicon substrate 20 being carried out cleaning surfaces, can improve the adhesion between tunnel oxide 21 and the silicon substrate 20, further improve the reliability of nanocrystalline flash memory grid electrode.
Further, the technology of deposition one tunnel oxide 21 may further comprise the steps on said silicon substrate 20: at first, deposit a silicide layer; Then, carry out first rapid thermal anneal process.
In the present embodiment, the material of said silicide layer is a silicon dioxide, and the thickness of said silicide layer is 30 dusts～150 dusts.The main purpose of deposition tunnel oxide 21 is to prevent that trapped charges turns back in the substrate in the floating boom, and therefore, the thickness of said silicide layer can be thicker; Perhaps, in order to satisfy the requirement that the flash memory size reduces, also suitably attenuate some.
In the present embodiment, the annealing temperature of said first rapid thermal anneal process is 1000 ℃～1200 ℃.Through carrying out first rapid thermal anneal process, can improve the density of tunnel oxide.
Once more, execution in step S22, deposition one metal silicide layer on said tunnel oxide.Shown in Fig. 3 C, deposition one metal silicide layer 22 on tunnel oxide 21, concrete, said metal silicide layer 22 can be tungsten silicide, germanium silicide etc.Further, said metal silicide layer 22 can form through the mode of low-pressure chemical vapor deposition (LPCVD).In the present embodiment, the thickness of said metal silicide layer is 40 dusts～150 dusts.The thickness of said metal silicide layer is relevant with follow-up formation metallic nano crystal quantity, i.e. the thicker of metal silicide layer, and the quantity that forms metallic nano crystal is many more, thereby has finally improved the electric charge capture and the storage capacity of grid.Therefore, the thickness of said metal silicide layer also can be according to the electric charge capture ability of grid and the dimensional requirement of storage capacity and grid are carried out the adjustment beyond above-mentioned scope.
Then, execution in step S23, deposition one barrier layer on said metal silicide layer.Shown in Fig. 3 D, deposition one barrier layer 23 on metal silicide layer 22.The effect of protection metal silicide layer 22 also can be played in said barrier layer 23 except the floating boom and control grid that can isolate follow-up formation, prevent that the material in metal silicide layer 22 and the environment from reacting, thereby improve product reliability.In the present embodiment, the thickness on said barrier layer 23 is 20 dusts～120 dusts, and material is an amorphous silicon.
Then, execution in step S24 carries out the fluorine ion injection technology to said metal silicide layer.Shown in Fig. 3 E, metal silicide layer 22 is carried out the fluorine ion injection technology.Because fluorine atom can form reaction fast and effectively with the silicon in the metal silicide layer 22; In conjunction with producing fluorine chemistry of silicones key, and follow-up when in oxygen atmosphere, carrying out rapid thermal anneal process when carrying out, oxygen atom very easily replaces the fluorine in the fluorine chemistry of silicones key; Combine to generate enough silicon dioxide with silicon; Thereby effectively the metallic nano crystal that forms is separated, make metallic nano crystal be evenly distributed, thereby improved the electric charge capture and the storage capacity of floating boom.In the present embodiment, the injection rate of said fluorine ion for example is 10
13Cm
-3～10
15Cm
-3
Execution in step S25 carries out rapid thermal anneal process in oxygen atmosphere, make said metal silicide layer be transformed into floating boom, the metallic nano crystal that said floating boom comprises dielectric and is insulated dielectric isolation.Shown in Fig. 3 F, carry out rapid thermal anneal process through carrying out in the oxygen atmosphere, make metal silicide layer 22 change floating boom 26, said floating boom 26 comprises the metallic nano crystal 25 that is insulated medium 24 and is insulated medium 24 isolation.In the present embodiment, the annealing temperature of said rapid thermal anneal process is 800 ℃～1000 ℃, and the material of said dielectric 24 is a silicon dioxide.After said metal silicide layer 22 carried out the fluorine ion injection technology; In oxygen atmosphere, carry out rapid thermal anneal process; Obtained being insulated the metallic nano crystal 25 that medium 24 effectively separates; Thereby make metallic nano crystal 25 be evenly distributed, further, improved the electric charge capture and the storage capacity of floating boom 26.
Draw through experimental data, metal silicide layer is not carried out the fluorine ion injection technology, and directly in oxygen atmosphere, carry out under the situation of rapid thermal anneal process, the separation rate of the metallic nano crystal that obtains is 40%～50%; And utilize the method for the embodiment of the invention; Promptly; After metal silicide layer 22 carried out the fluorine ion injection technology, in oxygen atmosphere, carry out rapid thermal anneal process again, the separation rate of the metallic nano crystal that obtains is 75%～85%; Thus, the electric charge capture and the storage capacity of formed floating boom 26 have been improved greatly.
At last, execution in step S26 forms control grid on said barrier layer.Shown in Fig. 3 G, on barrier layer 23, form control grid 27, thereby obtain the grid 1 of nanocrystalline flash memory.In the present embodiment, said control grid 27 can be through depositing the polysilicon layer formation that a thickness is 600 dusts～1200 dusts.
Foregoing description only is the description to preferred embodiment of the present invention, is not any qualification to the scope of the invention, and any change, modification that the those of ordinary skill in field of the present invention is done according to above-mentioned disclosure all belong to the protection range of claims.
Claims (10)
1. the manufacturing approach of a nanocrystalline flash memory grid electrode is characterized in that, comprising:
One silicon substrate is provided;
Deposition one tunnel oxide on said silicon substrate;
Deposition one metal silicide layer on said tunnel oxide;
Deposition one barrier layer on said metal silicide layer;
Said metal silicide layer is carried out the fluorine ion injection technology;
In oxygen atmosphere, carry out rapid thermal anneal process, make said metal silicide layer be transformed into floating boom, the metallic nano crystal that said floating boom comprises dielectric and is insulated dielectric isolation;
On said barrier layer, form control grid.
2. the manufacturing approach of nanocrystalline flash memory grid electrode as claimed in claim 1 is characterized in that, on said silicon substrate, before formation one tunnel oxide, said silicon substrate is carried out cleaning surfaces handle.
3. the manufacturing approach of nanocrystalline flash memory grid electrode as claimed in claim 1 is characterized in that, the technology that on said silicon substrate, forms a tunnel oxide comprises:
Deposit a silicide layer;
Carry out first rapid thermal anneal process.
4. the manufacturing approach of nanocrystalline flash memory grid electrode as claimed in claim 3 is characterized in that, the thickness of said silicide layer is 30 dusts～150 dusts.
5. the manufacturing approach of nanocrystalline flash memory grid electrode as claimed in claim 3 is characterized in that, the annealing temperature of said first rapid thermal anneal process is 1000 ℃～1200 ℃.
6. the manufacturing approach of nanocrystalline flash memory grid electrode as claimed in claim 1 is characterized in that, the thickness of said metal silicide layer is 40 dusts～150 dusts.
7. the manufacturing approach of nanocrystalline flash memory grid electrode as claimed in claim 1 is characterized in that, the thickness on said barrier layer is 20 dusts～120 dusts, and material is an amorphous silicon.
8. the manufacturing approach of nanocrystalline flash memory grid electrode as claimed in claim 1 is characterized in that, the injection rate of said fluorine ion is 10
13Cm
-3～10
15Cm
-3
9. the manufacturing approach of nanocrystalline flash memory grid electrode as claimed in claim 1 is characterized in that, the annealing temperature of said rapid thermal anneal process is 800 ℃～1000 ℃.
10. the manufacturing approach of nanocrystalline flash memory grid electrode as claimed in claim 1 is characterized in that, the thickness of said control grid is 600 dusts～1200 dusts, and material is a polysilicon.
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| CN201010620308.8A CN102543703B (en) | 2010-12-29 | 2010-12-29 | Manufacturing method of nanocrystalline flash memory grid |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104425226A (en) * | 2013-08-20 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Floating gate and forming method thereof, and flash memory unit and forming method thereof |
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| JPH01112755A (en) * | 1987-10-27 | 1989-05-01 | Sharp Corp | Manufacture of semiconductor device |
| US6093607A (en) * | 1998-01-09 | 2000-07-25 | Taiwan Semiconductor Manufacturing Company | Method of forming sharp beak of poly by oxygen/fluorine implant to improve erase speed for split-gate flash |
| CN101312213A (en) * | 2007-05-24 | 2008-11-26 | 中国科学院微电子研究所 | Non-volatile memory unit with nanocrystalline floating gate structure and manufacturing method thereof |
| US20100164021A1 (en) * | 2008-12-30 | 2010-07-01 | Yong-Soo Cho | Method of manufacturing semiconductor device |
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2010
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01112755A (en) * | 1987-10-27 | 1989-05-01 | Sharp Corp | Manufacture of semiconductor device |
| US6093607A (en) * | 1998-01-09 | 2000-07-25 | Taiwan Semiconductor Manufacturing Company | Method of forming sharp beak of poly by oxygen/fluorine implant to improve erase speed for split-gate flash |
| CN101312213A (en) * | 2007-05-24 | 2008-11-26 | 中国科学院微电子研究所 | Non-volatile memory unit with nanocrystalline floating gate structure and manufacturing method thereof |
| US20100164021A1 (en) * | 2008-12-30 | 2010-07-01 | Yong-Soo Cho | Method of manufacturing semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104425226A (en) * | 2013-08-20 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Floating gate and forming method thereof, and flash memory unit and forming method thereof |
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