CN102543207B - A kind of Efficient utilization method of RS error correction and detection algorithm in flash controller - Google Patents
A kind of Efficient utilization method of RS error correction and detection algorithm in flash controller Download PDFInfo
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Abstract
An Efficient utilization method for RS error correction and detection algorithm in flash controller, the method comprises: provide two RS error correction and detection algoritic modules, uses two frequency doubling clock time-sharing multiplex, completes the parallel encoding and decoding computing of 32 bit data interface data.The present invention adopts RS error correction and detection algoritic module and goes here and there and combine, and the method for time-sharing multiplex, decreases resource occupation, does not affect message transmission rate, and ensures the error correction and detection performance of RS code; Error correction and detection performance is outstanding, extends flash memory serviceable life; The serial of RS error correction and detection algoritic module accesses, and ensures the stream line operation of data.
Description
Technical field
The present invention relates to a kind of Efficient utilization method of RS error correction and detection algorithm, be specifically related to a kind of Efficient utilization method of RS error correction and detection algorithm in flash controller.
Background technology
In the flash controller of routine, usually adopt ECC, BCH, RS error correction and detection algorithm, ECC algorithm is simple relative to BCH algorithm and RS algorithm realization, takies resource few, but its limited error recovery capability.For the data of 512 bytes, by the checking information of generation 3 byte, can only correct the mistake of 1bit, the mistake of detected 2bit, therefore, if error number is too much in flash chip, ECC algorithm seems unable to do what one wishes.The error correcting capability of BCH algorithm is more eager to excel in whatever one does than ECC, is good at process random error, but BCH is step-by-step process data, for the process of parallel data, the data bus of such as flash chip is generally 8bit or higher, adopts BCH algorithm to process, then greatly can reduce message transmission rate.RS code is the important subclass of BCH, a special case of BCH code can be regarded as, RS code has the ability of good process random error and burst error, simultaneously, RS code is by Symbol processing data, and such as, in flash memory, certain byte should be 0X00, but to read from flash memory be but 0X0F, RS only thinks and has occurred 1 mistake, and BCH then thinks and occurred 4 mistakes.Therefore, in flash controller, use RS algorithm to correct burst error, reduce resource occupation, and do not affect message transmission rate.
Summary of the invention
The object of the present invention is to provide a kind of Efficient utilization method of RS error correction and detection algorithm in flash controller, which solve the defect that in prior art, error correction and detection module resource occupancy is high, its resources occupation rate is low, does not affect message transmission rate.
Technical solution of the present invention is:
An Efficient utilization method for RS error correction and detection algorithm in flash controller, its special character is, the method comprises:
Two RS error correction and detection algoritic modules are provided, use two frequency doubling clock time-sharing multiplex, complete the parallel encoding and decoding computing of 32 bit data interface data;
Specifically:
1) be first divided into by 32 position datawires high 16 and low 16, deliver to two RS modules respectively, then each RS error correction and detection algoritic module has only needed the coding and decoding of 16 bit data interface to calculate;
2) for the data of 16bit bit wide, first be given in the buffer memory of 1 16bit bit wide, after the data in buffer memory effectively, use the clock of 2 frequencys multiplication, the low 8bit data first read in buffer memory at first clock deliver to RS error correction and detection algoritic module as first raw data, read high 8bit data at second clock and deliver to RS error correction and detection algoritic module as second raw data, circulation is carried out, until all data are all given to RS error correction and detection algoritic module;
3) when coding and decoding result exports, result is given to the least-significant byte exporting buffer memory by first clock, result is given to the most-significant byte exporting buffer memory by second clock, circulation is carried out, until all results all export, simultaneously, when output buffer memory in data effectively by, adopt original clock by data reading, finally, export after the data of two 16bit are merged.
Above-mentioned encoding operation comprises:
1) 32 bit data exported from data buffer storage are split as 2 16 bit data (high 16bit and low 16bit), and respectively stored in buffer memory;
2) RS coding module adopts the clock of 2 frequencys multiplication, the low 8bit of 16bit data is taken out as raw data at first clock, the high 8bit of 16bit is taken out as raw data at second clock, order sends into RS coding module, and cycle alternation carries out until the data of a sector are all transmitted;
3) data of 512 bytes are all given to RS coding module by the time, stop reading data from data buffer storage;
4) by the time coding result starts to export, and first by first 8bit deposit data exporting least-significant byte to buffer memory, second 8bit deposit data is to the high 8bit of buffer memory, and cycle alternation carries out;
5) the 16bit data of two buffer memorys are spliced into 32bit data, are given in flash controller;
6) end-of-encode.
Above-mentioned decoding operation comprises:
1) from flash controller, 32bit data are read, be split as 2 16 bit data (high 16bit and low 16bit), and in data buffer storage respectively stored in the 16bit bit wide of two RS error correction and detection algoritic modules, make two RS error correction and detection algoritic modules independently carry out computing;
2) RS decoding module adopts the clock of 2 frequencys multiplication, takes out the low 8bit of 16bit data as raw data at first clock, and take out the high 8bit of 16bit as raw data at second clock, cycle alternation carries out;
3) by the time the data of 512 bytes are all given to RS decoding module, then from flash controller reader check information (2*32bit), be given to RS decoding module according to the method described above;
4) etc. to be decodedly to complete, when data inerrancy or existence are less than 4 byte wrong, directly misdata are corrected, then export.When error in data is greater than 4 byte, there is not repairable mistake in notice flash controller, requires that flash controller transmits the data of this sector again;
5) when decode results exports, first by first 8bit deposit data exporting to the least-significant byte of buffer memory, second 8bit deposit data is to the high 8bit of buffer memory, and cycle alternation carries out;
6) the 16bit data of two buffer memorys are spliced into 32bit data, are given in data buffer storage, only provide raw information, delete check information;
7) decoding terminates.
Above-mentioned error correction and detection module adopts the RS code on GF (2^8) territory, and its each symbol is 8bit (1 byte), and wherein raw data length is 128 byte, and check information length is 2 byte, corrects the mistake of 1 byte; For the data of 512 bytes, by the check information of generation 8 byte, correct the mistake of 4 byte.
Advantage of the present invention is:
1, go here and there to the employing of RS error correction and detection algoritic module module and combine, the method for time-sharing multiplex, decreases resource occupation, does not affect message transmission rate, and ensures the error correction and detection performance of RS code.
2, error correction and detection performance is outstanding, extends flash memory serviceable life.RS error correction and detection algorithm of the present invention, can ensure to each sector data the error in data correcting 4byte, meanwhile, when there is not repairable mistake, can provide error correction failure signal, and notice administration and supervision authorities carry out subsequent treatment.
3, RS error correction and detection algoritic module serial access, ensures the stream line operation of data.When encoding operation, RS error correction and detection algoritic module continually can read data and encode from upper layer data buffer memory, the result order of coding gained is delivered in flash memory write control module simultaneously.When decoding operation, the data that RS error correction and detection algoritic module can uninterruptedly receive in flash memory read control module carry out decoded operation, deliver in upper layer data buffer memory by the data sequence through correcting simultaneously, ensure the continuity of data, improve message transmission rate.
Accompanying drawing explanation
Fig. 1 is that RS error correction and detection module of the present invention adopts and goes here and there in conjunction with schematic diagram;
Fig. 2 is encoding operation schematic flow sheet of the present invention;
Fig. 3 is decoding operation schematic flow sheet of the present invention.
Embodiment
Error correction and detection module of the present invention adopts the RS code on GF (2^8) territory, and its each symbol is 8bit (1 byte), and wherein raw data length is 128 byte, and check information length is 2 byte, corrects the mistake of 1 byte; For the data of 512 bytes, by the check information of generation 8 byte, correct the mistake of 4 byte.
Structurally, RS error correction and detection module adopts and goes here and there the mode combined, and as shown in Figure 1, is first divided into by 32 position datawires high 16 and low 16, deliver to two RS modules respectively, then each RS error correction and detection algoritic module has only needed the coding and decoding of 16 bit data interface to calculate.For the data of 16bit bit wide, first be given in the buffer memory of 1 16bit bit wide, after the data in buffer memory effectively, use the clock of 2 frequencys multiplication, the low 8bit data first read in buffer memory at first clock deliver to RS error correction and detection algoritic module as first raw data, read high 8bit data at second clock and deliver to RS error correction and detection algoritic module as second raw data, circulation is carried out, until all data are all given to RS error correction and detection algoritic module.When coding and decoding result exports, result is given to the least-significant byte exporting buffer memory by first clock, result is given to the most-significant byte exporting buffer memory by second clock, circulation is carried out, until all results all export, simultaneously, when output buffer memory in data effectively by, adopt original clock by data reading, finally, export after the data of two 16bit are merged.
During coding: as shown in Figure 2
1) 32 bit data exported from data buffer storage are split as 2 16 bit data (high 16bit and low 16bit), and respectively stored in buffer memory;
2) RS coding module adopts the clock of 2 frequencys multiplication, the low 8bit of 16bit data is taken out as raw data at first clock, the high 8bit of 16bit is taken out as raw data at second clock, order sends into RS coding module, and cycle alternation carries out until the data of a sector are all transmitted;
3) data of 512 bytes are all given to RS coding module by the time, stop reading data from data buffer storage;
4) by the time coding result starts to export, and first by first 8bit deposit data exporting least-significant byte to buffer memory, second 8bit deposit data is to the high 8bit of buffer memory, and cycle alternation carries out;
5) the 16bit data of two buffer memorys are spliced into 32bit data, are given in flash controller;
6) end-of-encode.
During decoding: as shown in Figure 3
1) from flash controller, 32bit data are read, be split as 2 16 bit data (high 16bit and low 16bit), and in data buffer storage respectively stored in the 16bit bit wide of two RS error correction and detection algoritic modules, make two RS error correction and detection algoritic modules independently carry out computing;
2) RS decoding module adopts the clock of 2 frequencys multiplication, takes out the low 8bit of 16bit data as raw data at first clock, and take out the high 8bit of 16bit as raw data at second clock, cycle alternation carries out;
3) by the time the data of 512 bytes are all given to RS decoding module, then from flash controller reader check information (2*32bit), be given to RS decoding module according to the method described above;
4) etc. to be decodedly to complete, when data inerrancy or existence are less than 4 byte wrong, directly misdata are corrected, then export.When error in data is greater than 4 byte, there is not repairable mistake in notice flash controller, requires that flash controller transmits the data of this sector again;
5) when decode results exports, first by first 8bit deposit data exporting to the least-significant byte of buffer memory, second 8bit deposit data is to the high 8bit of buffer memory, and cycle alternation carries out;
6) the 16bit data of two buffer memorys are spliced into 32bit data, are given in data buffer storage, only provide raw information, delete check information;
7) decoding terminates.
RS error correction and detection algorithm used in the present invention, can correct the mistake of 4byte to the data of a sector, its performance is more superior compared with ECC algorithm, simultaneously under the prerequisite not affecting message transmission rate, with minimum resource occupation, ensure the consistance that flash chip reads and writes data.
Claims (4)
1. the Efficient utilization method of RS error correction and detection algorithm in flash controller, it is characterized in that, the method comprises:
Two RS error correction and detection algoritic modules are provided, use two frequency doubling clock time-sharing multiplex, complete the parallel encoding and decoding computing of 32 bit data interface data;
Specifically:
1) be first divided into by 32 position datawires high 16 and low 16, deliver to two RS modules respectively, then each RS error correction and detection algoritic module has only needed the coding and decoding of 16 bit data interface to calculate;
2) for the data of 16bit bit wide, first be given in the buffer memory of 1 16bit bit wide, after the data in buffer memory effectively, use the clock of 2 frequencys multiplication, the low 8bit data first read in buffer memory at first clock deliver to RS error correction and detection algoritic module as first raw data, read high 8bit data at second clock and deliver to RS error correction and detection algoritic module as second raw data, circulation is carried out, until all data are all given to RS error correction and detection algoritic module;
3) when coding and decoding result exports, result is given to the least-significant byte exporting buffer memory by first clock, result is given to the most-significant byte exporting buffer memory by second clock, circulation is carried out, until all results all export, simultaneously, when in output buffer memory, data are effective, adopt original clock by data reading, finally, export after the data of two 16bit are merged.
2. the Efficient utilization method of a kind of RS error correction and detection algorithm in flash controller according to claim 1, it is characterized in that, the encoding operation in described coding and decoding computing comprises:
1) 32 bit data exported from data buffer storage are split as 2 16 bit data height 16bit and low 16bit, and respectively stored in buffer memory;
2) RS coding module adopts the clock of 2 frequencys multiplication, the low 8bit of 16bit data is taken out as raw data at first clock, the high 8bit of 16bit is taken out as raw data at second clock, order sends into RS coding module, and cycle alternation carries out until the data of a sector are all transmitted;
3) data of 512 bytes are all given to RS coding module by the time, stop reading data from data buffer storage;
4) by the time coding result starts to export, and first by first 8bit deposit data exporting least-significant byte to buffer memory, second 8bit deposit data is to the high 8bit of buffer memory, and cycle alternation carries out;
5) the 16bit data of two buffer memorys are spliced into 32bit data, are given in flash controller;
6) end-of-encode.
3. the Efficient utilization method of a kind of RS error correction and detection algorithm in flash controller according to claim 1, it is characterized in that, the decoding operation in described coding and decoding computing comprises:
1) from flash controller, read 32bit data, be split as 2 16 bit data height 16bit and low 16bit, and in data buffer storage respectively stored in the 16bit bit wide of two RS error correction and detection algoritic modules, make two RS error correction and detection algoritic modules independently carry out computing;
2) RS decoding module adopts the clock of 2 frequencys multiplication, takes out the low 8bit of 16bit data as raw data at first clock, and take out the high 8bit of 16bit as raw data at second clock, cycle alternation carries out;
3) by the time the data of 512 bytes are all given to RS decoding module, then from flash controller reader check information 2*32bit, according to step 2) the data method that is given to RS decoding module is given to RS decoding module;
4) etc. to be decodedly to complete, when data inerrancy or existence are less than 4 byte wrong, directly misdata are corrected, then export; When error in data is greater than 4 byte, there is not repairable mistake in notice flash controller, requires that flash controller transmits the data of this buffer memory again;
5) when decode results exports, first by first 8bit deposit data exporting to the least-significant byte of buffer memory, second 8bit deposit data is to the high 8bit of buffer memory, and cycle alternation carries out;
6) the 16bit data of two buffer memorys are spliced into 32bit data, are given in data buffer storage, only provide raw information, delete check information;
7) decoding terminates.
4. according to the Efficient utilization method of the arbitrary described a kind of RS error correction and detection algorithm in flash controller of claims 1 to 3, it is characterized in that: described error correction and detection module adopts the RS code on GF (2^8) territory, its each symbol is 8bit (1 byte), wherein raw data length is 128 byte, check information length is 2 byte, corrects the mistake of 1 byte; For the data of 512 bytes, by the check information of generation 8 byte, correct the mistake of 4 byte.
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