CN1968036B - A forward correcting decoding device and control method - Google Patents
A forward correcting decoding device and control method Download PDFInfo
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- CN1968036B CN1968036B CN2006100851555A CN200610085155A CN1968036B CN 1968036 B CN1968036 B CN 1968036B CN 2006100851555 A CN2006100851555 A CN 2006100851555A CN 200610085155 A CN200610085155 A CN 200610085155A CN 1968036 B CN1968036 B CN 1968036B
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Abstract
The invention relates to a forward correcting decoder and relative control method, wherein said device comprises forward correct FEC decode circuit, frame data divide module and frame data recombine module; the FEC decode circuit has at least two parallel paths; the frame data divide module receives the frame data transmitted via FEC code method, and divides each frame data via word length sequence; feeds divided data sections into each FEC decode circuit and decodes; the frame data recombine module recombines frame data. The invention can avoid bandwidth limit, in GPON network, to send and decode descending data continuously.
Description
Technical field
The present invention relates to signal transmission technology, particularly a kind of forward correcting decoding device and control method.
Background technology
In the transmission of channel, avoid the interference of noise source in order to guarantee signal to the transmission signals content as far as possible, communication transmission system has all adopted error control mechanism usually, the information source and the stay of two nights are respectively the transmitting terminal and the receiving terminals of signal in the communication system, and the purpose of communication system allows signal zero defect ground be transferred to the stay of two nights from information source exactly.As shown in Figure 1, information source needs through source encoding after producing signal S, and the stay of two nights needs signal is carried out source coding before received signal, and these two is complete reverse process.The coding/decoding of information source is mainly finished the encryption of signal or other format conversion, and it is the preliminary treatment of before the signal transmission data content being carried out, and this part does not relate to the content of error control.These five parts of chnnel coding, modulator, channel, demodulator and channel-decoding are only the key component of error control in the signal transmission, highlight below.
As can see from Figure 1, when signal transmits in channel, can be subjected to the interference of noise source inevitably, the key of error control is how to make signal still can recover out after being subjected to noise jamming, and communication system is realized by before signal sends it being carried out chnnel coding.Concise and to the point, chnnel coding is to calculate according to data content to generate check code, and check code is inserted in the data content according to certain rule.When being sent to signal receiving end through coded data by modulator, channel and demodulator, whether channel-decoding comes the judgment data content to be polluted by noise source according to the check code in the transmission data again, and mistake is positioned and corrects.Like this, data just can realize the transmission of low error rate.
Error control classification in communication system is various, wherein main application now has four kinds: FEC (Forward Error Correction, forward error correction), ARQ (Automatic Error RequestEquipment, automatic error correction), HEC (Header Error Control, hybrid error correction mode) and narrow sense feedback information mode IRQ.
Under the ARQ transmission means, after signal receiving end was received the data that signal sending end sends, whether by check code is calculated, it was correct to judge the data that receive, and to the answer signal of ARQ signal sending end feedback judged result.If it is wrong judging data, then signal sending end resends this data, till receiving terminal can correctly receive data.This mode relatively is fit to the communication transmission of point-to-point, can guarantee to transmit the correctness of data, but its continuity and real-time is not high.Particularly under the more intense environment of noise background, the most of the time has been used on the data re-transmission;
Under the FEC transmission means, the receiving terminal of signal need not to feed back answer signal, and receiving terminal can transmit position wrong in the data according to the check code location, and mistake is made correction.This transmission mode does not have retransmission mechanism, therefore, can guarantee real time of data transmission, can carry out a user and broadcast communication to a plurality of users same;
The HEC mode combines the characteristics of FEC and ARQ, and after receiving data, receiving terminal at first carries out mistake and error correction to the data that receive.If the energy error correction then receives data; If can not error correction, feedback error correction failure signal then, signalling resends the data of last time.
After signal receiving end is received data in the IRQ mode, give signal sending end with the data loopback, whether correct by the transmitting terminal comparing data, and judge whether to resend.This mode efficiency of transmission is minimum, and the application scenario is limited.
Because the FEC error correcting system can guarantee real time of data transmission, therefore, must all correctly transmit and require in the Gigabit Passive Optical Network of real-time Transmission in not overcritical data, adopt the error control method of FEC.
PON (Passive Optics Network, EPON) is meant (Optics LineTerminate by OLT, optical line terminal), ONU (Optics Network Unit, optical network unit) and the passive electronic device systems formed of ODN (Optics Distribution Network, Optical Distribution Network).Passively be meant that Optical Distribution Network between OLT and ONU is without any active electronic equipment.Passive optical network technique is a kind of Optical Fiber Transmission and access technology of point-to-multipoint, descending employing broadcast mode, up employing time division multiple access way, can form topological structures such as tree type, star-like, bus-type neatly, do not need node device at optical branch point, only need that a simple optical branching device is installed and get final product, therefore have the cable resource of saving, bandwidth resources share, save machine room investment, device security height, networking speed soon, comprehensive networking low cost and other advantages.Just because of these reasons, make the PON technology obtain develop rapidly.
Classify from the content of carrying at present, the PON technology mainly comprises APON (ATM Based PONATM, ATM Passive Optical Network, wherein: ATM is Asynchronous Transfer Mode, asynchronous transfer mode), EPON (Ethernet Based PON, Ethernet passive optical network) and GPON (Gigabit-capable PON, Gigabit Passive Optical Network) etc., as shown in Figure 2, classical group web frame schematic diagram for the PON network, the PON network comprises OLT and a series of ONU that is positioned at user resident that is positioned at local side, between OLT and the ONU by optical fiber, the ODN that passive optical splitters or coupler constitute connects, ONU connects TDM (Time Division Multiplex, time division multiplexing) user (TDM Clients) or data user (Data Clients), OLT connects internet (IP Networks), TDM network (TDM Networks) or video network (VIDEO Networks).
Arrange in the PON system: the direction from OLT to ONU is a down direction, and the direction from ONU to OLT is a up direction.On up direction, on down direction, OLT is that all ONU in ODN of unit send data with the frame, and the frame transmission cycle that keeps 8KHz continually issues data to ODN, and the GPON downlink frame comprises frame head and payload part, as shown in Figure 3, be the example explanation with n frame and n+1 frame.
General RS (255, the 239) coding that adopts FEC when existing OLT sends downlink frame, ONU receive decoding and the error correction that needs to carry out downlink frame after the downlink frame.The position of FEC check code as shown in Figure 4 in the downlink frame, based on RS (255,239) Ma FEC check code is the check code that 16 bytes are inserted in per 239 byte back, per 255 bytes form a code word, for last data segment, if 239 bytes of data deficiencies increased by 0 with 239 bytes of polishing before or after the available data byte, insert check code then.For example shown in Figure 4, need in the end to mend 0 of 135 bytes in a code word.After ONU received downlink frame, downlink frame data need be cut into 255 bytes was the code word of unit, decodes respectively.After the decoding and error, remove the wherein check code of 16 bytes, the valid data spelling is just formed the frame data that ONU needs together.
Still consult shown in Figure 4, it should be noted that, mantissa part in each downlink frame, it is last code word, if during mantissa's less than 255 bytes, need insert 0 of suitable quantity in the data back before the ONU decoding, make the size of last code word also equal to finish fec decoder after 255 bytes, and utilize 16 corresponding byte check codes to carry out verification.After fec decoder finished, 0 of insertion need be removed once more, recovered to obtain original data.
Present many manufacturers all provide the ripe fec decoder module (FEC_CORE) based on RS (255,239) sign indicating number, and these FEC_CORE are 8 bit wides, and are that unit decodes with 255 byte codeword.Therefore, after ONU receives downlink frame, frame data must be organized into the code word of RS (255,239), and the code word of 255 byte longs is sent into FEC_CORE.Because the transmission of GPON downlink data is continual, every frame data finish the data of back followed by next frame.But during decoding, mantissa part in each downlink frame all might be inserted 0 extra data, 0 of extra insertion need take corresponding processing bandwidth, therefore, how to guarantee downlink frame data can be in real time, incessantly by the FEC_CORE decoding be the FEC mode can be in the GPON network key in application.
Summary of the invention
The invention provides a kind of forward correcting decoding device and control method, solving existing forward error correction error control method when the practical application, decoded portion is subjected to bandwidth constraints and can't realizes the problem of real-time decoding.
For solving the problems of the technologies described above, the invention provides following technical scheme:
A kind of forward error correction fec decoder device comprises frame data cutting module, frame data recombination module and the parallel forward error correction of the two-way at least fec decoder circuit that is provided with; Wherein,
Described frame data cutting module connects the input of each road forward error correction fec decoder circuit, be used to receive frame data based on forward error correction FEC coding, frame head sign according to frame data is distinguished adjacent two frame data, when receiving new frame data, send the frame head indication information at every turn, and according to each frame data of fixed byte length order cutting, each data sementation that is syncopated as is sent into each road forward error correction fec decoder circuit respectively according to setting decoding order, and at the byte length of postamble data sementation during less than described fixed byte length, after the postamble data sementation is inserted 0 processing, send into corresponding forward error correction fec decoder circuit or described postamble data sementation and the number that should insert 0 are sent into corresponding forward error correction fec decoder circuit simultaneously, by described forward error correction fec decoder circuit described postamble data sementation being inserted 0 handles, wherein, comprise one section valid data and corresponding forward error correction FEC check code in each data sementation, insert 0 position in the end before one section valid data or between these final stage valid data and last the forward error correction FEC check code, describedly send into each road forward error correction fec decoder circuit respectively and specifically comprise according to setting decoding order, according to the cutting order the non-postamble data sementation in each data sementation being write non-special-purpose decoding circuit in turn decodes, last postamble data sementation is write special-purpose decoding circuit decode, perhaps each the frame data segmentation in each data sementation is write each road decoding circuit in turn and decode according to the cutting order;
First Postponement module, be connected between described frame data cutting module and the frame data recombination module, described frame data recombination module is given in the frame head indication information delayed delivery that is used for described frame data cutting module is sent, and is the needed time of first data sementation of each frame data of decoding the time of delay of first Postponement module;
Described forward error correction fec decoder circuit comprises input buffer module, forward error correction fec decoder module and the output buffer module that connects in turn, is used for each data sementation is carried out parallel decoding, and decoded each data sementation is exported to the frame data recombination module;
Described frame data recombination module connects the output of each road decoding circuit, be used for that the decoding circuit from correspondence reads decoded first data sementation of these frame data behind the frame head indication information that receives the described first Postponement module delayed delivery, determine the total byte length that each frame data comprises according to the transmission rate of described frame data, when receiving described frame head indication information at every turn according to the count value of the local byte counter of described total byte length initialization, and when count value shows that having received described total byte length deducts a fixed byte length, determine that the next data sementation that read is the postamble data sementation, read each data sementation, and after reading decoded postamble data sementation, remove insert in the postamble data sementation whole 0, and remove check code in each data sementation, and according to output again behind the cutting order reorganization valid data.
Described decoding device also comprises second Postponement module; Wherein:
Insert 0 when sending into corresponding forward error correction fec decoder circuit after handling by described frame data cutting module at the postamble data sementation, be connected between described frame data cutting module and the frame data recombination module, be used for and give described frame data recombination module by described frame data cutting module in the number delayed delivery of described postamble data sementation insertion 0, be the needed time of first data sementation of each frame data of decoding the time of delay of second Postponement module; Perhaps
By described frame data cutting module described postamble data sementation and the number that should insert 0 are sent into corresponding forward error correction fec decoder circuit simultaneously, when described postamble data sementation being inserted 0 processing by described forward error correction fec decoder circuit, be connected between the input buffer module and frame data recombination module of No. one decoding circuit wherein, be used for giving described frame data recombination module in the number delayed delivery of described postamble data sementation insertion 0, be the needed time of first data sementation of each frame data of decoding the time of delay of second Postponement module this road decoding circuit.
Wherein, No. one decoding circuit at the input buffer module place that is connected with described second Postponement module is the special-purpose decoding circuit of described postamble data sementation.
Described forward error correction fec decoder module is 8 bit wide I/O; And/or described input buffer module and output buffer module all are first-in first-out FIFO memory.
The present invention also provides first kind of control method of above-mentioned decoding device, the road forward error correction fec decoder circuit that is provided with in this forward error correction fec decoder device is the special-purpose decoding circuit of decoded frame mantissa according to segmentation, other road forward error correction fec decoder circuit is the non-special-purpose decoding circuit of the non-postamble data sementation of decoding, and described control method comprises the steps:
A1, frame data cutting module receives the frame data based on forward error correction FEC coding, and distinguish adjacent two frame data according to the frame head of frame data sign, send the frame head indication information when receiving new frame data at every turn, and the frame head indication information is passed through the first Postponement module delayed delivery give the frame data recombination module, be decoding first needed time of data sementation of these frame data the time of delay of first Postponement module, according to these frame data of fixed byte length order cutting, comprise one section available frame count certificate and corresponding forward error correction FEC check code thereof in the frame data segmentation that each is syncopated as, according to the cutting order, frame data cutting module writes non-special-purpose decoding circuit in turn with the non-postamble data sementation in each frame data segmentation and decodes, last postamble data sementation is write special-purpose decoding circuit decodes, when the byte length of described postamble data sementation during less than described fixed byte length, the postamble data sementation is inserted 0 write described special-purpose decoding circuit after handling or with described postamble data sementation with should insert 0 number and send into described special-purpose decoding circuit simultaneously, by described special-purpose decoding circuit described postamble data sementation is inserted 0 and handle, insert 0 position in the end before one section valid data or between these final stage valid data and last the forward error correction FEC check code;
A2, frame data recombination module read decoded first data sementation of these frame data after receiving the frame head indication information from the decoding circuit of correspondence, determine the total byte length that each frame data comprises according to the transmission rate of described frame data, when receiving described frame head indication information or behind the intact frame data of every reorganization at every turn according to the count value of the local byte counter of described total byte length initialization; And when count value shows that having received described total byte length deducts a fixed byte length, determine that the next data sementation that read is the postamble data sementation, again according to the decoding order of non-postamble data sementation, after from non-special-purpose decoding circuit, reading all decoded non-postamble data sementations successively, from special-purpose decoding circuit, read decoded postamble data sementation again, and remove to insert whole 0, and according to reading order, the frame data recombination module is exported after removing the forward error correction FEC check code of each data sementation synchronously and the valid frame data sementation being reassembled as frame data.
When the byte length of described postamble data sementation during, before these postamble data of decoding, the postamble data sementation are inserted 0 handle, and whole 0 the concrete operations of removing insertion after decoding comprise following three kinds of modes less than described fixed byte length:
Also comprise in the described steps A 1: when the postamble data sementation that will write special-purpose decoding circuit by described frame data cutting module is inserted 0 processing, 0 the number that described frame data cutting module will be inserted is simultaneously given the frame data recombination module by the second Postponement module delayed delivery, is the needed time of first data sementation of each frame data of decoding the time of delay of second Postponement module; And also comprise in the described steps A 2: the frame data recombination module reads decoded postamble data sementation from special-purpose decoding circuit, and according to the number of described insertion 0, remove insert in this postamble data sementation whole 0 after the described frame data of recombinating again.
In the described steps A 1, when the postamble data sementation being write special-purpose decoding circuit by described frame data cutting module, 0 the number that should insert writes in the special-purpose decoding circuit, when the postamble data sementation being inserted 0 processing by special-purpose decoding circuit, 0 the number that described special-purpose decoding circuit will insert by second Postponement module again delayed delivery give the frame data recombination module, be the needed time of first data sementation of each frame data of decoding the time of delay of second Postponement module; Also comprise in the described steps A 2: the frame data recombination module reads decoded postamble data sementation from special-purpose decoding circuit, and according to the number of described insertion 0, remove insert in this postamble data sementation whole 0 after the described frame data of recombinating again.
Also comprise in the described steps A 2: the frame data recombination module reads decoded postamble data sementation from special-purpose decoding circuit, 0 the number of determining to insert according to the transmission rate of described frame data, and remove insert in this postamble data sementation whole 0 after the described frame data of recombinating again.
Said method kind, described frame data are that described fixed byte length is 255 bytes of integral multiple based on the frame data of the FEC coding of RS (255,239), and wherein the valid data that comprise in 255 bytes of each section are 239 bytes, and check code is 16 bytes; And
When transmission rate is 2.5G bps, should insert 135 0 in the postamble data sementation;
When transmission rate is 1.25G bps, should insert 195 0 in the postamble data sementation.
The control method of second kind of forward error correction fec decoder device provided by the invention comprises the steps:
B1, frame data cutting module receive the frame data based on forward error correction FEC coding, and distinguish adjacent two frame data according to the frame head sign of frame data, send the frame head indication information when receiving new frame data at every turn; And the frame head indication information is passed through the first Postponement module delayed delivery give the frame data recombination module, be decoding these frame data needed time of first data sementation the time of delay of first Postponement module, according to these frame data of fixed byte length order cutting, comprise one section available frame count certificate and corresponding forward error correction FEC check code thereof in the frame data segmentation that each is syncopated as, according to the cutting order, frame data cutting module writes each road decoding circuit in turn with each frame data segmentation synchronously and decodes, when the byte length of described postamble data sementation during less than described fixed byte length, the postamble data sementation is inserted 0 send into corresponding forward error correction fec decoder circuit after handling or with described postamble data sementation with should insert 0 number and send into corresponding forward error correction fec decoder circuit simultaneously, by described forward error correction fec decoder circuit described postamble data sementation is inserted 0 and handle, insert 0 position in the end before one section valid data or between these final stage valid data and last the forward error correction FEC check code;
B2, frame data recombination module read decoded first data sementation of these frame data after receiving the frame head indication information from the decoding circuit of correspondence, determine the total byte length that each frame data comprises according to the transmission rate of described frame data, when receiving described frame head indication information or behind the intact frame data of every reorganization at every turn according to the count value of the local byte counter of described total byte length initialization; Each time when count value shows that having received described total byte length deducts a fixed byte length, determine that the next data sementation that read is the postamble data sementation, and again according to the decoding order of correspondence, from each road decoding circuit, read each frame data segmentation successively, and remove to insert whole 0, and export after removing the forward error correction FEC check code of each data sementation synchronously and the valid frame data sementation being reassembled as frame data.
In this second kind of mode of operation, further processing procedure and first kind of mode of operation are similar.
Beneficial effect of the present invention is as follows:
The present invention adopts the multiplexing mode of multichannel FEC_CORE, a kind of parallel fec decoder device control corresponding method that multichannel FEC_CORE decoding circuit is set is provided, utilize the mode of multidiameter delay decoding, eliminated when utilizing the FEC error control method, to the extra bandwidth constraints problem of inserting at 0 o'clock in the postamble data of the frame data of FEC coded system transmission; Technical solution of the present invention satisfies the real-time decoding request to the descending fec frame data of interrupted transmission in the GPON network fully.
Description of drawings
Fig. 1 is the error control principle explanation schematic diagram in the communication system;
Fig. 2 is typical PON structural representation;
Fig. 3 is a GPON downlink frame structural representation;
Fig. 4 inserts the structural representation of FEC check code for the GPON downlink frame;
Fig. 5, Fig. 6 are the embodiment of the invention one described decoding device structural representation;
Fig. 7, Fig. 8 are the embodiment of the invention two described decoding device structural representations;
Fig. 9, Figure 10 are the embodiment of the invention three described decoding device structural representations.
Embodiment
Existing RS (255,239) FEC_CORE is the input of 8 bit wides, the output of 8 bit wides, carry out the needed extra bandwidth of preliminary treatment according to the bit wide of GPON downlink frame data with to the postamble data, the present invention adopts the multiplexing mode of multichannel FEC_CORE, total input and output bit wide of decoded portion should be complementary with the frame data bit wide of transmission, below with specific embodiment and be described with reference to the accompanying drawings.
Embodiment one
When 16 bit wide downlink frame datas were realized real-time fec decoder, decoding device structure provided by the invention comprised as shown in Figure 5:
First via fec decoder circuit is comprising input buffer module CW_BUF_0, the fec decoder module FEC_CORE_0 and the output buffer module FEC_BUF_0 that connect successively;
The second road fec decoder circuit is comprising input buffer module CW_BUF_1, the fec decoder module FEC_CORE_1 and the output buffer module FEC_BUF_1 that connect successively;
Third Road fec decoder circuit is comprising input buffer module CW_BUF_2, the fec decoder module FEC_CORE_2 and the output buffer module FEC_BUF_2 that connect successively;
Frame data cutting module FEC_IN is connected the input of each input buffer module CW_BUF;
Frame data recombination module FEC_OUT is connected the output of each output buffer module FEC_BUF;
The first Postponement module FP_DELAY is connected between FEC_IN and the FEC_OUT;
The second Postponement module NUM_RESIDUE_DELAY is connected between CW_BUF_2 and the FEC_OUT.
Wherein, the specific implementation circuit of each cache module is a lot, can export according to the input sequence of data as long as can control it, and wherein, the simplest cache module of control mode is first-in first-out FIFO (First in First out) memory.
Describe the course of work of frame data of the decoding of decoding device shown in Fig. 5 below in detail:
Needing 16 bit wide real time datas FEC_IN module right side input from Fig. 5 of decoding, according to RS (255,239) standard definition at present, all is the inputs of 8 bit wides based on the FEC_CORE module of RS (255,239), the output of 8 bit wides.Can see that the bit wide difference can cause the bottleneck of data stream bandwidth; Simultaneously because downlink frame fec decoder afterbody can be by inserting 0 code word that gathers together enough last 255 byte long, 0 of insertion can cause unnecessary bandwidth equally.
Consult shown in Figure 4ly, the beginning of each frame data partly carries frame head sign, and FEC_IN can be according to adjacent two frame data of frame head sign difference.
Can handle the data of input in real time for guaranteeing the fec decoder device, the present invention adopts the multiplexing method of multichannel fec decoder, device shown in Figure 5 is multiplexing three road FEC_CORE, be respectively FEC_CORE_0, FEC_CORE_1 and FEC_CORE_2, this three road fec decoder all is 8 bit wide I/O, three road fec decoder module cooperatings can satisfy the bandwidth requirement of downlink frame data.Fec decoder device shown in Figure 5 can have following two kinds of mode of operations:
One, wherein one road fec decoder module-specific is not used in the non-postamble code word of decoding in decoding postamble code word, sees FEC_CORE_2
Consult shown in Figure 5ly, middle three FEC_CORE modules are finished fec decoder, and the FEC_IN of both sides and FEC_OUT finish the frame data cutting before the decoding and the logic module of decoded frame data reorganization respectively.Because the transmission speed of frame data is much larger than the processing speed of single FEC_CORE module, therefore, the influence that the present invention adopts the loose coupling mode of FIFO to come buffering rate not match to bring.
Consult shown in Figure 5; CW_BUF cache module and FEC_BUF mould cache blocks that each FEC_CORE two ends connects all are the FIFO memories; these FIFO memories can absorb bandwidth difference between decoder module and the cutting/recombination module, and the achieve frame data seamlessly transit between two kinds of transmission rates.
Consult shown in Figure 5, downlink frame data is imported from the FEC_IN right side, FEC_IN is by the frame head id signal, identify the starting point of each downlink frame data, and the local byte counter of initialization begins counting and (byte counter can be initialized as 0 and carry out plus coujnt, the total byte length value that also can be initialized as frame data of current data transmission rate correspondence carries out the subtraction counting), downlink frame data being cut into 255 byte longs successively is the data segment of unit, and these length are that the data segment of 255 bytes is called code word.After FEC_IN generates these code words, again they are write in CW_BUF_0 and two fifo modules of CW_BUF_1 in turn successively.For example, first code word writes CW_BUF_0, and second code word writes CW_BUF_1, and the 3rd code word writes CW_BUF_0 again, by that analogy.
The code word that writes among CW_BUF_0 and the CW_BUF_1 is finished 16 after the conversion of 8 bit wides in FIFO, directly sent into two decoder modules of FEC_CORE_0 and FEC_CORE_1 and handle.Code word is finished bit wide from the CW_BUF_0/CW_BUF_1 module, and to be transformed into FEC_CORE_0/FEC_CORE_1 decoding all be continual, therefore, these two fifo modules of CW_BUF_0/CW_BUF_1 can not filled up, FEC_IN can continually write code word to CW_BUF_0 and CW_BUF_1, guarantees the interrupted transmission of downlink data.
As indicated above, downlink frame data is cut into one by one code word by FEC_IN with frame data sends into FEC_CORE_0 and FEC_CORE_1 decoding respectively by CW_BUF_0 and CW_BUF_1 two-way FIFO.But, when switching to the mantissa part of downlink frame data, last byte is not enough to form the code word of one 255 byte long, therefore, FEC_IN need determine to insert 0 number according to the postamble byte number, and will insert 0 number and write CW_BUF_2, CW_BUF_2 finishes bit width conversion, and when writing the FEC_CORE_2 decoder module, in desired location (before the data byte or between data byte and the 16 bit check bytes) insertion 0 of this byte, FEC_CORE_2 decodes to the postamble code word.
Here need to prove, under special speed, when the postamble data just in time are 255 bytes, do not need to insert 0 and handle.Insert 0 if desired and handle, FEC_IN can judge whether to be syncopated as the penult code word of the frame data of this decoding according to the count value of byte counter, if then next data sementation then is the postamble data sementation.
Here need to prove also that according to the concrete frame data section length that is syncopated as of setting of disposal ability of FIFO, if FIFO once can write two or three code words, then corresponding can be 510 bytes or 765 bytes with the length setting of cutting data sementation.Insert 0 when handling when needs, insert 0 position in the end before one section valid data or in the end between one section valid data and last check code.
Hereto, each data sementation of downlink frame data is all sent into FEC_CORE_0, FEC_CORE_1 and FEC_CORE_2 successively and is finished and decoded, below discuss data in detail by behind three road fec decoders, be combined into the process of a complete downlink frame data again.
Still consult as shown in Figure 5, the decoded data sementation of FEC_CORE_0, FEC_CORE_1 and FEC_CORE_2 is write FEC_BUF_0, FEC_BUF_1 and FEC_BUF_2 respectively.Wherein FEC_BUF_0, FEC_BUF_1 are used for data are become 16 bit wides from 8 bit width conversion with FEC_BUF_2, and its effect and CW_BUF_0, CW_BUF_1, CW_BUF_2 just in time are reverse.FEC_BUF_0, FEC_BUF_1 and the FEC_BUF_2 data after FEC_OUT output bit width conversion are finished the reorganization of frame data by FEC_OUT.
FEC_IN is to CW_BUF_0, CW_BUF_1 and CW_BUF_2 write the code word of downlink frame data respectively, simultaneously, the frame head index signal fp of each downlink frame is sent into the FP_DELAY module, wherein fp is the frame head indication of downlink frame, fp effectively represents the frame starting point of downlink frame data, between FEC_IN and FEC_OUT, play the effect of Synchronization Control, though the local byte counter of FEC_OUT can be divided adjacent two frame data by the total amount of byte of each frame data, but local counting is in case make mistakes, to cause irrecoverable error, so the Synchronization Control effect of fp indication can be avoided the generation of this situation.
The function of FP_DELAY is exactly to finish the time-delay of descending frame head index signal fp, and its time-delay clock periodicity equals the time that frame data need altogether through CW_BUF_0 and FEC_CORE_0/CW_BUF_1 and FEC_CORE_1/CW_BUF_2 and FEC_CORE_2 decoding just.Like this, FP_DELAY just can be synchronous with decoded frame data to the descending frame head signal fp of FEC_OUT output behind the suitable clock periodicity of delaying time.
FEC_OUT determines the total byte length that each frame data comprises according to the transmission rate of frame data equally, when count value shows that having received total byte length deducts a regular length byte, can determine that the next data sementation that read is the postamble data sementation each time.When FEC_OUT receive FP_DELAY module output through the descending frame head signal fp after the time-delay, represent that promptly first data of downlink frame have been finished fec decoder.Therefore, after FEC_OUT receives the descending frame head signal fp of FP_DELAY output, the local byte counter of synchronous initiation FEC_OUT, counting downlink frame total bytes, from FEC_BUF_0 and FEC_BUF_1, read by turns the code fetch digital data simultaneously, that is: from FEC_BUF_0, read first code word, from FEC_BUF_1, read second code word then, read the 3rd code word again from FEC_BUF_0, the rest may be inferred.When the total amount of byte of reading equals the frame data byte number of present rate correspondence, after FEC_OUT removes the check digit of these code word afterbodys, the code word content is connected in turn, remove to insert then extra 0 after just reconstruct decoded downlink frame data.
FP_DELAY is identical with the fp time delay module, FEC_IN can write CW_BUF_2 with the number of inserting 0, CW_BUF_2 outputs to the NUM_RESIDUE_DELAY module, NUM_RESIDUE_DELAY is a time delay module, through the time-delay identical with FP_DELAY, NUM_RESIDUE_DELAY exports to the FEC_OUT module with the number of postamble slotting 0.FEC_OUT removes 0 of respective number on this basis in the postamble code word that will read from FEC_BUF_2, obtain the remaining byte of postamble at last, as the postamble data of downlink frame.
As mentioned above, the data that FEC_OUT reads this three tunnel code word are stitched together and just are reduced into decoded downlink frame valid data, export from output port.
The effect of NUM_RESIDUE_DELAY module has been to provide transmits 0 the number of inserting in each postamble data, but existing GPON network mainly adopts 2.5G and two kinds of speed of 1.25G, 2.5G under the speed, each is based on RS (255, the downlink frame data of FEC coding 239) comprises 38880 bytes, need be cut into 153 code words and decode, each postamble code word need be inserted 135 0; 1.25G under the speed, each downlink frame data based on the FEC coding of RS (255,239) comprises 19440 bytes, need be cut into 77 code words and decode, each postamble code word need be inserted 195 0.With other regular length cutting code words, for example two 255 bytes, promptly during 510 byte cutting code words, it is identical to insert 0 number in each code word.If present rate is known, then FEC_OUT can judge that the tail frame data insert 0 number by present rate, do not need to utilize this pass through mechanism to know and insert 0 number each postamble data, can omit the NUM_RESIDUE_DELAY module under this application scenarios from FEC_IN.FEC_OUT determines the total byte length that each frame data comprises according to the transmission rate of frame data, utilizes the count value of local byte counter to distinguish adjacent two frame data, specifically comprises: zero clearing count value behind the intact frame data of every reorganization; Reach in count value each time and from special-purpose decoding circuit, read the postamble data sementation when frame data total byte length deducts the regular length of a frame data segmentation.
If between a plurality of speed, switch, perhaps the frequency of speed switching is higher, the number of each postamble data discrepancy 0 changes comparatively frequent, then can be when generation rate switching each time, carry out one time pass through mechanism, FEC_IN will insert 0 number and write CW_BUF_2, CW_BUF_2 outputs to the NUM_RESIDUE_DELAY module, NUM_RESIDUE_DELAY postpones to export to FEC_OUT, further, can when each tail frame data of decoding, all carry out once this pass through mechanism, to guarantee each frame data of correctly recombinating.
Here need to prove that in each communication network, corresponding all possess the present rate informing mechanism, when communication beginning or generation rate switch, notify corresponding processing module present rate.
Two, decoding schema in turn
In this mode of operation, FEC_IN is cut into one by one code word with frame data and sends into FEC_CORE_0, FEC_CORE_1 and FEC_CORE_2 decoding in turn by CW_BUF_0, CW_BUF_1 and CW_BUF_2 three road FIFO, when switching to the mantissa part of downlink frame data, last byte is not enough to form the code word of one 255 byte long, by FEC_IN this postamble code word is write among the CW_BUF_2, and write simultaneously and insert 0 number, FEC_CORE_2 decoding postamble code word to CW_BUF_2.
As previously mentioned, when not needing to transmit postamble and insert 0 number, can arrange decode first code word of each frame data of any one tunnel in No. three decoding circuits.If but when the needs pass through mechanism guarantees, select the decoding circuit of first code word of decoding in conjunction with actual circuit structure, make when the postamble code word write a corresponding decoding circuit, 0 the number that should insert also writes in this homographic solution decoding circuit, for example: in the circuit structure shown in Figure 5, under existing 2.5G and the 1.25G speed, when agreement No. the second decoding circuit, be that FEC_CORE_1 is when decoding first code word, the postamble code word is input among the CW_BUF_2, and finishes the transmission of the number of insertion 0 by the second Postponement module NUM_RESIDUE_DELAY that this CW_BUF_2 connects.
The delay mechanism of the frame head indication fp signal of downlink frame and process and first kind of mode of operation of FEC_OUT end reassembled frame data are identical.
The structure of another kind of decoding device as shown in Figure 6, the second Postponement module NUM_RESIDUE_DELAY directly is connected between FEC_IN and the FEC_OUT, operating among the FEC_IN of insertion 0 finished in the postamble data sementation, at this moment, when descending frame data arrive mantissa part, when last remainder bytes is not enough to form the code word of one 255 byte long, FEC_IN need insert 0 in last frame data, with 0 with the remaining byte of postamble is common forms a code word, and this postamble code word is write among the CW_BUF_2.To insert 0 number then and give FEC_OUT by the NUM_RESIDUE_DELAY delayed delivery.Except that operating in of insertion 0 finished among the FEC_IN, other courses of work and circuit shown in Figure 5 were identical.
Embodiment two
When 8 bit wide downlink frame datas were realized real-time fec decoder, decoding device structure provided by the invention comprised as shown in Figure 7:
First via fec decoder circuit is comprising input buffer module CW_BUF_0, the fec decoder module FEC_CORE_0 and the output buffer module FEC_BUF_0 that connect successively;
The second road fec decoder circuit is comprising input buffer module CW_BUF_1, the fec decoder module FEC_CORE_1 and the output buffer module FEC_BUF_1 that connect successively;
Frame data cutting module FEC_IN is connected the input of each input buffer module CW_BUF;
Frame data recombination module FEC_OUT is connected the output of each output buffer module FEC_BUF;
The first Postponement module FP_DELAY is connected between FEC_IN and the FEC_OUT;
The second Postponement module NUM_RESIDUE_DELAY is connected between CW_BUF_1 and the FEC_OUT.
In like manner, the mode of operation of this decoding device is identical with the mode of operation described in the embodiment one, and the course of work is all fours also, and difference is:
Under first kind of mode of operation, the decoding work of non-postamble code word is independently born by FEC_CORE_0;
Under second kind of mode of operation, by two FEC_CORE decoding in turn.
In like manner, when not needing to transmit the number of insertion 0 in the postamble code word, NUM_RESIDUE_DELAY can omit.Transmit if desired and insert 0 number in the postamble code word, when existing 2.5G and 1.25G speed, agreement is by decode first code word of each frame data of FEC_CORE_1, thereby the postamble code word is input among the CW_BUF_1, and finishes the transmission of the number of insertion 0 by the second Postponement module NUM_RESIDUE_DELAY that this CW_BUF_1 connects.
As Fig. 8, the second Postponement module NUM_RESIDUE_DELAY also can be connected between FEC_IN and the FEC_OUT, is specifically finished the operation of insertion 0 in the postamble data by FEC_IN.
Embodiment three
When 32 bit wide downlink frame datas were realized real-time fec decoder, decoding device structure provided by the invention needed No. five decoding circuit co-ordinations as shown in Figure 9 altogether, and this decoding device specifically comprises:
First via fec decoder circuit is comprising input buffer module CW_BUF_0, the fec decoder module FEC_CORE_0 and the output buffer module FEC_BUF_0 that connect successively;
The second road fec decoder circuit is comprising input buffer module CW_BUF_1, the fec decoder module FEC_CORE_1 and the output buffer module FEC_BUF_1 that connect successively;
Third Road fec decoder circuit is comprising input buffer module CW_BUF_2, the fec decoder module FEC_CORE_2 and the output buffer module FEC_BUF_2 that connect successively;
The four road fec decoder circuit is comprising input buffer module CW_BUF_3, the fec decoder module FEC_CORE_3 and the output buffer module FEC_BUF_3 that connect successively;
The five road fec decoder circuit is comprising input buffer module CW_BUF_4, the fec decoder module FEC_CORE_4 and the output buffer module FEC_BUF_4 that connect successively;
Frame data cutting module FEC_IN is connected the input of each input buffer module CW_BUF;
Frame data recombination module FEC_OUT is connected the output of each output buffer module FEC_BUF;
The first Postponement module FP_DELAY is connected between FEC_IN and the FEC_OUT;
The second Postponement module NUM_RESIDUE_DELAY is connected between CW_BUF_4 and the FEC_OUT.
The mode of operation of this decoding device is identical with the mode of operation described in the embodiment one, and the course of work is all fours also, and difference is:
Under first kind of mode of operation, the decoding work of non-postamble code word by FEC_CORE_0-FEC_CORE_3 totally No. four decoding circuits bear;
Under second kind of mode of operation, by the decoding in turn of No. five decoding circuits.
In like manner, when not needing to transmit the number of insertion 0 in the postamble code word, NUM_RESIDUE_DELAY can omit.Transmit if desired and insert 0 number in the postamble code word, when existing 2.5G and 1.25G speed, agreement is by decode first code word of each frame data of FEC_CORE_3, thereby the postamble code word is input among the CW_BUF_4, and finishes the transmission of the number of insertion 0 by the second Postponement module NUM_RESIDUE_DELAY that this CW_BUF_3 connects.
As shown in figure 10, the second Postponement module NUM_RESIDUE_DELAY also can be connected between FEC_IN and the FEC_OUT, is specifically finished the operation of insertion 0 in the postamble data by FEC_IN.
In sum, be generalized to ordinary circumstance, suppose that needing the real time data bit wide of decoding is N, the I/O bit wide of FEC_CORE is M, and N and M generally are 8 integral multiple, then need multiplexing N ÷ M+1 road decoding circuit.Existing FEC_CORE is 8 bit wide I/O, and therefore general multiplexing N ÷ 8+1 road decoding circuit can be realized the object of the invention.
The foregoing description is that example describes with the downlink frame data of decoding GPON network, in the network of same other communication mechanisms of technical scheme provided by the invention, upstream or downstream frame based on the FEC coded system is carried out decoding processing, do not limit to the frame data of processing equally based on RS (255,239) coded format.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (16)
1. a forward error correction fec decoder device is characterized in that, comprises frame data cutting module, frame data recombination module and the parallel forward error correction of the two-way at least fec decoder circuit that is provided with; Wherein,
Described frame data cutting module connects the input of each road forward error correction fec decoder circuit, be used to receive frame data based on forward error correction FEC coding, frame head sign according to frame data is distinguished adjacent two frame data, when receiving new frame data, send the frame head indication information at every turn, and according to each frame data of fixed byte length order cutting, each data sementation that is syncopated as is sent into each road forward error correction fec decoder circuit respectively according to setting decoding order, and at the byte length of postamble data sementation during less than described fixed byte length, after the postamble data sementation is inserted 0 processing, send into corresponding forward error correction fec decoder circuit or described postamble data sementation and the number that should insert 0 are sent into corresponding forward error correction fec decoder circuit simultaneously, by described forward error correction fec decoder circuit described postamble data sementation being inserted 0 handles, wherein, comprise one section valid data and corresponding forward error correction FEC check code in each data sementation, insert 0 position in the end before one section valid data or between these final stage valid data and last the forward error correction FEC check code, describedly send into each road forward error correction fec decoder circuit respectively and specifically comprise according to setting decoding order, according to the cutting order the non-postamble data sementation in each data sementation being write non-special-purpose decoding circuit in turn decodes, last postamble data sementation is write special-purpose decoding circuit decode, perhaps each the frame data segmentation in each data sementation is write each road decoding circuit in turn and decode according to the cutting order;
First Postponement module, be connected between described frame data cutting module and the frame data recombination module, described frame data recombination module is given in the frame head indication information delayed delivery that is used for described frame data cutting module is sent, and is the needed time of first data sementation of each frame data of decoding the time of delay of first Postponement module;
Described forward error correction fec decoder circuit comprises input buffer module, forward error correction fec decoder module and the output buffer module that connects in turn, is used for each data sementation is carried out parallel decoding, and decoded each data sementation is exported to the frame data recombination module;
Described frame data recombination module connects the output of each road decoding circuit, be used for that the decoding circuit from correspondence reads decoded first data sementation of these frame data behind the frame head indication information that receives the described first Postponement module delayed delivery, determine the total byte length that each frame data comprises according to the transmission rate of described frame data, when receiving described frame head indication information at every turn according to the count value of the local byte counter of described total byte length initialization, and when count value shows that having received described total byte length deducts a fixed byte length, determine that the next data sementation that read is the postamble data sementation, read each data sementation, and after reading decoded postamble data sementation, remove insert in the postamble data sementation whole 0, and remove check code in each data sementation, and according to output again behind the cutting order reorganization valid data.
2. decoding device as claimed in claim 1 is characterized in that, inserts 0 when sending into corresponding forward error correction fec decoder circuit after handling by described frame data cutting module at the postamble data sementation, and this decoding device also comprises second Postponement module; Be connected between described frame data cutting module and the frame data recombination module, be used for and give described frame data recombination module by described frame data cutting module in the number delayed delivery of described postamble data sementation insertion 0, be the needed time of first data sementation of each frame data of decoding the time of delay of second Postponement module.
3. decoding device as claimed in claim 1, it is characterized in that, by described frame data cutting module described postamble data sementation and the number that should insert 0 are sent into corresponding forward error correction fec decoder circuit simultaneously, when by described forward error correction fec decoder circuit described postamble data sementation being inserted 0 processing, this decoding device also comprises second Postponement module; Be connected between the input buffer module and frame data recombination module of No. one decoding circuit wherein, be used for giving described frame data recombination module in the number delayed delivery of described postamble data sementation insertion 0, be the needed time of first data sementation of each frame data of decoding the time of delay of second Postponement module this road decoding circuit.
4. decoding device as claimed in claim 3 is characterized in that, No. one decoding circuit at the input buffer module place that is connected with described second Postponement module is the special-purpose decoding circuit of described postamble data sementation.
5. decoding device as claimed in claim 1 or 2 is characterized in that, described forward error correction fec decoder module is 8 bit wide I/O; And/or described input buffer module and output buffer module all are first-in first-out FIFO memory.
6. decoding device as claimed in claim 1, it is characterized in that, described frame data are based on RS (255, the frame data of FEC coding 239), described fixed byte length is 255 bytes of integral multiple, wherein the valid data that comprise in 255 bytes of each section are 239 bytes, and check code is 16 bytes.
7. control method of forward error correction fec decoder device according to claim 1, the road forward error correction fec decoder circuit that is provided with in this forward error correction fec decoder device is the special-purpose decoding circuit of decoded frame mantissa according to segmentation, other road forward error correction fec decoder circuit is the non-special-purpose decoding circuit of the non-postamble data sementation of decoding, and described control method comprises the steps:
A1, frame data cutting module receives the frame data based on forward error correction FEC coding, and distinguish adjacent two frame data according to the frame head of frame data sign, send the frame head indication information when receiving new frame data at every turn, and the frame head indication information is passed through the first Postponement module delayed delivery give the frame data recombination module, be decoding first needed time of data sementation of these frame data the time of delay of first Postponement module, according to these frame data of fixed byte length order cutting, comprise one section available frame count certificate and corresponding forward error correction FEC check code thereof in the frame data segmentation that each is syncopated as, according to the cutting order, frame data cutting module writes non-special-purpose decoding circuit in turn with the non-postamble data sementation in each frame data segmentation and decodes, last postamble data sementation is write special-purpose decoding circuit decodes, when the byte length of described postamble data sementation during less than described fixed byte length, the postamble data sementation is inserted 0 write described special-purpose decoding circuit after handling or with described postamble data sementation with should insert 0 number and send into described special-purpose decoding circuit simultaneously, by described special-purpose decoding circuit described postamble data sementation is inserted 0 and handle, insert 0 position in the end before one section valid data or between these final stage valid data and last the forward error correction FEC check code;
A2, frame data recombination module read decoded first data sementation of these frame data after receiving the frame head indication information from the decoding circuit of correspondence, determine the total byte length that each frame data comprises according to the transmission rate of described frame data, when receiving described frame head indication information or behind the intact frame data of every reorganization at every turn according to the count value of the local byte counter of described total byte length initialization; And when count value shows that having received described total byte length deducts a fixed byte length, determine that the next data sementation that read is the postamble data sementation, again according to the decoding order of non-postamble data sementation, after from non-special-purpose decoding circuit, reading all decoded non-postamble data sementations successively, from special-purpose decoding circuit, read decoded postamble data sementation again, and remove to insert whole 0, and according to reading order, the frame data recombination module is exported after removing the forward error correction FEC check code of each data sementation synchronously and the valid frame data sementation being reassembled as frame data.
8. control method as claimed in claim 7 is characterized in that,
Also comprise in the described steps A 1: when the postamble data sementation that will write special-purpose decoding circuit by described frame data cutting module is inserted 0 processing, 0 the number that described frame data cutting module will be inserted is simultaneously given the frame data recombination module by the second Postponement module delayed delivery, is the needed time of first data sementation of each frame data of decoding the time of delay of second Postponement module; And
Also comprise in the described steps A 2: the frame data recombination module reads decoded postamble data sementation from special-purpose decoding circuit, and according to the number of described insertion 0, remove insert in this postamble data sementation whole 0 after the described frame data of recombinating again.
9. control method as claimed in claim 7 is characterized in that,
In the described steps A 1, when the postamble data sementation being write special-purpose decoding circuit by described frame data cutting module, 0 the number that should insert writes in the special-purpose decoding circuit, when the postamble data sementation being inserted 0 processing by special-purpose decoding circuit, 0 the number that described special-purpose decoding circuit will insert by second Postponement module again delayed delivery give the frame data recombination module, be the needed time of first data sementation of each frame data of decoding the time of delay of second Postponement module;
Also comprise in the described steps A 2: the frame data recombination module reads decoded postamble data sementation from special-purpose decoding circuit, and according to the number of described insertion 0, remove insert in this postamble data sementation whole 0 after the described frame data of recombinating again.
10. control method as claimed in claim 7 is characterized in that,
Also comprise in the described steps A 2: the frame data recombination module reads decoded postamble data sementation from special-purpose decoding circuit, 0 the number of determining to insert according to the transmission rate of described frame data, and remove insert in this postamble data sementation whole 0 after the described frame data of recombinating again.
11. as one of any described control method of claim 7-10, it is characterized in that, described frame data are based on RS (255, the frame data of FEC coding 239), described fixed byte length is 255 bytes of integral multiple, wherein the valid data that comprise in 255 bytes of each section are 239 bytes, and check code is 16 bytes; And
When transmission rate is 2.5G bps, should insert 135 0 in the postamble data sementation;
When transmission rate is 1.25G bps, should insert 195 0 in the postamble data sementation.
12. the control method of forward error correction fec decoder device according to claim 1, described control method comprises the steps:
B1, frame data cutting module receive the frame data based on forward error correction FEC coding, and distinguish adjacent two frame data according to the frame head sign of frame data, send the frame head indication information when receiving new frame data at every turn; And the frame head indication information is passed through the first Postponement module delayed delivery give the frame data recombination module, be decoding these frame data needed time of first data sementation the time of delay of first Postponement module, according to these frame data of fixed byte length order cutting, comprise one section available frame count certificate and corresponding forward error correction FEC check code thereof in the frame data segmentation that each is syncopated as, according to the cutting order, frame data cutting module writes each road decoding circuit in turn with each frame data segmentation and decodes, when the byte length of described postamble data sementation during less than described fixed byte length, the postamble data sementation is inserted 0 send into corresponding forward error correction fec decoder circuit after handling or with described postamble data sementation with should insert 0 number and send into corresponding forward error correction fec decoder circuit simultaneously, by described forward error correction fec decoder circuit described postamble data sementation is inserted 0 and handle, insert 0 position in the end before one section valid data or between these final stage valid data and last the forward error correction FEC check code;
B2, frame data recombination module read decoded first data sementation of these frame data after receiving the frame head indication information from the decoding circuit of correspondence, determine the total byte length that each frame data comprises according to the transmission rate of described frame data, when receiving described frame head indication information or behind the intact frame data of every reorganization at every turn according to the count value of the local byte counter of described total byte length initialization; Each time when count value shows that having received described total byte length deducts a fixed byte length, determine that the next data sementation that read is the postamble data sementation, and again according to the decoding order of correspondence, from each road decoding circuit, read each frame data segmentation successively, and remove to insert whole 0, and export after removing the forward error correction FEC check code of each data sementation synchronously and the valid frame data sementation being reassembled as frame data.
13. control method as claimed in claim 12 is characterized in that,
Also comprise among the described step B1: when the postamble data sementation that will write the homographic solution decoding circuit by described frame data cutting module is inserted 0 processing, 0 the number that described frame data cutting module will be inserted is simultaneously given the frame data recombination module by the second Postponement module delayed delivery, is the needed time of first data sementation of each frame data of decoding the time of delay of second Postponement module; And
Also comprise among the described step B2: the frame data recombination module reads decoded postamble data sementation from the homographic solution decoding circuit, and according to the number of described insertion 0, remove insert in this postamble data sementation whole 0 after the described frame data of recombinating again.
14. control method as claimed in claim 12 is characterized in that,
Among the described step B 1, when the postamble data sementation being write the homographic solution decoding circuit by described frame data cutting module, 0 the number that should insert writes in the homographic solution decoding circuit, when the postamble data sementation being inserted 0 processing by the homographic solution decoding circuit, 0 the number that described homographic solution decoding circuit will insert by second Postponement module again delayed delivery give the frame data recombination module, be the needed time of first data sementation of each frame data of decoding the time of delay of second Postponement module;
Also comprise among the described step B2: the frame data recombination module reads decoded postamble data sementation from the homographic solution decoding circuit, and according to the number of described insertion 0, remove insert in this postamble data sementation whole 0 after the described frame data of recombinating again.
15. control method as claimed in claim 12 is characterized in that,
Also comprise among the described step B2: the frame data recombination module reads decoded postamble data sementation from the homographic solution decoding circuit, 0 the number of determining to insert according to the transmission rate of described frame data, and remove insert in this postamble data sementation whole 0 after the described frame data of recombinating again.
16. as one of any described control method of claim 12-15, it is characterized in that, described frame data are based on RS (255, the frame data of forward error correction FEC coding 239), described fixed byte length is 255 bytes of integral multiple, wherein the valid data that comprise in 255 bytes of each section are 239 bytes, and check code is 16 bytes; And
When transmission rate is 2.5G bps, should insert 135 0 in the postamble data sementation;
When transmission rate is 1.25G bps, should insert 195 0 in the postamble data sementation.
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| CN102082629B (en) * | 2010-12-15 | 2013-06-19 | 烽火通信科技股份有限公司 | Hardware coding method and circuit based on FEC (forward error correction) in 10G EPON ONU (Ethernet passive optical network optical network unit) |
| CN102543207B (en) * | 2010-12-17 | 2016-01-06 | 西安奇维测控科技有限公司 | A kind of Efficient utilization method of RS error correction and detection algorithm in flash controller |
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| CN106998244A (en) * | 2017-05-31 | 2017-08-01 | 中国科学院半导体研究所 | Fec systems, method and the coding of ethernet data frame, decoding apparatus |
| CN109150410B (en) * | 2018-10-30 | 2021-09-24 | 京信网络系统股份有限公司 | Data transmission method and device |
| CN111416630A (en) * | 2020-03-05 | 2020-07-14 | 烽火通信科技股份有限公司 | Coding and decoding method and system |
| CN111769906B (en) * | 2020-06-29 | 2022-07-05 | 中国人民解放军国防科技大学 | Data transmission method and device for adaptively reducing processing delay of coding layer and link layer |
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| CN115314157B (en) * | 2022-07-19 | 2023-10-24 | 烽火通信科技股份有限公司 | Ethernet framing method and device |
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