CN102520343A - Graphical test method of semiconductor devices - Google Patents
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Abstract
The invention discloses a graphical test method of semiconductor devices. A test program is divided into a top layer, a test index layer and a programming module layer, wherein the top layer testing process is formed by test indexes; the test index layer is formed by programming modules according to a semiconductor test step; and the programming module layer corresponds to operation and needed parameters of the step. When the test program is developed, only the test indexes are set for each semiconductor device, and each test index sets up a sub process; then, in a graphical parameter setting interface, the programming module corresponding to each step in the process sets one parameter; after completing, the programming module automatically generates a test, and the text is explained to a C source program and is compiled into an ARM (Advanced RISC Machines) executable file; then the ARM executable file is downloaded through a USB (Universal Serial Bus) to a tester for operation; and finally the semiconductor devices are tested. The development convenience is increased, the development cycle is shortened at the same time, and the maintainability of the test program is enhanced.
Description
Technical field
The invention belongs to the semiconducter device testing technical field, more specifically, relate to a kind of semiconductor device graph method of testing.
Background technology
Transistor invention the 1950's, the semiconducter device testing technology produces thereupon.Even to this day, semiconductor industry is to weigh the mainstay property industry of national comprehensive strength.In the semiconductor industry chain, test is unique industry of producing and using overall process that runs through.
Therefore how whether up to standard the semiconductor devices quantity required is huge, in scale of mass production, guarantee the characterisitic parameter of semiconductor devices one of bottleneck of weighing each production firm's production strength and productivity effect that just becomes.Yet semiconductor devices is of a great variety, and model is various, and corresponding test index does not wait at several to dozens of, even with a kind of type product, the method for testing of different manufacturers also is not quite similar.Therefore to different semiconductor devices, its testing process also is different, must write different test procedures to each semiconductor devices.
Prior art; Adopt higher level lanquage such as C/C++/C#/Java etc. that each semiconductor devices is write the special test procedure of a cover; Though these higher level lanquages are powerful; Use flexibly, but in technical field of measurement and test is used, have weak point: to a kind of semiconductor all is to carry out test procedure with higher level lanquage to write, and convenience is poor, the construction cycle is long and it is high to safeguard.
Summary of the invention
The deficiency that the objective of the invention is to prior art provides a kind of semiconductor device graph method of testing, with convenience, the shortening construction cycle of improving test program development, and the maintainability of enhancing test procedure.
For realizing the foregoing invention purpose, a kind of semiconductor device graph method of testing of the present invention is characterized in that, may further comprise the steps:
(1), be that every kind of semiconductor device is created a test procedure in host computer, according to a patterned top layer testing process of the semiconducter device testing index formation that need test successively;
(2), set up a patterned sub-process for each test index; Each step of sub-process is represented with patterned programming module; Each programming module is provided with the interface to a parameter should be arranged, and through this parameter this programming module respective operations parameters needed of interface setting is set;
Programming module is divided into measurement and applies module, hardware operation module and decision-making function module; Wherein, Measurement applies the feature board that module is used to call tester and applies/measuring voltage or electric current; The hardware operation module is used to call the test board of tester and forms semi-conductive test circuit, and determination module is used for according to Rule of judgment, carries out process Selection;
(3), will be successively under the top layer testing process operation and the corresponding required Parameters Transformation of the programming module in each sub-process be text formatting, output test text file;
(4), the test text file is interpreted as the C source program: the feature board driver is encapsulated, obtain the trial function prototype of programming module, again the trial function prototype is encapsulated, accomplish the corresponding function of programming module; Then the C source program is compiled as the ARM executable file, downloads to the tester operation, semiconductor devices is tested through USB.
Goal of the invention of the present invention is achieved in that
Semiconductor device graph method of testing of the present invention, through test procedure being divided into top layer, test index layer and programming module layer, the top layer testing process is formed with test index; The test index layer is made up according to the semiconductor test step by programming module and forms, and the programming module layer is then to operation and parameters needed thereof that should step, during test program development; Only need press test index for each semiconductor devices; Each test index is set up sub-process, be provided with in the interface in graphical parameter then, the corresponding programming module of each step carries out the parameter setting in the flow; After the completion; Automatically generate text, be interpreted as the C source program and be compiled as the ARM executable file, download to the tester operation through USB then, semiconductor devices is tested.The exploitation convenience is improved, shortens the construction cycle simultaneously, and strengthens the maintainability of test procedure.
Description of drawings
Fig. 1 is the theory diagram of semiconducter device testing;
Fig. 2 is the particular flow sheet of semiconductor device graph method of testing of the present invention;
Fig. 3 is the structural drawing of semiconductor device graph method of testing of the present invention;
Fig. 4 is graphic programming module one instantiation figure in the semiconductor device graph method of testing of the present invention;
Fig. 5 is the encapsulation synoptic diagram of programming module;
Fig. 6 is the FIMV circuit theory diagrams;
Fig. 7 is that the parameter of judge module is provided with surface chart;
Fig. 8 is circulatory function flow instance figure;
Fig. 9 is selection function flow instance figure;
Figure 10 is transistor base and the corresponding sub-process figure of emitter saturation voltage test index;
Figure 11 is that flowchart illustrations is interpreted as C source program one embodiment process flow diagram;
Figure 12 is each item test index top-level flow figure;
Figure 13 is VCESTA test philosophy figure;
Figure 14 is saturation voltage between collector and emitter (VCESTA) process flow diagram;
Figure 15 is that UR makes up the test circuit synoptic diagram;
Figure 16 is that the FI_1 module parameter is provided with surface chart;
Figure 17 is that the FIMV_1 module parameter is provided with surface chart;
Figure 18 is that the RESET_1 module parameter is provided with surface chart.
Embodiment
Describe below in conjunction with the accompanying drawing specific embodiments of the invention, so that those skilled in the art understands the present invention better.What need point out especially is that in the following description, when perhaps the detailed description of known function and design can desalinate main contents of the present invention, these were described in here and will be left in the basket.
Fig. 1 is the theory diagram of semiconducter device testing.
Semiconductor device graph method of testing of the present invention is relied on semiconductor device tester, adopts host computer and tester framework, makes development environment and running environment separate, has improved the security and the stability of test.
As shown in Figure 1, tester comprises that a core control panel is a CPU board, produces polylith feature board and test boards such as pulse current board of the hardboard of high pressure excitation, the low pressing plate that produces low voltage excitation, generation current excitation.Be placed with semiconductor devices DUT to be measured on the test board.
The core control panel is tested the semiconductor devices DUT to be measured on the test board through from total each feature board of line traffic control, and uploads test result realizes test data and testing engineering to host computer centralized management through USB interface.
Host computer is realized the control to tester through USB interface; Host computer is deployed under the windows platform that .Net Frame Wbrk3.5 and SQL server 2000 are installed in advance; Completion is to the graphic programming of semiconductor devices DUT to be measured, and the text of generation correspondence automatically, is interpreted as the C source program then and is compiled as the ARM executable file; Download to the tester operation through USB, semiconductor devices is tested.
Fig. 2 is the particular flow sheet of semiconductor device graph method of testing of the present invention.
As shown in Figure 2; In the present embodiment; Type according to semiconductor devices DUT to be measured is set up the top-level flow figure that comprises each test index, each test index is called each programming module as required accomplish a test sub-process figure, thereby accomplish graphic programming.Then programming module is converted successively into the text of appointment, be the Xml file in the present embodiment, be interpreted as the C source program and be compiled as the ARM executable file, be downloaded to the tester operation by usb bus then, semiconductor devices is tested.
Wherein the realization of graphic programming stage and text → C source program is this patent innovative content.
1, the principle of graphic programming and realization
1.1, the general structure of graphic programming
Test for each semiconductor devices; Form a top layer testing process by several or tens different test indexs; The corresponding sub-flow process of each test index, sub-process by a series of hardware operation, apply programming modules such as excitation, measurement, data processing and form.
According to above design philosophy, total is divided into 2 parts: graphical interfaces and function prototype storehouse.The function prototype storehouse is the support and the basis of whole programming module.
Fig. 3 is the structural drawing of semiconductor device graph method of testing of the present invention;
As shown in Figure 3, graphically be subdivided into 3 levels:
Integrated testability layer (top layer testing process) generates when making up test event, comprises a graphical top layer testing process of being made up of a series of test indexs.
Test index layer (sub-process figure layer), the graphical test sub-process figure that forms according to certain testing sequence by programming module.
The programming module layer at first encapsulates the feature board driver and obtains the trial function prototype, the trial function prototype is encapsulated again, and accomplishes corresponding function.
Fig. 4 is graphic programming module one instantiation figure in the semiconductor device graph method of testing of the present invention.
In the present embodiment, as shown in Figure 4, programming module as follows is provided, have the function package module of calling function plate, and judgement, the branch of programming needs, functions such as circulation.
1, the classification of programming module
Programming module is divided into according to function:
● measure and to apply module: execute stream pressure measurement (FIMV), the pressure measurement of exerting pressure (FVMV), execute stream flow measurement (FVMI), execute stream flow measurement (FIMI), exert pressure (FV), execute stream (FI), pressure measurement (MV);
● the hardware operation module: reset (RESET), relay are selected (UR), pulse high current plate hardware operation (PIB), hardboard ramp voltage hardware operation (BVO), time-delay (Delay);
● logic function module: judge.
2, the encapsulation of programming module
Realize graphic programming, programming module must solve following problem.
● the module suction parameter comprises various excitation applying conditions etc.
● the module outlet parameter comprises information such as test result.
● the encapsulation of each feature board driving function.
Fig. 5 is the encapsulation synoptic diagram of programming module.
Graphic programming module as shown in Figure 5 is divided into 2 levels on module package, the processing on foreground demonstration and backstage.The foreground shows it mainly is some interface display and mutual with the user.The handling procedure on backstage then mainly is to the management at interface, foreground and calling of prototype function, converts text into and text converts the C source file into corresponding to the programming module among Fig. 2.
Parameter is provided with the interface each module package is become independently assembly, has not only comprised all properties of module, and required interface also is provided.
The background process program is mainly accepted parameter interface property and parameter is set, and is passed to corresponding prototype function, realizes the transmission of interface display program attribute and parameter.
Function prototype is that each feature board driving function is encapsulated the function that obtains.The process of encapsulation has masked the information relevant with hardware, and has realized the automatic selection and the conversion of current/voltage range.
3, the realization of programming module
3.1, measure and to apply module
With FIMV (adding the stream pressure measurement) module the process that graphic programming is realized is described below.
3.1.1 circuit theory analysis
Fig. 6 is the circuit theory diagrams of FIMV.As can be seen from Figure 6, computing machine carries out data transmission through usb bus and ARM.ARM carries out the mutual of detecting information through bus and FPGA, comprises that output applies current value, returns test voltage value etc.
The work engineering of FIMV is described below: the at first program run among the ARM, and FPGA control starts DA, the electric current that output applies, through first-level buffer, it is on the DUT that one-level power amplifier and sampling resistor are applied to measured device.Metering circuit is sent into AD with the aanalogvoltage of measuring through voltage follower, carries out sending into FPGA after the analog to digital conversion, sends into the value that ARM obtains measuring voltage through self-defined bus again.
Sample resistance converts current signal into voltage signal among the figure, and backfeed loop is used to hold the voltage at sample resistance two ends.Clamping circuit plays the effect of holding circuit, and when measured voltage surpassed the scope of measuring setting, the direct retroactive effect of clamping circuit made voltage be stabilized in set clamp voltage value in the power amplifier end, thereby plays the effect of holding circuit.
3.1.2 feature board driving function encapsulation
Can see that from Fig. 1 tester has four feature boards, each piece feature board all has the function of FIMV, but the driving function form of every feature board is all the same, just all contains the relevant information of hardware separately.So need the driving function of feature board be encapsulated.
The encapsulation step of the driving function of feature board is following:
(1), according to application point search function board name, slot number, channel number, slotted line system;
(2), according to the plate name, apply or clamp current value and current unit is applied or clamp current value and current range;
(3), according to the plate name, apply or the clamping voltage value is applied or clamp current value and voltage range;
(4), confirm to apply time-delay, measure time-delay, filtering type, filter times, filtering delay-time according to the plate name;
(5), drive according to plate name calling function plate.
3.1.3 implementation procedure
With the FIMV module is example, and semiconductor devices to be measured is applied the electric current of setting in the display routine interface, measures corresponding voltage, and returns the function of test value.
Table 1
It is as shown in table 1 that parameter is provided with the interface; Selection can be accomplished and apply the channel number that electric current is surveyed the feature board place of voltage under the channel selecting label; Input need put on the current value and the unit thereof of device under test, and the clamper value is set, and in panel the opening of pilot relay, closure.It is as shown in the table that function prototype and parameter are provided with the parameter corresponding relation at interface:
| Function parameter | position | ForceI | vClamp | CurrentUint | Relay |
| Parameter is provided with the interface | Passage | The value of applying | The clamper value | The value of applying unit | Relay |
Table 2
Preserve the name of module in the Xml file that program is preserved, type and some parameters are seen table 1.Wherein the sequence number of index representation module graphically shows by Left, Top, Width, Height and sets.FIMV_1 is the rreturn value of module in the Text node, and FIMV is a module type, and 1 is numbering, and FUN is a functional module.The series of parameters of logging modle in < Paral >; The rreturn value of return_variable=" rlt_FIMV_1 " representation module is rlt_FIMV_1, and channel=" M2 " expression postion is M2, and value_force=" 10 " expression ForceI is 10; Value_clamp=" 1 " expression vClamp is 1; Unit=" mA " expression applies the unit of electric current, and the state of relay=" ON " expression relay R elay is ON, and value_item=" True " representes as function return value.
It is as follows to be converted into Xml file process by the graphic programming module, and the parameter of this module and writing in the corresponding prototype function among the read-write Xml was accomplished calling of function prototype, thereby realized its functions of modules when compiling generated the C source program.
3.2, the hardware operation module
With the UR module is that example describes, and in the present embodiment, 64 relays on the test board is carried out switch set, as shown in table 3, and relay of each option control is chosen to opening, otherwise be closure.
Table 3
Through 0,1 variable, 0 for turn-offing to 64 relay switch controls, and 1 for opening.Thereby obtain 64 01 sequence, be kept in the Xml file.
Parameter is provided with shown in the following form of parameter corresponding relation of interface and function prototype:
| Function parameter | position |
| Interface program | Sequence after 64 relays transform |
Table 4
Write in the XML file of specified path and preserve, key code is following.Compile time read-write Xml calls corresponding UR (string position) function automatically, and parameter is imported into.
3..3, the logic function module
Describe with determination module, as shown in Figure 7, to importing the judgement of value into, and carry out selectivity according to structure and carry out.This module does not have function prototype, and through directly decision condition being attached among the if (), the judgement of setting then flows to carries out work.
This module can realize two kinds of different functions: circulation and selection.
That realizes shown in the process flow diagram as shown in Figure 8 is circulatory function.Semiconductor devices to be measured is added stream pressure measurement (FIMV_1), and rlt_FIMV_1＞1 decision that whether satisfies condition continues test component or reset passages (RESET_1) according to the size of module rreturn value rlt_FIMV_1.
In the Xml file of preserving, note the introducing node (FIMV_1 as above) of determination module, the decision condition and the branch of drawing node (RESET_1, FIMV_1) and correspondence of determination module, and the relative position of determination module.
The process flow diagram that is illustrated in fig. 9 shown below is realized selection function.Semiconductor devices to be measured is added stream pressure measurement (FIMV_1); Rlt_FIMV_1＞1 decision that whether satisfies condition is device under test to be applied voltage test (FV_1) and still apply electric current and test (FI_1) according to the size of module rreturn value rlt_FIMV_1; Test finishes, to passage reset (RESET_2).
4, sub-process figure
The corresponding sub-process flow diagram of test index.Each sub-process figure comprises one or more modules, is provided with according to the needs of testing process.The test procedure that utilizes the programming module structuring user's to need, shown in figure 10: to the realization of the saturation voltage between a triode test base stage and the emitter.The structure testing engineering is set up test index, adds functional module UR_1, FI_1, FI_2, FIMV_1, RESET_1, and corresponding parameters is set, and through the arrow in the panel test sequencing is set, and saves as the Xml file after completion is set.
5, top layer test flow chart
Test flow chart comprises and is no less than a test index, generates corresponding test index Xml through each test index, can generate the sequencing of a top layer testing process Xml with the operation of record test index to the traversal of test index.
When top-level flow figure was converted into the Xml file: at first the test index with each was converted into corresponding Xml, generates the Xml of a testing process then, write down the order of each test index test.
6, flowchart illustrations is interpreted as the C source program
Flowchart illustrations is interpreted as the C source program needs the function prototype of top-level flow figure Xml, sub-process figure Xml, module, C language public library.The explanation flow process is shown in figure 11.
The realization that the Xml file that generates is interpreted as the C source program is the design's important component part.Program at first generates the gauge outfit of C file, reads top layer test flow chart Xml then, reads the Xml of correspondence successively according to the order of test index.Then in test index sub-process figure Xml; Again according to the order of the module essential information and the parameter of read module successively, if prototype function is arranged, according to essential information call function prototype and write corresponding function parameter; Otherwise, directly generate corresponding C source program according to rule according to information.And write in the C source files of program.
Instance analysis
Be example with triode 8550 (positive-negative-positive) commonly used below, the process of graphic programming is described.
8550 common indexs comprise between emitter and the base stage between breakdown reverse voltage, collector and the emitter saturation voltage etc., and each index all has a test condition and acceptable ranges in test, as shown in table 5.Table 5 is 8550 each index test condition and test results.
Table 5
1, writes top-level flow figure
According to selecting test index and entering to be provided with shown in the table 1 with the relevant menu item of test, obtain the top-level flow figure of test index, shown in figure 12.Carry out the programming of sub-process figure then according to the test request of each test index.
2, write sub-process figure program
2.1, the test philosophy map analysis
The test of each index of 8550 all need make up test circuit according to testing process.Schematic diagram with this index of the saturation voltage between 8550 collectors and the emitter (VCESTA) is that example is carried out the test philosophy analysis.Figure 13 is the test circuit schematic diagram of this index of VCESTA.
Shown in figure 13; Record the saturation voltage (VCESTA) between the collector and emitter; Then triode should be in state of saturation; Apply electric current respectively at base stage and collector and make the triode state that reaches capacity, again with the direct ground connection of emitter, then shown in the voltage table be exactly the value of the VCESTA that will survey.Current source among the figure can apply through the passage of each feature board, and the passage of subfunction plate also has measurement function simultaneously.
The test process of VCESTA is divided into following four steps:
1: make up test circuit through closed corresponding relays.Closed UR1; The current/voltage that UR15 makes the base stage (being the B end among Figure 13) of triode be connected to the subfunction plate applies the measurement passage; Be numbered UR2 through closure; The UR16 relay applies the measurement passage by another current/voltage that the collector of triode (being the C end among Figure 13) is connected to the subfunction plate, is numbered the UR18 relay by the emitter of triode (be being E end among Figure 13) ground connection through closure again.
2: the base stage at triode applies rated current.According to the foundation of test circuit in test condition in the table 5 and the step 1, the current/voltage through subfunction plate PAB applies and measures passage and apply in the base stage of triode-electric current of 80mA.
3: the collector at triode applies rated current and measuring voltage.According to the foundation of test circuit in the test condition of table 5 and the step 1, the current/voltage through subfunction plate PAB applies and measures passage and apply at collector-electric current of 800mA, and measures the voltage of the relative emitter of collector, i.e. VCESTA.
4: used TCH test channel resets.For safety, all to the passage of test be resetted after measuring each time.
2.2, the setting of module parameter among the sub-process figure
With this index of the saturation voltage between the collector and emitter of triode 8550 (VCESTA) is example; Want to record the saturation voltage between the collector and emitter; Can know according to the analysis of test philosophy in 2.1 joints, need use the writing of flowchart program that four modules are accomplished this index, be respectively UR_1; FI_1, FIMV_1 and RESET_1 module.The sub-process figure program of index is shown in figure 14.
2.2.1, the parameter setting of UR_1 module
As can be seen from Figure 15, each index all will make up corresponding test network.Accomplish building of test circuit so at first call the UR module through choosing corresponding relays to number.According to the analysis in 2.1 joints, choose UR1, UR2, UR15, UR16, relays such as UR18.
2.2.2, the FI_1 module parameter is provided with
The completion test circuit need apply test and excitation after building.According to analysis and the test condition in the table 5 in 2.1 joints, apply in the base stage (being the B end) of triode-electric current of 80mA through FI_1, it is 2V that clamp voltage is set.Detail parameters is provided with shown in figure 16.
2.2.3, the FIMV_1 module parameter is provided with
After base stage applies excitation, according to test condition in analysis and the table 1 in 2.1 joints, adopt the FIMV_1 module, apply at the collector (being the C end) of triode-excitation of 800mA, it is 2V that clamp voltage is set, relay is opened, simultaneously the survey time C voltage of ordering.Detailed parameter is provided with shown in figure 17.
2.2.4, the RESET_1 module parameter is provided with
When accomplish excitation apply with the survey time test result after, need the passage of the subfunction plate that uses be resetted.In the RESET_1 module, choose corresponding passage name.Be provided with shown in figure 18 in detail.
At last, need these above-mentioned modules are coupled together according to sequencing, accomplish the programming of this test index of VCESAT, the process flow diagram test procedure of VCESAT is seen shown in Figure 14.
The measurement result of 3 triodes 8550
Each index to 8550 is all carried out sub-process figure programming according to above-mentioned process, and compiling is passed through, and moves, and obtains the measurement result of every index.Table 6 is to be the test result after 8550 triode is measured to three models.
Table 6
Although above the illustrative embodiment of the present invention is described; So that the technician of present technique neck understands the present invention, but should be clear, the invention is not restricted to the scope of embodiment; To those skilled in the art; As long as various variations appended claim limit and the spirit and scope of the present invention confirmed in, these variations are conspicuous, all utilize innovation and creation that the present invention conceives all at the row of protection.
Claims (3)
1. a semiconductor device graph method of testing is characterized in that, may further comprise the steps:
(1), be that every kind of semiconductor device is created a test procedure in host computer, according to a patterned top layer testing process of the semiconducter device testing index formation that need test successively;
(2), set up a patterned sub-process for each test index; Each step of sub-process is represented with patterned programming module; Each programming module is provided with the interface to a parameter should be arranged, and through this parameter this programming module respective operations parameters needed of interface setting is set;
Programming module is divided into measurement and applies module, hardware operation module and decision-making function module; Wherein, Measurement applies the feature board that module is used to call tester and applies/measuring voltage or electric current; The hardware operation module is used to call the test board of tester and forms semi-conductive test circuit, and determination module is used for according to Rule of judgment, carries out process Selection;
(3), will be successively under the top layer testing process operation and the corresponding required Parameters Transformation of the programming module in each sub-process be text formatting, output test text file;
(4), the test text file is interpreted as the C source program: the feature board driver is encapsulated, obtain the trial function prototype of programming module, again the trial function prototype is encapsulated, accomplish the corresponding function of programming module; Then the C source program is compiled as the ARM executable file, downloads to the tester operation, semiconductor devices is tested through USB.
2. semiconductor device graph method of testing according to claim 1 is characterized in that, described programming module is divided into 2 levels on module package, i.e. the handling procedure on foreground demonstration and backstage;
The foreground shows it mainly is some interface display and mutual with the user, and the handling procedure on backstage then mainly is to the management at interface, foreground and calling of prototype function, converts programming module into text and text converts the C source file into;
Parameter is provided with the interface each module package is become independently assembly, has not only comprised all properties of module, and required interface also is provided;
The background process program is mainly accepted parameter interface property and parameter is set, and is passed to corresponding prototype function, realizes the transmission of interface display program attribute and parameter;
Function prototype is that each feature board driving function is encapsulated the function that obtains, and the process of encapsulation has masked the information relevant with hardware, and has realized the automatic selection and the conversion of current/voltage range.
3. semiconductor device graph method of testing according to claim 1 is characterized in that, the encapsulation step of described feature board driving function is following:
(1), according to application point search function board name, slot number, channel number, slotted line system;
(2), according to the plate name, apply or clamp current value and current unit is applied or clamp current value and current range;
(3), according to the plate name, apply or the clamping voltage value is applied or clamp current value and voltage range;
(4), confirm to apply time-delay, measure time-delay, filtering type, filter times, filtering delay-time according to the plate name;
(5), drive according to plate name calling function plate.
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| WO2020000772A1 (en) * | 2018-06-28 | 2020-01-02 | 昂纳信息技术（深圳）有限公司 | Method and system for testing optical amplifier |
| CN110412380A (en) * | 2019-08-02 | 2019-11-05 | 西安太乙电子有限公司 | A kind of test method based on graphical mosfet driver |
| CN110412380B (en) * | 2019-08-02 | 2022-02-18 | 西安太乙电子有限公司 | Testing method based on graphical MOSFET driver |
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