CN102508983B - The simulation building method of process of memory rear section structure and simulation building device - Google Patents
The simulation building method of process of memory rear section structure and simulation building device Download PDFInfo
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- CN102508983B CN102508983B CN201110388699.XA CN201110388699A CN102508983B CN 102508983 B CN102508983 B CN 102508983B CN 201110388699 A CN201110388699 A CN 201110388699A CN 102508983 B CN102508983 B CN 102508983B
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Abstract
The present invention relates to a kind of simulation building method of process of memory rear section structure, be simultaneous for simulation building method and set up simulation building device.By the second dielectric layer in base structure is divided at least four layers of points of dielectric layers, the bottom surface of described second grid overlaps with second point of dielectric layer bottom surface, described 3rd grid bottom surface overlaps with the 4th point of dielectric layer, thus define second grid and the 3rd grid " suspends " in the simulation architecture of second dielectric layer, i.e. avoid violating simulation architecture and be necessary for the requirement of same material about same layer medium, the accurate location of each grid can be reflected again strictly according to the facts, it is thus possible to obtain output characteristics parameter accurately, improve verity and the accuracy of simulation result.
Description
Technical field
The present invention relates to a kind of simulation building method and simulation building device, particularly relate to a kind of process of memory back segment knot
The simulation building method of the simulation building method of structure and simulation building device.
Background technology
Memorizer (Memory) is the memory device in computer system, is used for depositing program and data.In computer entirely
Portion's information, initial data, computer program, middle operation result and final operation result including input are all saved in memorizer
In.It is stored according to the position that controller is specified and taking-up information.Having had memorizer, computer just has memory function, Cai Nengbao
The normal work of card.Main storage (internal memory) and additional storage (external memory) can be divided into by purposes memorizer, also have and be divided into outside to deposit
Reservoir and the sorting technique of internal storage.External memory is typically magnetic medium or CD etc., can preserve information for a long time.Internal memory refers to main
Memory unit on plate, is used for depositing the data and program being currently executing, but is only used for temporarily depositing program and data, close
Closing power supply or power-off, data can be lost.
In integrated circuit technology manufacturing process, the parameter each property to memorizer such as the size of each structure, material characteristic
Can all have an impact, for determining optimal size, the scheme of material characteristic before memorizer making, use simulation building device to depositing
Reservoir be simulated emulation testing, to obtain preferably device parameters in simulation process, with improve element manufacturing performance and
Efficiency.
Fig. 1 is the simplified diagram of process of memory rear section structure in prior art, in the structure of process of memory back segment
In, form multiple grid over the semiconductor substrate 10, including control gate 14, memory grid 17 and logic gate 19, by
Logic gate 19 on-load voltage, and then control memory grid 17 stores electric charge or release electric charge, thus complete memory element
Carry out editor and data store.In this technology, process of memory rear section structure includes Semiconductor substrate 10, is positioned at Semiconductor substrate
First medium layer on 10 11 and be positioned at the second dielectric layer 12 on first medium layer 11, described first medium layer 11 He
Second dielectric layer 12 is additionally provided with control gate 14, memory grid 17 and logic gate 19, wherein control gate 14 and institute
State and also there is between Semiconductor substrate 10 gate dielectric layer 15, between described memory grid 17 and Semiconductor substrate 10, also have
One insulating barrier 16, is additionally provided with the second insulating barrier 18 between described memory grid 17 and logic gate 19.Its dielectric layer 15,16
With 18 dielectric constant be different from first medium layer 11 and second dielectric layer 12.And back segment emulation construction rule does not allow same water
There are two or more media in flat bed.And the electric capacity that each grid and medium below are constituted has comprised in other models,
Need not back segment parasitic parameter again extract.
Wherein form parasitic capacitance between memory grid 17 and its other metal wire, and memory grid and logic gate it
Between the parasitic capacitance of generation, all memorizer is produced strong influence.
In the process of memory rear section structure that the construction method of prior art builds, the structure such as metal level, grid is formed
It is all to overlap with this layer of bottom surface time in dielectric layer, i.e. " stands " and on preceding layer, therefore cannot build and be suspended in a certain layer
Simulation architecture, i.e. cannot emulation logic grid with memory grid be suspended in the structure in first medium layer and second dielectric layer.
As in figure 2 it is shown, the simplified diagram of the process of memory rear section structure of the construction method structure that it is prior art.Prior art
In construction method can only in Semiconductor substrate 20 first medium layer 21, second dielectric layer 22 and control gate 24, control
Grid 24 is formed in described Semiconductor substrate 24, i.e. " stands " on Semiconductor substrate 20, and cannot emulate at structure
Cheng Zhong, construction logic grid is suspended in the structure in first medium layer and second dielectric layer with memory grid, thus simulation process
In cannot detect the electric capacity (PIP, poly-insulator-poly) between logic gate and memory grid, memory grid and phase
The actual output parameter information such as the electric capacity (PPS, poly=poly-silicon) between adjacent metal level, cause simulation result to be forbidden
Really.
Summary of the invention
The technical problem to be solved in the present invention is to provide simulation building method and the simulation building dress of a kind of memory construction
Putting, in building simulation process, construction logic grid is suspended in the knot in first medium layer and second dielectric layer with memory grid
Structure, to obtain simulation result more accurately.
For solve the problems referred to above, the present invention provides a kind of simulation building method of process of memory rear section structure, including with
Lower step:
Setting up base structure, described base structure includes the most successively: the first insulating barrier, first medium layer, second
Dielectric layer and the first metal layer, also include first grid, and the bottom surface of described first grid is heavy with the bottom surface of described first insulating barrier
Close；
Set up simulation architecture, first medium layer described in described base structure is divided into first point of dielectric layer and second point
Dielectric layer, is divided into described second dielectric layer the 3rd point of dielectric layer and the 4th point of dielectric layer, and increases second grid and the 3rd
Grid, the bottom surface of described second grid overlaps with second point of dielectric layer bottom surface, described 3rd grid bottom surface and the 4th point of dielectric layer
Overlapping, described 3rd grid is positioned at directly over second grid；
Setup parameter, sets the parameter of described simulation architecture；
Output simulation result.
Further, described first grid is control gate, and second grid is memory grid, and the 3rd grid is logic gate
Pole.
Further, the parameter of described simulation architecture includes first medium layer and the thickness of second dielectric layer, dielectric constant,
First point of dielectric layer to the thickness of the 4th point of dielectric layer, described first grid, second grid and the thickness of the 3rd grid, width with
And square resistance.
The present invention also provides for a kind of simulation building device for process of memory rear section structure, including:
Base structure sets up module, is used for setting up base structure, and described base structure includes the most successively: first is situated between
Matter layer, second dielectric layer and the first metal layer, also include first grid, the bottom surface of described first grid and described first medium layer
Bottom surface overlaps；
Module set up by simulation architecture, sets up module by signal with base structure and is connected, and is used for setting up simulation architecture, by described base
First medium layer described in plinth structure is divided into first point of dielectric layer and second point of dielectric layer, described second dielectric layer is divided into
3rd point of dielectric layer and the 4th point of dielectric layer, and increase second grid and the 3rd grid, the bottom surface of described second grid and second
Dividing dielectric layer bottom surface to overlap, described 3rd grid bottom surface overlaps with the 4th point of dielectric layer, and wherein, described 3rd grid is positioned at second
Directly over grid；
Parameter setting module, sets up module by signal with simulation architecture and is connected, for setting the parameter of described simulation architecture；
Emulation testing module, sets up module by signal with simulation architecture and is connected, and is analyzed simulation result, comparison.
Further, described first grid is control gate, and second grid is memory grid, and the 3rd grid is logic gate
Pole.
Further, the parameter of described simulation architecture includes first medium layer and the thickness of second dielectric layer, dielectric constant,
First point of dielectric layer to the thickness of the 4th point of dielectric layer, described first grid, second grid and the thickness of the 3rd grid, width with
And square resistance.
In sum, the present invention by a kind of simulation building method of foundation and sets up simulation architecture for this emulation mode,
By the second dielectric layer in base structure being divided at least four layers of points of dielectric layers, the bottom surface of described second grid and second point
Dielectric layer bottom surface overlaps, and described 3rd grid bottom surface overlaps with the 4th point of dielectric layer, thus defines second grid and the 3rd grid
Pole " suspends " in the simulation architecture of second dielectric layer, i.e. avoids violating simulation architecture and is necessary for same material about same layer medium
Requirement, the accurate location of each grid can be reflected again strictly according to the facts such that it is able to obtain output characteristics parameter accurately, improve emulation
The verity of result and accuracy.
Accompanying drawing explanation
Fig. 1 is the simplified diagram of process of memory rear section structure in prior art.
Fig. 2 is the simplified diagram of the process of memory rear section structure of the construction method structure of prior art.
Fig. 3 is the brief schematic flow sheet of simulation building method in one embodiment of the invention.
Fig. 4 is the brief knot of the base structure of process of memory back segment during the simulation building in one embodiment of the invention
Structure schematic diagram.
Fig. 5 be one embodiment of the invention simulation building during the brief configuration of simulation architecture of process of memory back segment
Schematic diagram.
Fig. 6 is the brief module diagram of simulation building device in one embodiment of the invention.
Detailed description of the invention
For making present disclosure more clear understandable, below in conjunction with Figure of description, present disclosure is made into one
Step explanation.Certainly the invention is not limited in this specific embodiment, the general replacement known to those skilled in the art is also
Contain within the scope of the present invention.
Secondly, the present invention utilizes schematic diagram to carry out detailed statement, when describing present example in detail, for the ease of saying
Bright, schematic diagram, should be in this, as limitation of the invention not according to general ratio partial enlargement.
Fig. 3 is the brief schematic flow sheet of simulation building method in one embodiment of the invention.As it is shown on figure 3, the present invention carries
For a kind of simulation building method of process of memory rear section structure, comprise the following steps:
S01: set up base structure, as shown in Figure 4, Fig. 4 is memory during the simulation building in one embodiment of the invention
The brief configuration schematic diagram of the base structure of body technology back segment.
Described base structure includes the most successively: the first insulating barrier 105, first medium layer 101, second dielectric layer
102 and the first metal layer 103, also include first grid 104, the bottom surface of described first grid 104 and described first insulating barrier 105
Bottom surface overlap；Described base structure is formed at above substrate 100, and described substrate 100 can be with Semiconductor substrate or a upper medium
Layer, the bottom surface of described first grid 104 and described first insulating barrier 105 bottom surface overlap, i.e. form described first grid 104
By the first insulating barrier 105 " standing " above substrate 105.
S02: set up simulation architecture, as it is shown in figure 5, memory body work during the simulation building that it is one embodiment of the invention
The brief configuration schematic diagram of the simulation architecture of skill back segment.First medium layer in base structure described in step S01 is divided into 2
Dielectric layer, is followed successively by first point of dielectric layer 101a, second point of dielectric layer 101b, from the bottom to top by described second dielectric layer 102 strokes
It is divided into 2 points of dielectric layers, is followed successively by the 3rd point of dielectric layer 102a, the 4th point of dielectric layer 102b from the bottom to top, and increases second gate
Pole 107 and the 3rd grid 109, the bottom surface of described second grid 107 overlaps with second point of dielectric layer 101b bottom surface, described 3rd grid
Bottom surface, pole 109 overlaps with the 4th point of dielectric layer 102b, and described 3rd grid 109 is positioned at directly over second grid 107；Wherein said
First grid is control gate, and second grid is memory grid, and the 3rd grid is logic gate, so that second grid 107 He
3rd grid 109 " suspension " is in first medium layer 101 and second dielectric layer 102, thus is obtained in that in simulation process
Electric capacity (PIP, poly-insulator-poly), second grid 106 and adjacent gold between two grids 107 and the 3rd grid 109
The actual output parameter information such as the electric capacity (PPS, poly=poly-silicon) between genus layer, it is thus achieved that emulate comprehensively and accurately
Result.
S03: setup parameter, sets the parameter of described simulation architecture；Wherein, the parameter of described simulation architecture includes first Jie
Matter layer 101 and the thickness of second dielectric layer 102, dielectric constant, described first point of dielectric layer divides the thickness of dielectric layer, institute to N
State first grid 104, second grid 107 and thickness, width and the square resistance of the 3rd grid 109.
S04: Output simulation result, in this step, emulates simulation architecture input pre-signal, it is thus achieved that characteristic exports
The simulation result of parameter.
As shown in Figure 6, it is the brief module diagram of simulation building device in one embodiment of the invention, and combines Fig. 4
～Fig. 5, the present invention also provides for the simulation building device of a kind of process of memory rear section structure, including:
Base structure sets up module 10, is used for setting up base structure, and described base structure includes the most successively: first
Insulating barrier 105, first medium layer 101, second dielectric layer 102 and the first metal layer 103, also include first grid 104, described
The bottom surface of one grid 104 overlaps with the bottom surface of described first insulating barrier 105；Described base structure is formed at above substrate 100, institute
Stating substrate 100 can be with Semiconductor substrate or a upper dielectric layer, the bottom surface of described first grid 104 and described first insulating barrier 105
Bottom surface overlap, i.e. form described first grid 104 by the first insulating barrier 105 " standing " above substrate 105.
Module 30 set up by simulation architecture, sets up module 10 signal with base structure and is connected, by described base structure first
Dielectric layer is divided into 2 dielectric layers, is followed successively by first point of dielectric layer 101a, second point of dielectric layer 101b from the bottom to top, by described
Second dielectric layer 102 is divided into 2 points of dielectric layers, is followed successively by the 3rd point of dielectric layer 102a, the 4th point of dielectric layer from the bottom to top
102b, and increase second grid 107 and the 3rd grid 109, at the bottom of the bottom surface of described second grid 107 and second point of dielectric layer 101b
Face overlaps, and described 3rd grid 109 bottom surface overlaps with the 4th point of dielectric layer 102b, and described 3rd grid 109 is positioned at second grid
Directly over 107；Wherein said first grid is control gate, and second grid is memory grid, and the 3rd grid is logic gate, from
And make second grid 107 and the 3rd grid 109 " suspension " in first medium layer 101 and second dielectric layer 102, thus emulation
During be obtained in that between second grid 107 and the 3rd grid 109 electric capacity (PIP, poly-insulator-poly),
The actual output parameter information such as the electric capacity (PPS, poly=poly-silicon) between two grids 106 and adjacent metal, obtain
Obtain simulation result comprehensively and accurately.
Parameter setting module 20, sets up module 30 signal and is connected with simulation architecture, for setting the ginseng of described simulation architecture
Number；Wherein, the parameter of described simulation architecture includes first medium layer 101 and the thickness of second dielectric layer 102, dielectric constant, institute
State first point of dielectric layer and divide the thickness of dielectric layer to N, described first grid 104, second grid 107 and the 3rd grid 109
Thickness, width and square resistance.
Emulation testing module 40, sets up module 30 signal and is connected with simulation architecture, to simulation result input stimulus source signal,
And to obtain characteristic output parameter be analyzed, comparison.
In sum, the present invention is by setting up a kind of simulation building method and simulation building device, by described base structure
Described in first medium layer be divided into first point of dielectric layer and second point of dielectric layer, described second dielectric layer is divided into the 3rd point
Dielectric layer and the 4th point of dielectric layer, and increase second grid and the 3rd grid, the bottom surface of described second grid and second point of medium
Layer bottom surface overlaps, and described 3rd grid bottom surface overlaps with the 4th point of dielectric layer, and stating second grid is memory grid, and the 3rd grid is
Logic gate, forms second grid and the 3rd grid " suspends " in the simulation architecture of second dielectric layer, thus defines second gate
Pole and the 3rd grid " suspend " in the simulation architecture of second dielectric layer, i.e. avoid violating simulation architecture necessary about same layer medium
For the requirement of same material, the accurate location of each grid can be reflected again strictly according to the facts such that it is able to obtain output characteristics ginseng accurately
Number, improves verity and the accuracy of simulation result.
Although the present invention is disclosed above with preferred embodiment, so it is not limited to the present invention, any affiliated technology
Field has usually intellectual, without departing from the spirit and scope of the present invention, when making a little change and retouching, therefore
Protection scope of the present invention is when being as the criterion depending on those as defined in claim.
Claims (4)
1. the simulation building method of a process of memory rear section structure, it is characterised in that comprise the following steps:
Setting up base structure, described base structure includes the most successively: the first insulating barrier, first medium layer, second medium
Layer and the first metal layer, also include that first grid, the bottom surface of described first grid overlap with the bottom surface of described first insulating barrier, institute
Stating first grid is control gate；
Set up simulation architecture, first medium layer described in described base structure is divided into first point of dielectric layer and second point of medium
Layer, is divided into described second dielectric layer the 3rd point of dielectric layer and the 4th point of dielectric layer, and increases second grid and the 3rd grid,
Described second grid is memory grid, and described 3rd grid is logic gate, the bottom surface of described second grid and second point of medium
Layer bottom surface overlaps, and described 3rd grid bottom surface overlaps with the 4th point of dielectric layer, and described 3rd grid is positioned at directly over second grid；
Setup parameter, sets the parameter of described simulation architecture；
Output simulation result.
2. the simulation building method of process of memory rear section structure as claimed in claim 1, it is characterised in that described emulation is tied
The parameter of structure includes first medium layer and the thickness of second dielectric layer, dielectric constant, and first point of dielectric layer is to the 4th point of dielectric layer
Thickness, described first grid, second grid and thickness, width and the square resistance of the 3rd grid.
3. the simulation building device for process of memory rear section structure, it is characterised in that including:
Base structure sets up module, is used for setting up base structure, and described base structure includes the most successively: first medium
Layer, second dielectric layer and the first metal layer, also include at the bottom of first grid, the bottom surface of described first grid and described first medium layer
Face overlaps, and described first grid is control gate；
Module set up by simulation architecture, sets up module by signal with base structure and is connected, and is used for setting up simulation architecture, by described basis knot
First medium layer described in structure is divided into first point of dielectric layer and second point of dielectric layer, and described second dielectric layer is divided into the 3rd
Point dielectric layer and the 4th point of dielectric layer, and increase second grid and the 3rd grid, described second grid is memory grid, described the
Three grids are logic gate, and the bottom surface of described second grid overlaps with second point of dielectric layer bottom surface, described 3rd grid bottom surface with
4th point of dielectric layer overlaps, and wherein, described 3rd grid is positioned at directly over second grid；
Parameter setting module, sets up module by signal with simulation architecture and is connected, for setting the parameter of described simulation architecture；
Emulation testing module, sets up module by signal with simulation architecture and is connected, and is analyzed simulation result, comparison.
4. the simulation building device for process of memory rear section structure as claimed in claim 3, it is characterised in that described imitative
The parameter of true structure includes first medium layer and the thickness of second dielectric layer, dielectric constant, and first point of dielectric layer is to the 4th point of Jie
The thickness of matter layer, described first grid, second grid and thickness, width and the square resistance of the 3rd grid.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110388699.XA CN102508983B (en) | 2011-11-29 | The simulation building method of process of memory rear section structure and simulation building device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110388699.XA CN102508983B (en) | 2011-11-29 | The simulation building method of process of memory rear section structure and simulation building device |
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| Publication Number | Publication Date |
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| CN102508983A CN102508983A (en) | 2012-06-20 |
| CN102508983B true CN102508983B (en) | 2016-12-14 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1385903A (en) * | 2001-05-16 | 2002-12-18 | 华邦电子股份有限公司 | Non-volatility memory and making technology thereof |
| CN1619817A (en) * | 2003-11-12 | 2005-05-25 | 三星电子株式会社 | Semiconductor devices having different gate dielectrics and methods for manufacturing the same |
| US7693700B1 (en) * | 2003-05-09 | 2010-04-06 | Altera Corporation | Caching technique for electrical simulation of VLSI interconnect |
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1385903A (en) * | 2001-05-16 | 2002-12-18 | 华邦电子股份有限公司 | Non-volatility memory and making technology thereof |
| US7693700B1 (en) * | 2003-05-09 | 2010-04-06 | Altera Corporation | Caching technique for electrical simulation of VLSI interconnect |
| CN1619817A (en) * | 2003-11-12 | 2005-05-25 | 三星电子株式会社 | Semiconductor devices having different gate dielectrics and methods for manufacturing the same |
Non-Patent Citations (1)
| Title |
|---|
| 纳米晶浮栅结构先进存储器的研究与模拟;宁润苏;《中国优秀硕士学位论文全文数据库 信息科技辑（月刊）》;20091115;第2009年卷(第11期);第I137-33页 * |
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