CN102508983A - Simulation construction method and device of back-end structure of process of memory - Google Patents
Simulation construction method and device of back-end structure of process of memory Download PDFInfo
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Abstract
The invention relates to a simulation construction method of a back-end structure of a process of a memory, and a simulation construction device established against the simulation construction method. A simulation structure capable of enabling a second gate and a third gate to suspend at a second dielectric layer is formed by dividing the second dielectric layer in a foundation structure into at least four sub-dielectric layers, superposing the bottom surface of the second gate with the bottom surface of the second sub-dielectric layer, and superposing the bottom surface of the third gate with the fourth sub-dielectric layer, so that the requirement that the simulation structure needs to be made of the same material about the same dielectric layer can be prevented from being violated, the accurate positions of all the gates can be truly reflected, accurate output property parameters can be further obtained and authenticity and accuracy in simulation results can be improved.
Description
Technical field
The present invention relates to a kind of emulation construction method and emulation construction device, relate in particular to the emulation construction method and the emulation construction device of the emulation construction method of segment structure after a kind of memory body technology.
Background technology
Storer (Memory) is the memory device in the computer system, is used for depositing program and data.Full detail in the computing machine comprises that raw data, computer program, middle operation result and the final operation result of input all is kept in the storer.It deposits in and taking-up information according to the controller appointed positions.Storer has been arranged, and computing machine just has memory function, could guarantee operate as normal.Can be divided into primary memory (internal memory) and supplementary storage (external memory) by the purposes storer, the sorting technique that is divided into external memory storage and internal storage is also arranged.External memory is magnetic medium or CD etc. normally, can long preservation information.Internal memory refers to the memory unit on the mainboard, is used for depositing current data of carrying out and program, but only is used for temporarily depositing program and data, powered-down or outage, and data can be lost.
In integrated circuit technology manufacturing process; Parameters such as the size of each structure, material characteristic are all influential to each performance of storer; For before making storer, confirming best size, the scheme of material characteristic; Adopt the emulation construction device that storer is carried out the analog simulation test, in simulation process, to obtain preferable device parameters, to improve the performance and the efficient of element manufacturing.
Fig. 1 is the simplified diagram of segment structure after the memory body technology in the prior art; In the structure of memory body technology back segment; On Semiconductor substrate 10, form a plurality of grids, comprise control grid 14, memory grid 17 and logic gate 19, through at logic gate 19 on-load voltages; And then control stored charge or release electric charge in the memory grid 17, thereby accomplish storage unit is edited and data storage.In this technology after the memory body technology segment structure comprise Semiconductor substrate 10; Be positioned at first dielectric layer 11 on the Semiconductor substrate 10 and be positioned at second dielectric layer 12 on first dielectric layer 11; In said first dielectric layer 11 and second dielectric layer 12, also be provided with control grid 14, memory grid 17 and logic gate 19; Wherein control between grid 14 and the said Semiconductor substrate 10 and also have gate dielectric layer 15; Also have first insulation course 16 between said memory grid 17 and the Semiconductor substrate 10, also be provided with second insulation course 18 between said memory grid 17 and the logic gate 19.Wherein dielectric layer 15,16 and 18 specific inductive capacity are different from first dielectric layer 11 and second dielectric layer 12.And back segment emulation construction rule does not allow same flat seam two or more media to occur.And each grid and the electric capacity that medium constituted below it have comprised in other models, do not need the back segment parasitic parameter to extract once more.
Wherein remember between the other metal wire of grid 17 and its and form stray capacitance, and the stray capacitance of the generation between memory grid and the logic gate, all storer is produced influence greatly.
After the memory body technology that the construction method of prior art makes up in the segment structure; All be to overlap when structure such as metal level, grid is formed in the dielectric layer with this layer bottom surface; Promptly " stand " with preceding one deck on; So can't make up the simulation architecture that is suspended in certain one deck, promptly can't be suspended in the structure in first dielectric layer and second dielectric layer with the memory grid by the emulation logic grid.As shown in Figure 2, it is the simplified diagram of segment structure after the memory body technology that makes up of the construction method of prior art.Construction method of the prior art can only be on Semiconductor substrate 20 first dielectric layer 21, second dielectric layer 22 and control grid 24; Control grid 24 is formed on the said Semiconductor substrate 24; Promptly " stand " on Semiconductor substrate 20, and can't be in making up simulation process, the construction logic grid is suspended in the structure in first dielectric layer and second dielectric layer with the memory grid; Thereby can't detect the electric capacity (PIP between logic gate and the memory grid in the simulation process; Poly-insulator-poly), (PPS, poly=poly-silicon) etc. actual output parameter information causes simulation result inaccurate to the electric capacity between memory grid and the adjacent metal.
Summary of the invention
The technical matters that the present invention will solve is; A kind of emulation construction method and emulation construction device of memory construction are provided; In making up simulation process, the construction logic grid is suspended in the structure in first dielectric layer and second dielectric layer with the memory grid, to obtain simulation result more accurately.
For addressing the above problem, the present invention provides the emulation construction method of segment structure after a kind of memory body technology, may further comprise the steps:
Set up foundation structure, said foundation structure comprises from the bottom to top successively: first insulation course, first dielectric layer, second dielectric layer and the first metal layer, also comprise first grid, and the bottom surface of said first grid overlaps with the bottom surface of said first insulation course;
Set up simulation architecture; First dielectric layer described in the said foundation structure is divided into first fen dielectric layer and second fen dielectric layer; Said second dielectric layer is divided into the 3rd fen dielectric layer and the 4th fen dielectric layer, and increases second grid and the 3rd grid, the bottom surface of said second grid overlaps with second fen dielectric layer bottom surface; Said the 3rd grid bottom surface overlaps with the 4th fen dielectric layer, and said the 3rd grid is positioned at directly over the second grid;
Setup parameter is set the parameter of said simulation architecture;
The output simulation result.
Further, said first grid is the control grid, and second grid is the memory grid, and the 3rd grid is a logic gate.
Further; The parameter of said simulation architecture comprises thickness, the specific inductive capacity of first dielectric layer and second dielectric layer; The thickness of four fens dielectric layers of first fen dielectric layer to the, thickness, width and the square resistance of said first grid, second grid and the 3rd grid.
The present invention also provides a kind of emulation construction device that is used for segment structure after the memory body technology, comprising:
Foundation structure is set up module, is used to set up foundation structure, and said foundation structure comprises from the bottom to top successively: first dielectric layer, second dielectric layer and the first metal layer, also comprise first grid, and the bottom surface of said first grid overlaps with the said first dielectric layer bottom surface;
Simulation architecture is set up module; Set up module by signal with foundation structure and link to each other, be used to set up simulation architecture, first dielectric layer described in the said foundation structure is divided into first fen dielectric layer and second fen dielectric layer; Said second dielectric layer is divided into the 3rd fen dielectric layer and the 4th fen dielectric layer; And increase second grid and the 3rd grid, and the bottom surface of said second grid overlaps with second fen dielectric layer bottom surface, and said the 3rd grid bottom surface overlaps with the 4th fen dielectric layer; Wherein, said the 3rd grid is positioned at directly over the second grid;
Parameter setting module is set up module by signal with simulation architecture and is linked to each other, and is used to set the parameter of said simulation architecture;
The emulation testing module is set up module by signal with simulation architecture and is linked to each other, and simulation result is analyzed, compared.
Further, said first grid is the control grid, and second grid is the memory grid, and the 3rd grid is a logic gate.
Further; The parameter of said simulation architecture comprises thickness, the specific inductive capacity of first dielectric layer and second dielectric layer, the thickness of four fens dielectric layers of first fen dielectric layer to the, thickness, width and the square resistance of said first grid, second grid and the 3rd grid.
In sum; The present invention is through setting up a kind of emulation construction method and setting up simulation architecture to this emulation mode, and through second dielectric layer in the foundation structure is divided at least four layers of branch dielectric layer, the bottom surface of said second grid overlaps with second fen dielectric layer bottom surface; Said the 3rd grid bottom surface overlaps with the 4th fen dielectric layer; Thereby formed second grid and the 3rd grid " suspension " in the simulation architecture of second dielectric layer, promptly avoided violating simulation architecture, can reflect the accurate position of each grid again strictly according to the facts about be necessary for the requirement of same material with one deck medium; Thereby can obtain output characteristics parameter accurately, improve the authenticity and the accuracy of simulation result.
Description of drawings
Fig. 1 is the simplified diagram of segment structure after the memory body technology in the prior art.
Fig. 2 is the simplified diagram of segment structure after the memory body technology that makes up of the construction method of prior art.
Fig. 3 is the concise and to the point schematic flow sheet of emulation construction method in one embodiment of the invention.
Fig. 4 is the brief configuration synoptic diagram of the foundation structure of memory body technology back segment in the emulation building process in one embodiment of the invention.
Fig. 5 is the brief configuration synoptic diagram of the simulation architecture of memory body technology back segment in the emulation building process of one embodiment of the invention.
Fig. 6 is the concise and to the point module diagram of emulation construction device in one embodiment of the invention.
Embodiment
For making content of the present invention clear more understandable,, content of the present invention is described further below in conjunction with Figure of description.Certainly the present invention is not limited to this specific embodiment, and the general replacement that those skilled in the art knew also is encompassed in protection scope of the present invention.
Secondly, the present invention utilizes synoptic diagram to carry out detailed statement, and when instance of the present invention was detailed, for the ease of explanation, synoptic diagram did not amplify according to general ratio is local, should be with this as to qualification of the present invention.
Fig. 3 is the concise and to the point schematic flow sheet of emulation construction method in one embodiment of the invention.As shown in Figure 3, the present invention provides the emulation construction method of segment structure after a kind of memory body technology, may further comprise the steps:
S01: set up foundation structure, as shown in Figure 4, Fig. 4 is the brief configuration synoptic diagram of the foundation structure of memory body technology back segment in the emulation building process in one embodiment of the invention.
Said foundation structure comprises from the bottom to top successively: first insulation course 105, first dielectric layer 101, second dielectric layer 102 and the first metal layer 103, also comprise first grid 104, and the bottom surface of said first grid 104 overlaps with the bottom surface of said first insulation course 105; Said foundation structure is formed at substrate 100 tops; Said substrate 100 can a Semiconductor substrate or a last dielectric layer; The bottom surface of said first grid 104 and said first insulation course 105 the bottom surface overlap, promptly form said first grid 104 and " stand " in substrate 105 tops through first insulation course 105.
S02: set up simulation architecture, as shown in Figure 5, it is the brief configuration synoptic diagram of the simulation architecture of memory body technology back segment in the emulation building process of one embodiment of the invention.First dielectric layer in the foundation structure described in the step S01 is divided into 2 dielectric layers; Be followed successively by first fen dielectric layer 101a, second fen dielectric layer 101b from the bottom to top; Said second dielectric layer 102 is divided into 2 branch dielectric layers; Be followed successively by the 3rd fen dielectric layer 102a, the 4th fen dielectric layer 102b from the bottom to top, and increase second grid 107 and the 3rd grid 109, the bottom surface of said second grid 107 overlaps with second fen dielectric layer 101b bottom surface; Said the 3rd grid 109 bottom surfaces overlap with the 4th fen dielectric layer 102b, and said the 3rd grid 109 is positioned at directly over the second grid 107; Wherein said first grid is the control grid; Second grid is the memory grid; The 3rd grid is a logic gate; Thereby make second grid 107 and the 3rd grid 109 " suspension " in first dielectric layer 101 and second dielectric layer 102, thus in simulation process, can obtain between second grid 107 and the 3rd grid 109 electric capacity (PIP, poly-insulator-poly), the electric capacity (PPS between second grid 106 and the adjacent metal; Poly=poly-silicon) etc. actual output parameter information obtains simulation result comprehensively and accurately.
S03: setup parameter, set the parameter of said simulation architecture; Wherein, The parameter of said simulation architecture comprises thickness, the specific inductive capacity of first dielectric layer 101 and second dielectric layer 102; Said first minute dielectric layer to the N divides the thickness of dielectric layer, thickness, width and the square resistance of said first grid 104, second grid 107 and the 3rd grid 109.
S04: the output simulation result, in this step, carry out emulation, the simulation result of acquired character output parameter to simulation architecture input pre-signal.
As shown in Figure 6, it is the concise and to the point module diagram of emulation construction device in one embodiment of the invention, and combines Fig. 4～Fig. 5, the present invention that the emulation construction device of segment structure after a kind of memory body technology also is provided, and comprising:
Foundation structure is set up module 10; Be used to set up foundation structure; Said foundation structure comprises from the bottom to top successively: first insulation course 105, first dielectric layer 101, second dielectric layer 102 and the first metal layer 103; Also comprise first grid 104, the bottom surface of said first grid 104 overlaps with the bottom surface of said first insulation course 105; Said foundation structure is formed at substrate 100 tops; Said substrate 100 can a Semiconductor substrate or a last dielectric layer; The bottom surface of said first grid 104 and said first insulation course 105 the bottom surface overlap, promptly form said first grid 104 and " stand " in substrate 105 tops through first insulation course 105.
Simulation architecture is set up module 30; Set up module 10 signals with foundation structure and link to each other, first dielectric layer in the said foundation structure is divided into 2 dielectric layers, be followed successively by first fen dielectric layer 101a, second fen dielectric layer 101b from the bottom to top; Said second dielectric layer 102 is divided into 2 branch dielectric layers; Be followed successively by the 3rd fen dielectric layer 102a, the 4th fen dielectric layer 102b from the bottom to top, and increase second grid 107 and the 3rd grid 109, the bottom surface of said second grid 107 overlaps with second fen dielectric layer 101b bottom surface; Said the 3rd grid 109 bottom surfaces overlap with the 4th fen dielectric layer 102b, and said the 3rd grid 109 is positioned at directly over the second grid 107; Wherein said first grid is the control grid; Second grid is the memory grid; The 3rd grid is a logic gate; Thereby make second grid 107 and the 3rd grid 109 " suspension " in first dielectric layer 101 and second dielectric layer 102, thus in simulation process, can obtain between second grid 107 and the 3rd grid 109 electric capacity (PIP, poly-insulator-poly), the electric capacity (PPS between second grid 106 and the adjacent metal; Poly=poly-silicon) etc. actual output parameter information obtains simulation result comprehensively and accurately.
In sum, the present invention is divided into first fen dielectric layer and second fen dielectric layer through setting up a kind of emulation construction method and emulation construction device with first dielectric layer described in the said foundation structure; Said second dielectric layer is divided into the 3rd fen dielectric layer and the 4th fen dielectric layer; And increase second grid and the 3rd grid, and the bottom surface of said second grid overlaps with second fen dielectric layer bottom surface, and said the 3rd grid bottom surface overlaps with the 4th fen dielectric layer; State second grid and be the memory grid; The 3rd grid is a logic gate, forms second grid and the 3rd grid " suspension " in the simulation architecture of second dielectric layer, thereby has formed second grid and the 3rd grid " suspension " in the simulation architecture of second dielectric layer; Promptly avoid violating simulation architecture about be necessary for the requirement of same material with one deck medium; Can reflect the accurate position of each grid strictly according to the facts again, thereby can obtain output characteristics parameter accurately, improve the authenticity and the accuracy of simulation result.
Though the present invention discloses as above with preferred embodiment; Right its is not in order to limit the present invention; Has common knowledge the knowledgeable in the technical field under any; Do not breaking away from the spirit and scope of the present invention, when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (6)
1. the emulation construction method of segment structure after the memory body technology is characterized in that, may further comprise the steps:
Set up foundation structure, said foundation structure comprises from the bottom to top successively: first insulation course, first dielectric layer, second dielectric layer and the first metal layer, also comprise first grid, and the bottom surface of said first grid overlaps with the bottom surface of said first insulation course;
Set up simulation architecture; First dielectric layer described in the said foundation structure is divided into first fen dielectric layer and second fen dielectric layer; Said second dielectric layer is divided into the 3rd fen dielectric layer and the 4th fen dielectric layer, and increases second grid and the 3rd grid, the bottom surface of said second grid overlaps with second fen dielectric layer bottom surface; Said the 3rd grid bottom surface overlaps with the 4th fen dielectric layer, and said the 3rd grid is positioned at directly over the second grid;
Setup parameter is set the parameter of said simulation architecture;
The output simulation result.
2. the emulation construction method of segment structure is characterized in that after the memory body technology as claimed in claim 1, and said first grid is the control grid, and second grid is the memory grid, and the 3rd grid is a logic gate.
3. like the emulation construction method of segment structure after claim 1 or the 4 described memory body technologies; It is characterized in that; The parameter of said simulation architecture comprises thickness, the specific inductive capacity of first dielectric layer and second dielectric layer; The thickness of four fens dielectric layers of first fen dielectric layer to the, thickness, width and the square resistance of said first grid, second grid and the 3rd grid.
4. an emulation construction device that is used for segment structure after the memory body technology is characterized in that, comprising:
Foundation structure is set up module, is used to set up foundation structure, and said foundation structure comprises from the bottom to top successively: first dielectric layer, second dielectric layer and the first metal layer, also comprise first grid, and the bottom surface of said first grid overlaps with the said first dielectric layer bottom surface;
Simulation architecture is set up module; Set up module by signal with foundation structure and link to each other, be used to set up simulation architecture, first dielectric layer described in the said foundation structure is divided into first fen dielectric layer and second fen dielectric layer; Said second dielectric layer is divided into the 3rd fen dielectric layer and the 4th fen dielectric layer; And increase second grid and the 3rd grid, and the bottom surface of said second grid overlaps with second fen dielectric layer bottom surface, and said the 3rd grid bottom surface overlaps with the 4th fen dielectric layer; Wherein, said the 3rd grid is positioned at directly over the second grid;
Parameter setting module is set up module by signal with simulation architecture and is linked to each other, and is used to set the parameter of said simulation architecture;
The emulation testing module is set up module by signal with simulation architecture and is linked to each other, and simulation result is analyzed, compared.
5. the emulation construction device of segment structure is characterized in that after the memory body technology as claimed in claim 5, and said first grid is the control grid, and second grid is the memory grid, and the 3rd grid is a logic gate.
6. like the emulation construction method of segment structure after claim 4 or the 6 described memory body technologies; It is characterized in that; The parameter of said simulation architecture comprises thickness, the specific inductive capacity of first dielectric layer and second dielectric layer; The thickness of four fens dielectric layers of first fen dielectric layer to the, thickness, width and the square resistance of said first grid, second grid and the 3rd grid.
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| CN201110388699.XA CN102508983B (en) | 2011-11-29 | The simulation building method of process of memory rear section structure and simulation building device |
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| CN201110388699.XA CN102508983B (en) | 2011-11-29 | The simulation building method of process of memory rear section structure and simulation building device |
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| CN102508983A true CN102508983A (en) | 2012-06-20 |
| CN102508983B CN102508983B (en) | 2016-12-14 |
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| US7693700B1 (en) * | 2003-05-09 | 2010-04-06 | Altera Corporation | Caching technique for electrical simulation of VLSI interconnect |
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1385903A (en) * | 2001-05-16 | 2002-12-18 | 华邦电子股份有限公司 | Non-volatility memory and making technology thereof |
| US7693700B1 (en) * | 2003-05-09 | 2010-04-06 | Altera Corporation | Caching technique for electrical simulation of VLSI interconnect |
| CN1619817A (en) * | 2003-11-12 | 2005-05-25 | 三星电子株式会社 | Semiconductor devices having different gate dielectrics and methods for manufacturing the same |
| US20080098342A1 (en) * | 2006-10-20 | 2008-04-24 | Yutaka Yoshimoto | Semiconductor integrated circuit designing method, semiconductor integrated circuit device, and electronic device |
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| 宁润苏: "纳米晶浮栅结构先进存储器的研究与模拟", 《中国优秀硕士学位论文全文数据库 信息科技辑（月刊）》 * |
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