CN102468428A - Manufacture method of phase transition random memory - Google Patents
Manufacture method of phase transition random memory Download PDFInfo
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- CN102468428A CN102468428A CN201010534163XA CN201010534163A CN102468428A CN 102468428 A CN102468428 A CN 102468428A CN 201010534163X A CN201010534163X A CN 201010534163XA CN 201010534163 A CN201010534163 A CN 201010534163A CN 102468428 A CN102468428 A CN 102468428A
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- temperature oxide
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 238000000034 method Methods 0.000 title claims abstract description 16
- 230000015654 memory Effects 0.000 title claims abstract description 5
- 230000007704 transition Effects 0.000 title abstract description 8
- 230000004888 barrier function Effects 0.000 claims abstract description 63
- 238000005530 etching Methods 0.000 claims abstract description 47
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 27
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 27
- 239000004065 semiconductor Substances 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000012782 phase change material Substances 0.000 claims description 38
- 238000001312 dry etching Methods 0.000 claims description 7
- 239000004568 cement Substances 0.000 claims description 5
- 239000002131 composite material Substances 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 5
- 239000002253 acid Substances 0.000 claims description 3
- 239000003795 chemical substances by application Substances 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims 1
- 238000000151 deposition Methods 0.000 abstract description 5
- 239000000463 material Substances 0.000 abstract description 5
- 238000005468 ion implantation Methods 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 8
- 150000004767 nitrides Chemical class 0.000 description 8
- 230000008859 change Effects 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 238000003860 storage Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229910052714 tellurium Inorganic materials 0.000 description 2
- -1 Chalcogenide compound Chemical class 0.000 description 1
- 244000188472 Ilex paraguariensis Species 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008034 disappearance Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000013011 mating Effects 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- PORWMNRCUJJQNO-UHFFFAOYSA-N tellurium atom Chemical compound [Te] PORWMNRCUJJQNO-UHFFFAOYSA-N 0.000 description 1
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Abstract
The invention provides a manufacture method of a top electrode of a phase transition random memory. The method comprises the following steps: providing a semiconductor substrate, and forming a second insulating layer on the semiconductor substrate, wherein, the second insulating layer is filled with GST phase transition material; depositing a low temperature oxide layer, a silicon nitride layer and a third insulating layer on the second insulating layer and the GST phase transition material in order; etching the third insulating layer and the silicon nitride layer to expose the low temperature oxide layer at a bottom and form an etching hole; carrying out ion implantation processing or plasma processing on the low temperature oxide layer in a bottom of the etching hole; removing the low temperature oxide layer in the bottom of the etching hole; forming the top electrode in the etching hole. According to the invention, the low temperature oxide layer and the silicon nitride layer which are deposited in order are taken as a barrier layer of top electrode etching, when etching the low temperature oxide with a wet method, an etching selectivity ratio larger than 15 is provided between the low temperature oxide layer and the GST phase transition material, thus loss of the GST phase transition material in etching is avoided.
Description
Technical field
The present invention relates to the semiconductor memory technologies field, relate in particular to a kind of manufacturing approach of phase-change random access memory.
Background technology
Phase-change random access memory (phase change random access memory; PCRAM) be to utilize phase change film material to realize a kind of memory of storage being acknowledged as the memory of successfully breaking through 22nm size node the most likely as storage medium.
Chalcogenide compound Ge by germanium (Ge)-antimony (Sb)-tellurium (Te) formation
2Sb
2Te
5(GST), can realize the reversible transition between crystalline state and the amorphous state rapidly, become present PCRAM and go up the most frequently used phase-change material.GST is a low resistance state in crystalline state, is high-resistance state in amorphous state, and the resistance difference of phase transition storage when utilizing GST between crystalline state and amorphous state, to change just realizes storage.
Fig. 1 is the cross-sectional view of present phase change memory device.Like figure; First insulating barrier 101 is enclosed in the side of bottom electrode 102; Second insulating barrier 103 is formed at first insulating barrier 101 and bottom electrode 102 upper surfaces, GST phase-change material 104 be filled in the perforate of second insulating barrier 103 and with bottom electrode 102 centrally aligneds, the 3rd insulating barrier 107 is formed at second insulating barrier, 103 upper surfaces; Top electrode 108 is formed in the perforate of the 3rd insulating barrier 107, and with the perforate of second insulating barrier 103 in GST phase-change material 104 centrally aligneds.
At present, on the GST phase-change material, deposit the loss that one deck barrier layer reduces GST phase-change material in the top electrode etching technics in the top electrode etching technics usually.
As shown in Figure 2, and deposition one deck low-temperature nitride on the GST phase-change material (low temperature nitride, LTN) as the barrier layer in the top electrode etching technics 106, desirable etching effect is as shown in Figure 3, and GST phase-change material 104 is lossless.But the tellurium in the GST phase-change material 104 (Te) can volatilize at 300 ℃; And as shown in Figure 4, in fact, when dry etching removes low-temperature nitride LTN barrier layer 106; Because extremely low etching selection ratio between LTN and the GST; Cause this etch step also to remove a part of GST phase-change material 104 simultaneously, formed GST phase-change material loss region 109, and then top electrode forms time and requires the GST phase-change material process window disappearance of mating.
Because the top electrode etching technics of phase-change random access memory requires better hole etching technics control precision and lower GST phase-change material loss; And the process on deposition one deck low-temperature nitride LTN barrier layer is no longer suitable; So be badly in need of providing a kind of manufacturing approach of new phase-change random access memory; Solve these problems in the etching technics, reduce the technology cost, improve device performance.
Summary of the invention
The object of the present invention is to provide a kind of manufacturing approach of phase-change random access memory; When preparing to solve present top electrode that dry etching removes low-temperature nitride (LTN) barrier layer in the process, extremely low etching selection ratio between LTN and the GST and the GST phase-change material that causes receives the problem of loss.
For addressing the above problem, the present invention proposes a kind of manufacturing approach of phase-change random access memory, and this method comprises the steps:
Semiconductor substrate is provided, is formed with second insulating barrier on the said Semiconductor substrate, be filled with the GST phase-change material in said second insulating barrier;
On said second insulating barrier and GST phase-change material, deposit low temperature oxide layer, silicon nitride layer and the 3rd insulating barrier successively;
Said the 3rd insulating barrier of etching and silicon nitride layer to expose the low temperature oxide layer of bottom, form etched hole successively;
Ion injects to be handled or the interior low temperature oxide layer in Cement Composite Treated by Plasma said etched hole bottom;
Remove the low temperature oxide layer in the said etched hole bottom;
In said etched hole, form top electrode.
Optional, also be provided with first insulating barrier between the said Semiconductor substrate and second insulating barrier, be formed with bottom electrode in said first insulating barrier.
Optional, said GST phase-change material is covered in the bottom electrode upper surface, aims at bottom electrode.
Optional, the deposit thickness of said low temperature oxide layer is 50 dusts～500 dusts.
Optional, the deposit thickness of said silicon nitride layer is 50 dusts～500 dusts.
Optional, the lithographic method of said the 3rd insulating barrier is a dry etching.
Optional, the etching of said the 3rd insulating barrier and silicon nitride layer is vertical etching.
Optional, the method that removes of the low temperature oxide layer in the said etched hole bottom is a wet etching, the etching agent of employing is a fluoric-containing acid.
Compared with prior art, the present invention adopts and to stack gradually low temperature oxide layer and silicon nitride layer as the barrier layer, when wet etching method removes low temperature oxide layer; Have high etching selection ratio between low temperature oxide layer and the GST phase-change material, thereby the loss of GST phase-change material when having avoided etching has improved the controllability of technology; And then kept top electrode better and form time and require the GST phase-change material process window that matees; Technological operation is simple, has reduced the technology cost, has improved device performance.
Description of drawings
Fig. 1 is the cross-sectional view of phase change memory device
Fig. 2 is that the low-temperature nitride LTN layer in the top electrode etching technics of prior art forms the back structural representation;
Fig. 3 is the ideal structure sketch map after the low-temperature nitride LTN layer etching;
Fig. 4 is the practical structures sketch map after the low-temperature nitride LTN layer etching in the prior art;
Fig. 5 is the process chart of the embodiment of the invention;
Fig. 6 A to Fig. 6 F is the cross-sectional view of the embodiment of the invention.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment the manufacturing approach of the phase-change random access memory of the present invention's proposition is done further explain.According to following explanation and claims, advantage of the present invention and characteristic will be clearer.What need explanation is, accompanying drawing all adopts the form of simplifying very much, only is used for conveniently, the purpose of the aid illustration embodiment of the invention lucidly.
As shown in Figure 5, the present invention proposes a kind of manufacturing approach of phase-change random access memory.This method comprises the steps:
S501 provides Semiconductor substrate, is formed with second insulating barrier on the said Semiconductor substrate, is filled with the GST phase-change material in said second insulating barrier;
S502 deposits low temperature oxide layer, silicon nitride layer and the 3rd insulating barrier successively on said second insulating barrier and GST phase-change material;
S503, said the 3rd insulating barrier of etching and silicon nitride layer to expose the low temperature oxide layer of bottom, form etched hole successively;
S504, ion inject and handle or the interior low temperature oxide layer in Cement Composite Treated by Plasma said etched hole bottom;
S505 removes the low temperature oxide layer in the said etched hole bottom;
S506 forms top electrode in said etched hole.
Below in conjunction with Fig. 6 A～6F, the manufacturing approach of above-mentioned phase-change random access memory is explained in detail.
S501 provides Semiconductor substrate, is formed with second insulating barrier on the said Semiconductor substrate, is filled with the GST phase-change material in said second insulating barrier.
With reference to figure 6A, Semiconductor substrate 600 is provided, on said Semiconductor substrate 600, be formed with first insulating barrier 601, bottom electrode 602, second insulating barrier 603 and GST phase-change material 604.Wherein be formed with bottom electrode 602 in first insulating barrier 601; And expose bottom electrode 602 upper surfaces; Second insulating barrier 603 is formed at first insulating barrier 601 and bottom electrode 602 upper surfaces, and GST phase-change material 604 is filled in 603 perforates of second insulating barrier, and covers the upper surface of bottom electrode 602; The perforate of second insulating barrier 603 is aimed at bottom electrode 602, makes the GST phase-change material 604 of filling aim at bottom electrode 602.
S502 deposits low temperature oxide layer, silicon nitride layer and the 3rd insulating barrier successively on said second insulating barrier and GST phase-change material.
With reference to figure 6B, on said second insulating barrier 603 and GST phase-change material 604, deposit low temperature oxide layer 605, silicon nitride layer 606 and the 3rd insulating barrier 607 successively, low temperature oxide layer 605 is 50 dusts～500 dusts with silicon nitride layer 606 deposit thickness.
S503, said the 3rd insulating barrier of etching and silicon nitride layer to expose the low temperature oxide layer of bottom, form etched hole successively.
With reference to figure 6C, adopt dry etching the 3rd insulating barrier 607 to be carried out vertical etching, the filling centrally aligned of the 3rd insulating barrier 607 etching centers and GST phase-change material 604.At this moment, the barrier layer of silicon nitride layer 606 during as etching, the high etching selection ratio of the 3rd insulating barrier 607 and silicon nitride layer 606 makes dry etching stop at the upper surface of silicon nitride layer 606.Then the silicon nitride layer 606 in the 3rd insulating barrier 607 etched holes is carried out the dry etching of vertical direction; Low temperature oxide layer 605 is as the barrier layer of this etching step, the high etching selection ratio between silicon nitride layer 606 and the low temperature oxide layer 605 make etching stopping in the etched hole bottom the upper surface of low temperature oxide layer 304.Silicon nitride layer 606 and low temperature oxide layer 605 have prevented the loss of the GST phase-change material 606 in the etching technics as the barrier layer in this step.
S504, ion inject and handle or the interior low temperature oxide layer in Cement Composite Treated by Plasma said etched hole bottom.
With reference to figure 6D; In the present embodiment; Low temperature oxide layer 605 in the etched hole bottom that forms after the 3rd insulating barrier 607 and silicon nitride layer 606 etchings is carried out ion inject processing (IMP) or Cement Composite Treated by Plasma, make that the low temperature oxide layer 605 inside and outside the etched hole is easy to separating treatment.
S505 removes the low temperature oxide layer in the said etched hole bottom.
With reference to figure 6E, adopt fluoric-containing acid that the low temperature oxide layer 605 in the said etched hole bottom is carried out wet etching in the present embodiment, the etching selection ratio during etching between low temperature oxide layer 605 and the GST phase-change material 604 is greater than 15, and GST phase-change material 604 is lossless.
S506 forms top electrode in said etched hole.
With reference to figure 6F, in the present embodiment, in said etched hole, form top electrode 608, and top electrode 608 and GST phase-change material 604 centrally aligneds, and the upper surface of covering GST phase-change material 604.This step can realize through vapour deposition, also can the top electrode of making in advance directly be inserted in the etched hole and accomplish.
In sum; The present invention adopts the barrier layer when depositing low temperature oxide layer and silicon nitride layer as the top electrode etching successively; The loss of GST phase-change material when the high etching selection ratio (greater than 15) between low temperature oxide layer and the GST phase-change material has been avoided etching has improved the controllability of technology, and technological operation is simple; Reduce the technology cost, improved device performance.
Obviously, those skilled in the art can carry out various changes and modification to invention and not break away from the spirit and scope of the present invention.Like this, belong within the scope of claim of the present invention and equivalent technologies thereof if of the present invention these are revised with modification, then the present invention also is intended to comprise these changes and modification interior.
Claims (9)
1. the manufacturing approach of the top electrode of a phase-change random access memory.It is characterized in that, comprising:
Semiconductor substrate is provided, is formed with second insulating barrier on the said Semiconductor substrate, be filled with the GST phase-change material in said second insulating barrier;
On said second insulating barrier and GST phase-change material, deposit low temperature oxide layer, silicon nitride layer and the 3rd insulating barrier successively;
Said the 3rd insulating barrier of etching and silicon nitride layer to expose the low temperature oxide layer of bottom, form etched hole successively;
Ion injects to be handled or the interior low temperature oxide layer in Cement Composite Treated by Plasma said etched hole bottom;
Remove the low temperature oxide layer in the said etched hole bottom;
In said etched hole, form top electrode.
2. according to the manufacturing approach of the said phase-change random access memory of claim 1, it is characterized in that: also be provided with first insulating barrier between the said Semiconductor substrate and second insulating barrier, be formed with bottom electrode in said first insulating barrier.
3. according to the manufacturing approach of the said phase-change random access memory of claim 2, it is characterized in that: said GST phase-change material is covered in the bottom electrode upper surface, aims at bottom electrode.
4. according to the manufacturing approach of the said phase-change random access memory of claim 1, it is characterized in that: the deposit thickness of said low temperature oxide layer is 50 dusts～500 dusts.
5. according to the manufacturing approach of the said phase-change random access memory of claim 1, it is characterized in that: the deposit thickness of said silicon nitride layer is 50 dusts～500 dusts.
6. according to the manufacturing approach of the said phase-change random access memory of claim 1, it is characterized in that: the lithographic method of said the 3rd insulating barrier and silicon nitride layer is a dry etching.
7. according to the manufacturing approach of claim 1 or 6 said phase-change random access memories, it is characterized in that: the etching of said the 3rd insulating barrier and silicon nitride layer is vertical etching.
8. according to the manufacturing approach of the said phase-change random access memory of claim 1, it is characterized in that: the method that removes of the low temperature oxide layer of said patterning is a wet etching.
9. the manufacturing approach of said phase-change random access memory according to Claim 8, it is characterized in that: the etching agent that said wet etching adopts is a fluoric-containing acid.
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|---|---|---|---|
| CN201010534163XA CN102468428A (en) | 2010-11-05 | 2010-11-05 | Manufacture method of phase transition random memory |
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| CN201010534163XA CN102468428A (en) | 2010-11-05 | 2010-11-05 | Manufacture method of phase transition random memory |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020072217A1 (en) * | 2000-12-13 | 2002-06-13 | Macronix International Co., Ltd. | Method for improving contact reliability in semiconductor devices |
| CN101142695A (en) * | 2004-12-30 | 2008-03-12 | 意法半导体股份有限公司 | Phase change memory and manufacturing method thereof |
-
2010
- 2010-11-05 CN CN201010534163XA patent/CN102468428A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020072217A1 (en) * | 2000-12-13 | 2002-06-13 | Macronix International Co., Ltd. | Method for improving contact reliability in semiconductor devices |
| CN101142695A (en) * | 2004-12-30 | 2008-03-12 | 意法半导体股份有限公司 | Phase change memory and manufacturing method thereof |
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Application publication date: 20120523 |