CN102467581B - Ultrasound data acquisition chip - Google Patents
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Abstract
The invention discloses a kind of ultrasound data acquisition chip, each comprising modules of ultrasound data acquisition chip is integrated in a piece of FPGA, and ultrasound data acquisition chip includes transmission module on phase-locked loop module, encoder to count module, pci bus interface, ultrasound data, time-sequence control mode, multiple ultrasound detection channel module; With host computer by pci interface bus communication, can multichannel simultaneously data acquisition, data acquisition can be carried out sequencing contro, can to encoder pulse count, chip other analog sampling SOC(system on a chip) outer can be sent to, it is also possible to realize the cascade of multi-disc ultrasound data acquisition chip to carry out the extension of ultrasound detection passage by SPI interface by the parameter synchronization that host computer is issued by SPI interface. The ultrasound data acquisition chip of the present invention possesses that volume is little, versatility good, processing speed is fast, autgmentability is strong, high reliability.
Description
Technical field
The present invention relates to and the invention belongs to SOC(system on a chip), particularly relate to a kind of ultrasound data acquisition chip.
Background technology
Ultrasonic testing system generally comprises hardware system and software system two parts, is respectively completed ultrasonic emitting, echo reception, signal conversion and signal processing function and parameter setting, signal analysis and waveform display function. Ultrasound data acquisition card is the core of ultrasound detection hardware system, it is responsible for receiving the parameter that software system issues, it is used for controlling ultrasonic emitting and echo reception, echo-signal is carried out high-speed AD (modulus) conversion, signal processing, and the signal after processing is uploaded to software system processes.
Ultrasound data acquisition card conventional at present is all realized by design on board level, designs based on a piece of microprocessor (51 processors or DSP). Owing to the processing speed of microprocessor own is limited, and chip interface is few, therefore when ultrasound detection passage is more, (general ultrasound data acquisition card has four-way) needs time-sharing work, efficiency is low, the requirement simultaneously worked can not be met, and acquisition speed slow (about 50MHz), system reliability is poor. The ultrasonic acquisition card of this use microprocessor can not meet industry and produce high speed that ultrasonic testing system proposes by line, multichannel, the requirement such as reliable.
SOC(system on a chip) SoC (System-on-Chip), also referred to as system level chip, is the complete electronic system including the simulations such as memorizer, Signal sampling and processing circuit, CPU core, numeral and hybrid circuit composition be integrated on a chip. It is an integrated circuit having application-specific target, wherein comprises holonomic system and has the full content of embedded software. Along with FPGA (Field-ProgrammableGateArray, field programmable gate array) development of the increase of chip capacity and the raising of performance and hardware description language, a lot of complicated systems are transferred to chip-level design by design on board level gradually, this greatly reduces the workload of design on board level, decrease electromagnetic compatibility problem, improve the reliability of system.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of ultrasound data acquisition chip, and volume is little, versatility good, processing speed is fast, autgmentability is strong, reliability is high.
For solving above-mentioned technical problem, the ultrasound data acquisition chip of the present invention employed technical scheme comprise that, each comprising modules of ultrasound data acquisition chip is integrated in a piece of FPGA, and ultrasound data acquisition chip includes transmission module on phase-locked loop module, encoder to count module, pci bus interface, ultrasound data, time-sequence control mode, multiple ultrasound detection channel module;
Phase-locked loop module, for producing the clock signal of the every other module job demand of ultrasound data acquisition chip;
Encoder to count module, for the outside encoder pulse accessed of counting chip, count value is sent to each ultrasound detection channel module;
Pci bus interface, for same host computer communication, receive the parameter that host computer transmits, relevant parameter is respectively transmitted to time-sequence control mode, each ultrasound detection channel module, and the ultrasound detection data of each ultrasound detection channel module transmitted by transmission module on ultrasound data are sent to host computer;
The ultrasound detection data of each ultrasound detection channel module, for the data upload requests according to each ultrasound detection channel module, are sent in pci bus interface by transmission module on ultrasound data;
Time-sequence control mode, be used for receive chip exterior input triggering pulse or encoder pulse, and according to the parameter that host computer issues, export corresponding sampling pulse, data are uploaded and are pulsed into each ultrasound detection channel module;
Each ultrasound detection channel module, for receiving the ultrasonic echo data of this ultrasound detection channel module after analog digital conversion that chip exterior transmits, and in the parameter issued according to host computer when the sampling pulse of this ultrasound detection channel module arrives, obtain the A total number evidence of the ultrasonic echo data of this ultrasound detection channel module, C total number evidence, data are uploaded the A total number evidence of this ultrasound detection channel module when pulse arrives, C total number evidence, the encoder pulse count value that encoder to count module transmits, the parameter that host computer issues is packed the ultrasound detection data as this ultrasound detection channel module together, and send data upload requests to ultrasound data transmission module.
Ultrasound data acquisition chip also includes a SPI interface;
SPI interface is for being sent to the relevant parameter that pci bus interface in chip transmits outside chip, and the relevant parameter transmitted outside chip is respectively transmitted to time-sequence control mode, each ultrasound detection channel module.
Time-sequence control mode includes detection mode selection module and data upload time block;
Detection mode module, receive triggering pulse and the encoder pulse of chip exterior input, according to the mode of operation parameter that host computer issues, output services pattern information uploads time block to data, and exports the sampling pulse of each ultrasound detection channel module to each ultrasound detection channel module;
Data upload time block, send data according to host computer by the operating mode information timing that the fixed time interval parameter that issues and detection mode module transmit and upload and be pulsed into each ultrasound detection channel module.
Pci bus interface includes transmission module on parameter configuration module and DMA data;
Parameter configuration module, receives the parameter that transmits of host computer and relevant parameter is respectively transmitted to time-sequence control mode, each ultrasound detection channel module and SPI interface;
Transmission module on DMA data, the ultrasound detection data transmitted by transmission module on ultrasound data are sent in host computer.
Each ultrasound detection channel module includes a configuration parameter memory module, an AD data reception module, a data preprocessing module, a sampling control module, an A sweeps module, a C sweeps module and a data package module;
Configuration parameter memory module, for storing the parameter that host computer issues;
AD data reception module, for receiving the ultrasonic echo data after analog digital conversion that chip exterior transmits;
Data preprocessing module, for according to the squelching threshold parameter in described configuration parameter memory module, DAC compensation point parameter, the ultrasonic echo data that AD data reception module is received carries out noise suppressed and DAC and compensates pretreatment, and pretreated ultrasonic echo data exports A and sweeps module and C sweeps module;
Sampling control module, for according to the sampling original position parameter in described configuration parameter memory module, sampling time length parameter, the sampling pulse and the data that produce according to time-sequence control mode upload pulse, output sampling control signal sweeps module to A and C sweeps module, controls the sampling of ultrasonic echo data and uploads;
A sweeps module, under sampling control signal control, according to the mode of operation parameter in pretreated ultrasonic echo data and described configuration parameter memory module, compression ratio parameter, obtains A total number evidence;
C sweeps module, under sampling control signal control, according to the gate original position parameter in described configuration parameter memory module, gate widths parameter, gate height parameter, the amplitude of pretreated ultrasonic echo data is judged, obtain the amplitude of defect point and positional information as C total number evidence;
Data package module, data are uploaded the A total number of this ultrasound detection channel module when pulse arrives according to and the parameter that issues of the encoder pulse count value that transmits according to, encoder to count module of the C total number, host computer add packet header bag tail together, it is packaged into a packet, as the ultrasound detection data of this ultrasound detection channel module, and send data upload requests to ultrasound data transmission module.
Described mode of operation parameter includes free mode of operation, decoders-Synchronous pattern, encoder asynchronous mode;
Under free mode of operation, the sampling pulse of time-sequence control mode output is matched with the triggering pulse of chip exterior input, and A total number evidence is the result after pretreated ultrasonic echo data being compressed according to compression ratio parameter;
Under decoders-Synchronous pattern, the sampling pulse of time-sequence control mode output is matched with the encoder pulse of chip exterior input, and A total number evidence is after pretreated ultrasonic echo data being compressed according to compression ratio parameter and takes the result of envelope;
Under encoder asynchronous mode, the sampling pulse of time-sequence control mode output is matched with the triggering pulse of chip exterior input, and A total number evidence is after pretreated ultrasonic echo data being compressed according to compression ratio parameter and takes the result of envelope.
The ultrasound data acquisition chip of the present invention, by multiple for ultrasonic testing system ultrasound detection passages, pci bus interface, ultrasound data is uploaded, phaselocked loop, encoder to count, multiple module such as SPI interface and sequencing contro integrates, hardware description language Verilog HDL is used to program and be integrated in a piece of FPGA, with PC by pci interface bus communication, can multichannel simultaneously data acquisition, data acquisition can be carried out sequencing contro, can to encoder pulse count, chip other analog sampling SOC(system on a chip) outer can be sent to by the parameter synchronization that host computer is issued by SPI interface, it is used for arranging the gain of sampling simulation system, trigger voltage, the parameter such as front end attenuation and filtering channel, the cascade of multi-disc ultrasound data acquisition chip can also be realized to carry out the extension of ultrasound detection passage by SPI interface, motility due to FPGA design online programmable, the ultrasound data acquisition chip of the present invention and host computer, interface between other analog sampling SOC(system on a chip) all can define flexibly, design can be changed easily and meet the needs of any occasion. the ultrasound data acquisition chip of the present invention possesses that volume is little, versatility good, processing speed is fast, autgmentability is strong, high reliability.
Accompanying drawing explanation
Below in conjunction with the drawings and the specific embodiments, the present invention is described in further detail.
Fig. 1 is the ultrasound data acquisition chip one embodiment schematic diagram of the present invention;
Fig. 2 is the pci bus interface schematic diagram of ultrasound data acquisition chip one embodiment of the present invention;
Fig. 3 is the time-sequence control mode schematic diagram of ultrasound data acquisition chip one embodiment of the present invention;
Fig. 4 is the ultrasound detection channel module schematic diagram of ultrasound data acquisition chip one embodiment of the present invention;
Fig. 5 is the configuration parameter memory module schematic diagram of ultrasound data acquisition chip one embodiment of the present invention.
Detailed description of the invention
Ultrasound data acquisition chip one embodiment of the present invention is as shown in Figure 1, each comprising modules of ultrasound data acquisition chip is integrated in a piece of FPGA (Field-ProgrammableGateArray, field programmable gate array) in, ultrasound data acquisition chip includes phase-locked loop module, encoder to count module, PCI (PeripheralComponentInterconnect, peripheral component interconnection) EBI, transmission module on ultrasound data, SPI (SerialPeripheralInterface, Serial Peripheral Interface (SPI)) interface/time-sequence control mode, multiple (such as four, six) ultrasound detection channel module,
Phase-locked loop module, for producing the clock signal of the every other module job demand of ultrasound data acquisition chip, as produced the 10MHz clock that the 100MHz clock that ultrasound detection channel module needs, time-sequence control mode and SPI interface need, the 35MHz clock that pci interface needs;
Encoder to count module, for the outside encoder pulse accessed of counting chip, outside three encoder pulses accessed of energy counting chip, count value delivers to each ultrasound detection channel module as the positional information of measured workpiece, uploads together with the A total number of each ultrasound detection channel module evidence, C total number evidence;
Pci bus interface, for same host computer communication, receive the parameter that host computer transmits, relevant parameter is respectively transmitted to time-sequence control mode, each ultrasound detection channel module and SPI interface, and the ultrasound detection data of each ultrasound detection channel module transmitted by transmission module on ultrasound data are sent to host computer; Pci bus interface is as in figure 2 it is shown, include transmission module in parameter configuration module and DMA (DirectMemoryAccess, direct memory access) data; Parameter configuration module receives the parameter that transmits of host computer and relevant parameter is respectively transmitted to time-sequence control mode, each ultrasound detection channel module and SPI interface; The ultrasound detection data that on DMA data, transmission module on ultrasound data is transmitted by transmission module are sent in host computer, display and sentence wound;
SPI interface is for being sent to the relevant parameter that pci bus interface in chip transmits outside chip, and the relevant parameter transmitted outside chip is respectively transmitted to time-sequence control mode, each ultrasound detection channel module; One preferred embodiment, SPI interface is not more than 1MB/S in peak transfer rate, and each order continuously transmits 3 times, by receiving terminal using the same wherein twice data as actual command data.
On ultrasound data, transmission module is connected with transmission module on the DMA data in each ultrasound detection channel module and pci bus interface respectively, the ultrasound detection data of each ultrasound detection channel module are sent to transmission module on the DMA data in pci bus interface by the transmission module data upload requests according to each ultrasound detection channel module in data;
Time-sequence control mode, it is used for receiving triggering pulse or the encoder pulse of chip exterior input, and according to the parameter that host computer issues, export corresponding sampling pulse, data are uploaded and are pulsed into each ultrasound detection channel module, control the data sampling time sequence of each ultrasound detection channel module. as shown in Figure 3, time-sequence control mode includes detection mode selection module and data upload time block, detection mode module receives triggering pulse and the encoder pulse of chip exterior input, according to the mode of operation parameter that host computer issues, output services pattern information m uploads time block to data, and export the sampling pulse p of each ultrasound detection channel module to each ultrasound detection channel module, mode of operation parameter includes free mode of operation, decoders-Synchronous pattern, encoder asynchronous mode, under free mode of operation, the sampling pulse of time-sequence control mode output is matched with the triggering pulse of chip exterior input, under decoders-Synchronous pattern, the sampling pulse of time-sequence control mode output is matched with the encoder pulse of chip exterior input, under encoder asynchronous mode, the sampling pulse of time-sequence control mode output is matched with the triggering pulse of chip exterior input, data upload fixed time interval parameter that time block issues according to host computer and operating mode information m timing sends data and uploads pulse t to each ultrasound detection channel module, the detection data controlling each ultrasound detection channel module are uploaded.
Ultrasound detection channel module, for receiving the ultrasonic echo data of this ultrasound detection channel module after analog digital conversion that chip exterior transmits, and in the parameter issued according to host computer when the sampling pulse of this ultrasound detection channel module arrives, obtain the A total number evidence of the ultrasonic echo data of this ultrasound detection channel module, C total number evidence, data are uploaded the A total number evidence of this ultrasound detection channel module when pulse arrives, C total number evidence, the encoder pulse count value that encoder to count module transmits, the parameter that host computer issues is packed the ultrasound detection data as this ultrasound detection channel module together, and send data upload requests to ultrasound data transmission module.
Each ultrasound detection channel module function is identical, all it is used for realizing A to sweep and sweep ultrasound detection basic function with C, as shown in Figure 4, each ultrasound detection channel module all includes a configuration parameter memory module, AD (modulus) data reception module, a data preprocessing module, a sampling control module, an A sweeps module, a C sweeps module, a data package module;
Described configuration parameter memory module, for storing the parameter that host computer is issued by pci bus interface or SPI interface; As it is shown in figure 5, configuration parameter memory module includes dual port RAM and RAM read-write controller, when pci bus interface, SPI interface issue parameter, RAM read-write controller controls the parameter that dual port RAM is stored in pci bus interface, SPI interface currently issues; The parameter leaving dual port RAM when data are uploaded in is read out, and packs and upload together with A total number evidence, C total number evidence, encoder pulse count value;
AD data reception module, for receiving the ultrasonic echo data after analog digital conversion that chip exterior transmits, AD data reception module includes a FIFO memory, and the ultrasonic echo data after analog digital conversion that chip exterior transmits reads in data preprocessing module after FIFO memory buffer memory;
Data preprocessing module, for according to parameters such as the squelching threshold in described configuration parameter memory module, DAC (distance amplitude compensation) compensation points, the ultrasonic echo data that AD data reception module is received carries out noise suppressed and DAC compensates pretreatment and (is suppressed to 0 lower than the ultrasound echo signal of squelching threshold, ultrasound echo signal can be carried out at most the DAC compensation of 16), pretreated ultrasonic echo data d ' output sweeps module to A and C sweeps module;
Sampling control module, for according to parameters such as the sampling original position in described configuration parameter memory module, sampling time length, the sampling pulse p produced according to time-sequence control mode and data upload pulse t, export sampling control signal tCSweep module to A and C sweeps module, control the sampling of ultrasonic echo data d ' and upload.
A sweeps module, at sampling control signal tCUnder control, according to parameters such as the mode of operation in pretreated ultrasonic echo data d ' and described configuration parameter memory module, compression ratios, obtain the A total number according to also buffer memory; Mode of operation parameter includes free mode of operation, decoders-Synchronous pattern, encoder asynchronous mode; Under free mode of operation, the sampling pulse of time-sequence control mode output is matched with the triggering pulse of chip exterior input, and A total number evidence is the result after pretreated ultrasonic echo data d ' being compressed according to compression ratio parameter; Under decoders-Synchronous pattern, the sampling pulse of time-sequence control mode output is matched with the encoder pulse of chip exterior input, and A total number evidence is after pretreated ultrasonic echo data d ' being compressed according to compression ratio parameter and takes the result of envelope; Under encoder asynchronous mode, the sampling pulse of time-sequence control mode output is matched with the triggering pulse of chip exterior input, and A total number evidence is after pretreated ultrasonic echo data d ' being compressed according to compression ratio parameter and takes the result of envelope.
C sweeps module, at sampling control signal tCUnder control, according to parameters such as the gate original position in described configuration parameter memory module, gate widths, gate heights, the amplitude of pretreated ultrasonic echo data d ' is judged, obtain the amplitude of defect point and positional information as C total number evidence;
Data package module, data are uploaded the A total number of this ultrasound detection channel module when pulse arrives according to and the parameter that issues of the encoder pulse count value that transmits according to, encoder to count module of the C total number, host computer add packet header bag tail together, it is packaged into a packet, as the ultrasound detection data of this ultrasound detection channel module, and send data upload requests to ultrasound data transmission module.
The ultrasound data acquisition chip of the present invention, by multiple for ultrasonic testing system ultrasound detection passages, pci bus interface, ultrasound data is uploaded, phaselocked loop, encoder to count, multiple module such as SPI interface and sequencing contro integrates, hardware description language Verilog HDL is used to program and be integrated in a piece of FPGA, with PC by pci interface bus communication, can multichannel simultaneously data acquisition, data acquisition can be carried out sequencing contro, can to encoder pulse count, chip other analog sampling SOC(system on a chip) outer can be sent to by the parameter synchronization that host computer is issued by SPI interface, it is used for arranging the gain of sampling simulation system, trigger voltage, the parameter such as front end attenuation and filtering channel, the cascade of multi-disc ultrasound data acquisition chip can also be realized to carry out the extension of ultrasound detection passage by SPI interface, motility due to FPGA design online programmable, the ultrasound data acquisition chip of the present invention and host computer, interface between other analog sampling SOC(system on a chip) all can define flexibly, design can be changed easily and meet the needs of any occasion. the ultrasound data acquisition chip of the present invention possesses that volume is little, versatility good, processing speed is fast, autgmentability is strong, high reliability.
Claims (8)
1. a ultrasound data acquisition chip, it is characterized in that, each comprising modules of ultrasound data acquisition chip is integrated in a piece of FPGA, and ultrasound data acquisition chip includes transmission module on phase-locked loop module, encoder to count module, pci bus interface, ultrasound data, time-sequence control mode, multiple ultrasound detection channel module;
Phase-locked loop module, for producing the clock signal of the every other module job demand of ultrasound data acquisition chip;
Encoder to count module, for the outside encoder pulse accessed of counting chip, count value is sent to each ultrasound detection channel module;
Pci bus interface, for same host computer communication, receive the parameter that host computer transmits, relevant parameter is respectively transmitted to time-sequence control mode, each ultrasound detection channel module, and the ultrasound detection data of each ultrasound detection channel module transmitted by transmission module on ultrasound data are sent to host computer;
The ultrasound detection data of each ultrasound detection channel module, for the data upload requests according to each ultrasound detection channel module, are sent in pci bus interface by transmission module on ultrasound data;
Time-sequence control mode, be used for receive chip exterior input triggering pulse or encoder pulse, and according to the parameter that host computer issues, export corresponding sampling pulse, data are uploaded and are pulsed into each ultrasound detection channel module;
Each ultrasound detection channel module, for receiving the ultrasonic echo data of this ultrasound detection channel module after analog digital conversion that chip exterior transmits, and when the sampling pulse of this ultrasound detection channel module arrives the parameter that issues according to host computer, obtain the A total number evidence of the ultrasonic echo data of this ultrasound detection channel module, C total number evidence, data are uploaded the A total number evidence of this ultrasound detection channel module when pulse arrives, C total number evidence, the encoder pulse count value that encoder to count module transmits, the parameter that host computer issues is packed the ultrasound detection data as this ultrasound detection channel module together, and send data upload requests to ultrasound data transmission module.
2. ultrasound data acquisition chip according to claim 1, it is characterised in that ultrasound data acquisition chip includes a SPI interface;
SPI interface is for being sent to the relevant parameter that pci bus interface in chip transmits outside chip, and the relevant parameter transmitted outside chip is respectively transmitted to time-sequence control mode, each ultrasound detection channel module.
3. ultrasound data acquisition chip according to claim 1, it is characterised in that time-sequence control mode includes detection mode selection module and data upload time block;
Detection mode module, receive triggering pulse and the encoder pulse of chip exterior input, according to the mode of operation parameter that host computer issues, output services pattern information uploads time block to data, and exports the sampling pulse of each ultrasound detection channel module to each ultrasound detection channel module;
Data upload time block, send data according to host computer by the operating mode information timing that the fixed time interval parameter that issues and detection mode module transmit and upload and be pulsed into each ultrasound detection channel module.
4. ultrasound data acquisition chip according to claim 2, it is characterised in that pci bus interface includes transmission module on parameter configuration module and DMA data;
Parameter configuration module, receives the parameter that transmits of host computer and relevant parameter is respectively transmitted to time-sequence control mode, each ultrasound detection channel module and SPI interface;
Transmission module on DMA data, the ultrasound detection data transmitted by transmission module on ultrasound data are sent in host computer.
5. the ultrasound data acquisition chip according to claim 1 to 4 any one, it is characterized in that, each ultrasound detection channel module includes a configuration parameter memory module, an AD data reception module, a data preprocessing module, a sampling control module, an A sweeps module, a C sweeps module and a data package module;
Configuration parameter memory module, for storing the parameter that host computer issues;
AD data reception module, for receiving the ultrasonic echo data after analog digital conversion that chip exterior transmits;
Data preprocessing module, for according to the squelching threshold parameter in described configuration parameter memory module, DAC distance amplitude compensation point parameter, the ultrasonic echo data that AD data reception module is received carries out noise suppressed and DAC distance amplitude compensation pretreatment, and pretreated ultrasonic echo data exports A and sweeps module and C sweeps module;
Sampling control module, for according to the sampling original position parameter in described configuration parameter memory module, sampling time length parameter, the sampling pulse and the data that produce according to time-sequence control mode upload pulse, output sampling control signal sweeps module to A and C sweeps module, controls the sampling of ultrasonic echo data and uploads;
A sweeps module, under sampling control signal control, according to the mode of operation parameter in pretreated ultrasonic echo data and described configuration parameter memory module, compression ratio parameter, obtains A total number evidence;
C sweeps module, under sampling control signal control, according to the gate original position parameter in described configuration parameter memory module, gate widths parameter, gate height parameter, the amplitude of pretreated ultrasonic echo data is judged, obtain the amplitude of defect point and positional information as C total number evidence;
Data package module, data are uploaded the A total number of this ultrasound detection channel module when pulse arrives according to and the parameter that issues of the encoder pulse count value that transmits according to, encoder to count module of the C total number, host computer add packet header bag tail together, it is packaged into a packet, as the ultrasound detection data of this ultrasound detection channel module, and send data upload requests to ultrasound data transmission module.
6. ultrasound data acquisition chip according to claim 5, it is characterised in that described mode of operation parameter includes free mode of operation, decoders-Synchronous pattern, encoder asynchronous mode;
Under free mode of operation, the sampling pulse of time-sequence control mode output is matched with the triggering pulse of chip exterior input, and A total number evidence is the result after pretreated ultrasonic echo data being compressed according to compression ratio parameter;
Under decoders-Synchronous pattern, the sampling pulse of time-sequence control mode output is matched with the encoder pulse of chip exterior input, and A total number evidence is after pretreated ultrasonic echo data being compressed according to compression ratio parameter and takes the result of envelope;
Under encoder asynchronous mode, the sampling pulse of time-sequence control mode output is matched with the triggering pulse of chip exterior input, and A total number evidence is after pretreated ultrasonic echo data being compressed according to compression ratio parameter and takes the result of envelope.
7. ultrasound data acquisition chip according to claim 1, it is characterised in that ultrasound detection channel module is four.
8. ultrasound data acquisition chip according to claim 1, it is characterised in that three encoder pulses that encoder to count module count chip exterior accesses.
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| CN107064303A (en) * | 2017-04-24 | 2017-08-18 | 南通友联数码技术开发有限公司 | A kind of solid wheel shaft non-pulling wheel ultrasonic testing system, detection method and imaging method |
| CN107422042A (en) * | 2017-06-21 | 2017-12-01 | 株洲时代电子技术有限公司 | A kind of rail examination work data is shown and storage system |
| CN113381948B (en) * | 2021-05-12 | 2023-05-19 | 聚融医疗科技(杭州)有限公司 | Method and system for collecting and uploading multichannel ultrasonic data |
| CN116509454A (en) * | 2023-07-05 | 2023-08-01 | 深圳市威尔德医疗电子有限公司 | Full digital A/B ultrasonic device for eyes |
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