CN102467581A - Ultrasound data acquisition chip - Google Patents
Ultrasound data acquisition chip Download PDFInfo
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- CN102467581A CN102467581A CN2010105416725A CN201010541672A CN102467581A CN 102467581 A CN102467581 A CN 102467581A CN 2010105416725 A CN2010105416725 A CN 2010105416725A CN 201010541672 A CN201010541672 A CN 201010541672A CN 102467581 A CN102467581 A CN 102467581A
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Abstract
The invention discloses an ultrasound data acquisition chip, all composition modules of which are integrated into an FPGA (Field Programmable Gate Array). The ultrasound data acquisition chip comprises a phaselocked loop module, a coder counting module, a PCI (Peripheral Component Interconnect) bus interface, an ultrasound data uploading module, a time sequence controlling module and a plurality of ultrasound detection channel modules; the ultrasound data acquisition chip can be communicated with an upper computer through the PCI interface, can carry out data acquisition through multiple channels, and can also be used for carrying out time sequence control on the data acquisition and pulse counting on a coder as well as synchronously sending parameters issued by the upper computer to other simulation sampling systems-on-chip outside the chip through an SPI interface; and a plurality of ultrasound data acquisition chips can be cascaded through the SPI interfaces for carrying out expansion of ultrasound detection channels. The ultrasound data acquisition chip disclosed by the invention has the advantages of small volume, good generality, high processing speed, strong expansibility, high reliability and the like.
Description
Technical field
The present invention relates to the invention belongs to SOC(system on a chip), relate in particular to a kind of ultrasound data acquisition chip.
Background technology
Ultrasonic testing system generally comprises hardware system and software systems two parts, accomplishes ultrasonic emitting, echo reception, conversion of signals and signal processing function and parameter setting, signal analysis and waveform Presentation Function respectively.The ultrasound data capture card is the core of ultrasound detection hardware system; Be responsible for the parameter that the receiving software system issues; Be used for controlling ultrasonic emitting and echo and receive, echoed signal is carried out high-speed AD (modulus) conversion, signal Processing, and the signal after will handling is uploaded to software systems and handles.
Ultrasound data capture card commonly used is at present all realized through the design of plate level, is designed based on a slice microprocessor (51 processors or DSP).Because the processing speed of microprocessor own is limited; And chip interface is few; Therefore when the ultrasound detection passage more for a long time (general ultrasound data capture card all has four-way) need time-sharing work, efficient is low, can not satisfy the requirement of working simultaneously; And acquisition speed slow (about 50MHz), system reliability is poor.The ultrasonic acquisition card of this use microprocessor can not satisfy industry and produce high speed that line proposes ultrasonic testing system, hyperchannel, requirement such as reliable.
SOC(system on a chip) SoC (System-on-Chip) is also referred to as system level chip, is with comprising that the complete electronic system that simulations such as storer, signals collecting and treatment circuit, CPU nuclear, numeral and hybrid circuit constitute is integrated on the chip.It is an integrated circuit that application-specific target is arranged, and wherein comprises holonomic system and the full content of embedded software is arranged.Along with FPGA (Field-Programmable Gate Array; Field programmable gate array) development of the raising of the increase of chip capacity and performance and hardware description language; A lot of complicated systems transfer the chip-scale design to by the design of plate level gradually; The workload that this greatly reduces the design of plate level has reduced electromagnetic compatibility problem, has improved the reliability of system.
Summary of the invention
The technical matters that the present invention will solve provides a kind of ultrasound data acquisition chip, and volume is little, versatility good, processing speed is fast, extendability is strong, reliability is high.
For solving the problems of the technologies described above; The technical scheme that ultrasound data acquisition chip of the present invention adopts is; The module of respectively forming of ultrasound data acquisition chip is integrated among a slice FPGA, and the ultrasound data acquisition chip comprises transmission module on phase-locked loop module, encoder to count module, pci bus interface, the ultrasound data, time-sequence control module, a plurality of ultrasound detection channel module;
Phase-locked loop module is used to produce the clock signal of the every other module need of work of ultrasound data acquisition chip;
The encoder to count module is used for the outside encoder pulse that inserts of counting chip, and count value is sent to each ultrasound detection channel module;
Pci bus interface; Be used for host computer communication; Receive the parameter that host computer transmits, relevant parameter is sent to time-sequence control module, each ultrasound detection channel module respectively, and the ultrasound detection data of each ultrasound detection channel module that transmission module on the ultrasound data is transmitted are sent to host computer;
Transmission module on the ultrasound data is used for the data upload request according to each ultrasound detection channel module, and the ultrasound detection data of each ultrasound detection channel module are sent in the pci bus interface;
Time-sequence control module is used for the trigger pulse or the encoder pulse of the outside input of receiving chip, and according to the parameter that host computer issues, exports corresponding sampling pulse, data upload pulse to each ultrasound detection channel module;
Each ultrasound detection channel module; The ultrasonic echo data of this ultrasound detection channel module after analog to digital conversion that is used for transmitting the receiving chip outside; And the parameter that when the sampling pulse at this ultrasound detection channel module arrives, issues according to host computer; Obtain A total number certificate, the C total number certificate of the ultrasonic echo data of this ultrasound detection channel module; The A total number certificate of this ultrasound detection channel module when the data upload pulse is arrived, C total number certificate, the encoder pulse count value that the encoder to count module transmits, the parameter that host computer issues are packed as the ultrasound detection data of this ultrasound detection channel module together, and send data upload request transmission module to the ultrasound data.
The ultrasound data acquisition chip also comprises a SPI interface;
The SPI interface is used for the relevant parameter that pci bus interface in the chip transmits is sent to outside the chip, and the relevant parameter that chip transmits outward is sent to time-sequence control module, each ultrasound detection channel module respectively.
Time-sequence control module comprises detecting pattern selection module and data upload time block;
The detecting pattern module; The trigger pulse and the encoder pulse of the outside input of receiving chip; According to the mode of operation parameter that host computer issues, the output services pattern information is given the data upload time block, and the sampling pulse of exporting each ultrasound detection channel module is to each ultrasound detection channel module;
The data upload time block regularly sends the data upload pulse to each ultrasound detection channel module according to the mode of operation information that host computer transmits through the fixed time interval parameter that issues and detecting pattern module.
Pci bus interface comprises parameter configuration module and DMA data upload module;
Parameter configuration module receives parameter that host computer transmits and relevant parameter is sent to time-sequence control module, each ultrasound detection channel module and SPI interface respectively;
DMA data upload module, the ultrasound detection data that transmission module on the ultrasound data is transmitted are sent in the host computer.
Each ultrasound detection channel module comprises that a configuration parameter memory module, an AD data reception module, a data preprocessing module, a controlling of sampling module, an A sweep module, a C sweeps a module and a data encapsulation module;
The configuration parameter memory module is used to store the parameter that host computer issues;
The AD data reception module is used for the ultrasonic echo data after analog to digital conversion that the receiving chip outside is transmitted;
Data preprocessing module; Be used for squelch threshold parameter, DAC compensation point parameter according to said configuration parameter memory module; The ultrasonic echo data that the AD data reception module is received carries out squelch and DAC compensation pre-service, and pretreated ultrasonic echo data outputs to that A sweeps module and C sweeps module;
The controlling of sampling module; Be used for sampling reference position parameter, sampling time length parameter according to said configuration parameter memory module; Sampling pulse and data upload pulse according to the time-sequence control module generation; The output sampling control signal is swept module and C sweeps module to A, controls the sampling of ultrasonic echo data and uploads;
A sweeps module, and under sampling control signal control, mode of operation parameter, ratio of compression parameter according in pretreated ultrasonic echo data and the said configuration parameter memory module obtain A total number certificate;
C sweeps module; Under sampling control signal control; Gate reference position parameter, gate width parameter, gate height parameter according in the said configuration parameter memory module judge the amplitude of pretreated ultrasonic echo data, and the amplitude and the positional information that obtain defect point are as C total number certificate;
The data encapsulation module; The A total number certificate of this ultrasound detection channel module when the data upload pulse is arrived and C total number certificate, the encoder pulse count value that the encoder to count module transmits, the parameter that host computer issues are added packet header bag tail together; Be packaged into a packet; As the ultrasound detection data of this ultrasound detection channel module, and send data upload request transmission module to the ultrasound data.
Said mode of operation parameter comprises free mode of operation, scrambler synchronous mode, scrambler asynchronous mode;
Under the free mode of operation, the sampling pulse of time-sequence control module output is matched with the trigger pulse of chip exterior input, and A total number certificate is the result after according to the ratio of compression parameter pretreated ultrasonic echo data being compressed;
Under the scrambler synchronous mode, the sampling pulse of time-sequence control module output is matched with the encoder pulse of chip exterior input, and the A total number is according to the result for according to the ratio of compression parameter pretreated ultrasonic echo data being compressed the back and gets envelope;
Under the scrambler asynchronous mode, the sampling pulse of time-sequence control module output is matched with the trigger pulse of chip exterior input, and the A total number is according to the result for according to the ratio of compression parameter pretreated ultrasonic echo data being compressed the back and gets envelope.
Ultrasound data acquisition chip of the present invention; With a plurality of ultrasound detection passages of ultrasonic testing system, pci bus interface, ultrasound data upload, a plurality of modules such as phaselocked loop, encoder to count, SPI interface and sequential control integrate; Use hardware description language Verilog HDL programming also is integrated among a slice FPGA; Pass through the pci interface bus communication with PC; Can hyperchannel data acquisition simultaneously, can carry out sequential control to the data collection, can be to encoder pulse count; Can send to outer other analog sampling SOC(system on a chip)s of chip through the parameter synchronization that the SPI interface issues host computer; Be used for being provided with the parameters such as gain, trigger voltage, front end decay and filtering channel of sampling simulation system, the cascade that can also realize multi-disc ultrasound data acquisition chip through the SPI interface is to carry out the expansion of ultrasound detection passage, because the programmable dirigibility of FPGA online design; Interface between ultrasound data acquisition chip of the present invention and host computer, other analog sampling SOC(system on a chip)s all can define flexibly, can change the needs that any occasion is satisfied in design easily.Ultrasound data acquisition chip of the present invention possesses that volume is little, versatility good, processing speed is fast, extendability is strong, the reliability advantages of higher.
Description of drawings
Below in conjunction with accompanying drawing and embodiment the present invention is done further explain.
Fig. 1 is ultrasound data acquisition chip one an embodiment synoptic diagram of the present invention;
Fig. 2 is the pci bus interface synoptic diagram of ultrasound data acquisition chip one embodiment of the present invention;
Fig. 3 is the time-sequence control module synoptic diagram of ultrasound data acquisition chip one embodiment of the present invention;
Fig. 4 is the ultrasound detection channel module synoptic diagram of ultrasound data acquisition chip one embodiment of the present invention;
Fig. 5 is the configuration parameter memory module synoptic diagram of ultrasound data acquisition chip one embodiment of the present invention.
Embodiment
Ultrasound data acquisition chip one embodiment of the present invention is as shown in Figure 1; The module of respectively forming of ultrasound data acquisition chip is integrated in a slice FPGA (Field-Programmable Gate Array; Field programmable gate array) in; The ultrasound data acquisition chip comprises phase-locked loop module, encoder to count module, PCI (Peripheral Component Interconnect; Peripheral component interconnection) transmission module, SPI (Serial Peripheral Interface, Serial Peripheral Interface (SPI)) interface/time-sequence control module, a plurality of (as four, six) ultrasound detection channel module on EBI, the ultrasound data;
Phase-locked loop module; Be used to produce the clock signal of the every other module need of work of ultrasound data acquisition chip; As produce the 100MHz clock that the ultrasound detection channel module needs, the 10MHz clock that time-sequence control module and SPI interface need, the 35MHz clock that pci interface needs;
The encoder to count module; Be used for the outside encoder pulse that inserts of counting chip; Outside three encoder pulses that insert of ability counting chip; Count value is delivered to each ultrasound detection channel module as the positional information of measured workpiece, uploads with A total number certificate, the C total number certificate of each ultrasound detection channel module;
Pci bus interface; Be used for host computer communication; Receive the parameter that host computer transmits; Relevant parameter is sent to time-sequence control module, each ultrasound detection channel module and SPI interface respectively, and the ultrasound detection data of each ultrasound detection channel module that transmission module on the ultrasound data is transmitted are sent to host computer; Pci bus interface is as shown in Figure 2, comprises parameter configuration module and DMA (Direct Memory Access, direct memory access) data upload module; Parameter configuration module receives parameter that host computer transmits and relevant parameter is sent to time-sequence control module, each ultrasound detection channel module and SPI interface respectively; DMA data upload module is sent to the ultrasound detection data that transmission module on the ultrasound data transmits in the host computer, shows and declares wound;
The SPI interface is used for the relevant parameter that pci bus interface in the chip transmits is sent to outside the chip, and the relevant parameter that chip transmits outward is sent to time-sequence control module, each ultrasound detection channel module respectively; One preferred embodiment, the SPI interface is not more than 1MB/S in peak transfer rate, each order is sent 3 times continuously, by receiving end wherein twice the same data as the actual command data.
On the ultrasound data transmission module respectively with each ultrasound detection channel module and pci bus interface in DMA data upload module link to each other; The data upload module is according to the data upload request of each ultrasound detection channel module, and the ultrasound detection data of each ultrasound detection channel module are sent to the DMA data upload module in the pci bus interface;
Time-sequence control module; Be used for the trigger pulse or the encoder pulse of the outside input of receiving chip; And, export corresponding sampling pulse, data upload pulse to each ultrasound detection channel module according to the parameter that host computer issues, control the data acquisition sequential of each ultrasound detection channel module.As shown in Figure 3; Time-sequence control module comprises detecting pattern selection module and data upload time block; The trigger pulse and the encoder pulse of the outside input of detecting pattern module receiving chip, according to the mode of operation parameter that host computer issues, output services pattern information m gives the data upload time block; And the sampling pulse p that exports each ultrasound detection channel module arrives each ultrasound detection channel module; The mode of operation parameter comprises free mode of operation, scrambler synchronous mode, scrambler asynchronous mode, and under the free mode of operation, the sampling pulse of time-sequence control module output is matched with the trigger pulse of chip exterior input; Under the scrambler synchronous mode; The sampling pulse of time-sequence control module output is matched with the encoder pulse of chip exterior input, and under the scrambler asynchronous mode, the sampling pulse of time-sequence control module output is matched with the trigger pulse of chip exterior input; The data upload time block regularly sends data upload pulse t to each ultrasound detection channel module according to fixed time interval parameter and the mode of operation information m that host computer issues, and controls the detection data upload of each ultrasound detection channel module.
The ultrasound detection channel module; The ultrasonic echo data of this ultrasound detection channel module after analog to digital conversion that is used for transmitting the receiving chip outside; And the parameter that when the sampling pulse at this ultrasound detection channel module arrives, issues according to host computer; Obtain A total number certificate, the C total number certificate of the ultrasonic echo data of this ultrasound detection channel module; The A total number certificate of this ultrasound detection channel module when the data upload pulse is arrived, C total number certificate, the encoder pulse count value that the encoder to count module transmits, the parameter that host computer issues are packed as the ultrasound detection data of this ultrasound detection channel module together, and send data upload request transmission module to the ultrasound data.
Each ultrasound detection channel module function is identical; Be used to all realize that A sweeps with C sweeps the ultrasound detection basic function; As shown in Figure 4, each ultrasound detection channel module includes that a configuration parameter memory module, A D (modulus) data reception module, a data preprocessing module, a controlling of sampling module, an A are swept module, a C sweeps module, a data encapsulation module;
Said configuration parameter memory module is used to store the parameter that host computer issues through pci bus interface or SPI interface; As shown in Figure 5, the configuration parameter memory module comprises dual port RAM and RAM read-write controller, and when pci bus interface, when the SPI interface issues parameter, RAM read-write controller control dual port RAM deposits pci bus interface, the current parameter that issues of SPI interface in; The parameter that when data upload, leaves dual port RAM in is read, and packs and uploads with A total number certificate, C total number certificate, encoder pulse count value;
The AD data reception module; Be used for the ultrasonic echo data after analog to digital conversion that the receiving chip outside is transmitted; The AD data reception module comprises a FIFO storer, and what chip exterior transmitted reads in data preprocessing module through the ultrasonic echo data after the analog to digital conversion after the FIFO memory buffer;
Data preprocessing module; Be used for parameter such as squelch threshold value, DAC (distance amplitude compensation) compensation point according to said configuration parameter memory module; The ultrasonic echo data that the AD data reception module is received carries out squelch and DAC compensation pre-service, and (it is 0 that the ultrasound echo signal that is lower than the squelch threshold value is suppressed; Can carry out 16 DAC compensation to ultrasound echo signal at most), pretreated ultrasonic echo data d ' outputs to that A sweeps module and C sweeps module;
The controlling of sampling module is used for the parameters such as sampling reference position, sampling time length according to said configuration parameter memory module, and sampling pulse p and data upload pulse t according to time-sequence control module produces export sampling control signal t
CSweep module and C sweeps module to A, the sampling of control ultrasonic echo data d ' and uploading.
A sweeps module, at sampling control signal t
CControl according to parameters such as the mode of operation in pretreated ultrasonic echo data d ' and the said configuration parameter memory module, ratio of compression, obtains A total number certificate and buffer memory down; The mode of operation parameter comprises free mode of operation, scrambler synchronous mode, scrambler asynchronous mode; Under the free mode of operation, the sampling pulse of time-sequence control module output is matched with the trigger pulse of chip exterior input, and A total number certificate is the result after according to the ratio of compression parameter pretreated ultrasonic echo data d ' being compressed; Under the scrambler synchronous mode, the sampling pulse of time-sequence control module output is matched with the encoder pulse of chip exterior input, and the A total number is according to the result for according to the ratio of compression parameter pretreated ultrasonic echo data d ' being compressed the back and gets envelope; Under the scrambler asynchronous mode, the sampling pulse of time-sequence control module output is matched with the trigger pulse of chip exterior input, and the A total number is according to the result for according to the ratio of compression parameter pretreated ultrasonic echo data d ' being compressed the back and gets envelope.
C sweeps module, at sampling control signal t
CControl judges the amplitude of pretreated ultrasonic echo data d ' according to parameters such as the gate reference position in the said configuration parameter memory module, gate width, gate height down, and the amplitude and the positional information that obtain defect point are as C total number certificate;
The data encapsulation module; The A total number certificate of this ultrasound detection channel module when the data upload pulse is arrived and C total number certificate, the encoder pulse count value that the encoder to count module transmits, the parameter that host computer issues are added packet header bag tail together; Be packaged into a packet; As the ultrasound detection data of this ultrasound detection channel module, and send data upload request transmission module to the ultrasound data.
Ultrasound data acquisition chip of the present invention; With a plurality of ultrasound detection passages of ultrasonic testing system, pci bus interface, ultrasound data upload, a plurality of modules such as phaselocked loop, encoder to count, SPI interface and sequential control integrate; Use hardware description language Verilog HDL programming also is integrated among a slice FPGA; Pass through the pci interface bus communication with PC; Can hyperchannel data acquisition simultaneously, can carry out sequential control to the data collection, can be to encoder pulse count; Can send to outer other analog sampling SOC(system on a chip)s of chip through the parameter synchronization that the SPI interface issues host computer; Be used for being provided with the parameters such as gain, trigger voltage, front end decay and filtering channel of sampling simulation system, the cascade that can also realize multi-disc ultrasound data acquisition chip through the SPI interface is to carry out the expansion of ultrasound detection passage, because the programmable dirigibility of FPGA online design; Interface between ultrasound data acquisition chip of the present invention and host computer, other analog sampling SOC(system on a chip)s all can define flexibly, can change the needs that any occasion is satisfied in design easily.Ultrasound data acquisition chip of the present invention possesses that volume is little, versatility good, processing speed is fast, extendability is strong, the reliability advantages of higher.
Claims (8)
1. ultrasound data acquisition chip; It is characterized in that; The module of respectively forming of ultrasound data acquisition chip is integrated among a slice FPGA, and the ultrasound data acquisition chip comprises transmission module on phase-locked loop module, encoder to count module, pci bus interface, the ultrasound data, time-sequence control module, a plurality of ultrasound detection channel module;
Phase-locked loop module is used to produce the clock signal of the every other module need of work of ultrasound data acquisition chip;
The encoder to count module is used for the outside encoder pulse that inserts of counting chip, and count value is sent to each ultrasound detection channel module;
Pci bus interface; Be used for host computer communication; Receive the parameter that host computer transmits, relevant parameter is sent to time-sequence control module, each ultrasound detection channel module respectively, and the ultrasound detection data of each ultrasound detection channel module that transmission module on the ultrasound data is transmitted are sent to host computer;
Transmission module on the ultrasound data is used for the data upload request according to each ultrasound detection channel module, and the ultrasound detection data of each ultrasound detection channel module are sent in the pci bus interface;
Time-sequence control module is used for the trigger pulse or the encoder pulse of the outside input of receiving chip, and according to the parameter that host computer issues, exports corresponding sampling pulse, data upload pulse to each ultrasound detection channel module;
Each ultrasound detection channel module; The ultrasonic echo data of this ultrasound detection channel module after analog to digital conversion that is used for transmitting the receiving chip outside; And the parameter that when the sampling pulse at this ultrasound detection channel module arrives, issues according to host computer; Obtain A total number certificate, the C total number certificate of the ultrasonic echo data of this ultrasound detection channel module; The A total number certificate of this ultrasound detection channel module when the data upload pulse is arrived, C total number certificate, the encoder pulse count value that the encoder to count module transmits, the parameter that host computer issues are packed as the ultrasound detection data of this ultrasound detection channel module together, and send data upload request transmission module to the ultrasound data.
2. ultrasound data acquisition chip according to claim 1 is characterized in that, the ultrasound data acquisition chip comprises a SPI interface;
The SPI interface is used for the relevant parameter that pci bus interface in the chip transmits is sent to outside the chip, and the relevant parameter that chip transmits outward is sent to time-sequence control module, each ultrasound detection channel module respectively.
3. ultrasound data acquisition chip according to claim 1 is characterized in that, time-sequence control module comprises detecting pattern selection module and data upload time block;
The detecting pattern module; The trigger pulse and the encoder pulse of the outside input of receiving chip; According to the mode of operation parameter that host computer issues, the output services pattern information is given the data upload time block, and the sampling pulse of exporting each ultrasound detection channel module is to each ultrasound detection channel module;
The data upload time block regularly sends the data upload pulse to each ultrasound detection channel module according to the mode of operation information that host computer transmits through the fixed time interval parameter that issues and detecting pattern module.
4. ultrasound data acquisition chip according to claim 2 is characterized in that, pci bus interface comprises parameter configuration module and DMA data upload module;
Parameter configuration module receives parameter that host computer transmits and relevant parameter is sent to time-sequence control module, each ultrasound detection channel module and SPI interface respectively;
DMA data upload module, the ultrasound detection data that transmission module on the ultrasound data is transmitted are sent in the host computer.
5. according to any described ultrasound data acquisition chip of claim 1 to 4; It is characterized in that each ultrasound detection channel module comprises that a configuration parameter memory module, an AD data reception module, a data preprocessing module, a controlling of sampling module, an A sweep module, a C sweeps a module and a data encapsulation module;
The configuration parameter memory module is used to store the parameter that host computer issues;
The AD data reception module is used for the ultrasonic echo data after analog to digital conversion that the receiving chip outside is transmitted;
Data preprocessing module; Be used for squelch threshold parameter, DAC compensation point parameter according to said configuration parameter memory module; The ultrasonic echo data that the AD data reception module is received carries out squelch and DAC compensation pre-service, and pretreated ultrasonic echo data outputs to that A sweeps module and C sweeps module;
The controlling of sampling module; Be used for sampling reference position parameter, sampling time length parameter according to said configuration parameter memory module; Sampling pulse and data upload pulse according to the time-sequence control module generation; The output sampling control signal is swept module and C sweeps module to A, controls the sampling of ultrasonic echo data and uploads;
A sweeps module, and under sampling control signal control, mode of operation parameter, ratio of compression parameter according in pretreated ultrasonic echo data and the said configuration parameter memory module obtain A total number certificate;
C sweeps module; Under sampling control signal control; Gate reference position parameter, gate width parameter, gate height parameter according in the said configuration parameter memory module judge the amplitude of pretreated ultrasonic echo data, and the amplitude and the positional information that obtain defect point are as C total number certificate;
The data encapsulation module; The A total number certificate of this ultrasound detection channel module when the data upload pulse is arrived and C total number certificate, the encoder pulse count value that the encoder to count module transmits, the parameter that host computer issues are added packet header bag tail together; Be packaged into a packet; As the ultrasound detection data of this ultrasound detection channel module, and send data upload request transmission module to the ultrasound data.
6. ultrasound data acquisition chip according to claim 5 is characterized in that, said mode of operation parameter comprises free mode of operation, scrambler synchronous mode, scrambler asynchronous mode;
Under the free mode of operation, the sampling pulse of time-sequence control module output is matched with the trigger pulse of chip exterior input, and A total number certificate is the result after according to the ratio of compression parameter pretreated ultrasonic echo data being compressed;
Under the scrambler synchronous mode, the sampling pulse of time-sequence control module output is matched with the encoder pulse of chip exterior input, and the A total number is according to the result for according to the ratio of compression parameter pretreated ultrasonic echo data being compressed the back and gets envelope;
Under the scrambler asynchronous mode, the sampling pulse of time-sequence control module output is matched with the trigger pulse of chip exterior input, and the A total number is according to the result for according to the ratio of compression parameter pretreated ultrasonic echo data being compressed the back and gets envelope.
7. ultrasound data acquisition chip according to claim 1 is characterized in that, the ultrasound detection channel module is four.
8. ultrasound data acquisition chip according to claim 1 is characterized in that, three encoder pulses that encoder to count module count chip exterior inserts.
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| CN107422042A (en) * | 2017-06-21 | 2017-12-01 | 株洲时代电子技术有限公司 | A kind of rail examination work data is shown and storage system |
| CN113381948A (en) * | 2021-05-12 | 2021-09-10 | 聚融医疗科技(杭州)有限公司 | Sub-channel ultrasonic data acquisition and uploading method and system |
| CN116509454A (en) * | 2023-07-05 | 2023-08-01 | 深圳市威尔德医疗电子有限公司 | Full digital A/B ultrasonic device for eyes |
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