CN102467429A - Smart card chip simulator - Google Patents
Smart card chip simulator Download PDFInfo
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- CN102467429A CN102467429A CN2010105392824A CN201010539282A CN102467429A CN 102467429 A CN102467429 A CN 102467429A CN 2010105392824 A CN2010105392824 A CN 2010105392824A CN 201010539282 A CN201010539282 A CN 201010539282A CN 102467429 A CN102467429 A CN 102467429A
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- smart card
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Abstract
The invention discloses a smart card chip simulator, which comprises a clock source module and a simulated chip, wherein the clock source module has a plurality of clock output pins for generating a multi-path clock signal; and the simulated chip is realized by a field programmable gate array (FPGA) chip of which input/output (I/O) interfaces are connected with the clock output pins of the clock source module, processes the clock signal and transmits the processed clock signal to other modules for use. In the smart card chip simulator, the simulated chip can be realized by the FPGA chip with relatively fewer clock resources, and functions, executed by the simulated chip in the simulator, of a user program are ensured to be consistent with those executed by a product chip; and the invention is favorable for further decreasing the manufacture cost of the smart card chip simulator and shortening a production cycle.
Description
Technical field
The present invention relates to field of intelligent cards, particularly relate to a kind of intelligent card chip emulator that uses the low side fpga chip to realize emulation chip.
Background technology
The user program that has the user to develop in the smart card, in the writing and debug of user program, employed instrument generally is the intelligent card chip emulator.Use in the emulator to comprise product chips each item function simulating chip, be used for the work behavior of analog equipment card.The usage quantity of considering emulator is less, accordingly the emulation chip use amount of certain model chip also seldom, and flow expense (tens to 1,000,000) and risk are all very high.In order to reduce cost; The emulation chip that a lot of manufacturers all do not design, flow is independent, then the emulation chip that uses FPGA (field programmable gate array) chip and show to substitute flow to the net of concrete chip model design to certain type product chip.The emulation chip that fpga chip screening table is realized (being called for short FPGA form emulation chip); Because fpga chip can use repeatedly, can realize different designs through the net table of revising, upgrade in the fpga chip, the chip functions of simulation different model; Than making dedicated emulated chip; Cost savings is a lot, and the versatility of emulation chip is also stronger, the design risk also reduces greatly, so the ratio that FPGA form emulation chip occupies in the emulator series products is increasingly high.
The characteristics of intelligent card chip are the internal clocking complex structures; Need the multipath clock of supplying with algorithms of different, distinct interface module; And the pin that final smart card product chip is drawn seldom, and the clock that needs in inner each the road algorithms of different of product chips chips, interface module all needs chip to produce voluntarily in inside.In the existing emulator; When using fpga chip to realize emulation chip; In fpga chip, produce multipath clock equally,, just have to select to have the high-end fpga chip of a lot of clock resources because this need take a large amount of fpga chip clock resources; These high-end fpga chip expensive (several thousand to several ten thousand yuan of a slices), procurement cycle are long, have objectively increased the cost and the production time of emulator.And low side fpga chip (thousand yuan of a slices of hundreds of to) can't be realized multipath clock required in the emulation chip because the clock resource that it comprised is less, can't be used to realize the emulation chip of intelligent card chip.
Summary of the invention
The technical matters that the present invention will solve provides a kind of intelligent card chip emulator, can use the less fpga chip of clock resource to realize emulation chip, and guarantees that the function of emulation chip execution user program in the emulator is consistent with product chips.
For solving the problems of the technologies described above, intelligent card chip emulator of the present invention comprises:
The clock source module has a plurality of clock output pins, is used to produce the multipath clock signal;
Emulation chip adopts fpga chip to realize that the I/O interface of this fpga chip is connected with the clock output pin of said clock source module; Sending other module after said clock signal handled to uses.
Adopt intelligent card chip emulator of the present invention, can use the less low side fpga chip of clock resource to realize emulation chip, and guarantee that the function of emulation chip execution user program in the emulator is consistent with product chips; Help further to reduce cost of manufacture, the shortening production cycle of intelligent card chip emulator.
Description of drawings
Below in conjunction with accompanying drawing and embodiment the present invention is done further detailed explanation:
Accompanying drawing is intelligent card chip emulator one an example structure synoptic diagram of the present invention;
Embodiment
Need be appreciated that earlier that even the less fpga chip of clock resource, the I/O interface of drawing also has tens to hundreds of, these I/O interfaces can be used as the input of external timing signal.Emulator uses to user's debug user programs; Therefore Simulator Design being required is that the function that shows during with execution on product chips of the function that shows when in emulator, carrying out on the emulation chip of user program is consistent as far as possible, and the user also is indifferent to realization principle and the framework etc. of emulator.
As shown in the figure, in one embodiment, said intelligent card chip emulator comprises: emulation chip 2 and clock source module 3.
Said emulation chip 2 uses the less low side fpga chip of clock resource to realize that described clock source module 3 can produce the multipath clock signal.Clock source module 3 has a plurality of clock output pins, clock output pin 1 ... Clock output pin n is with the I/O interface (IO1 of the fpga chip of realizing emulation chip 2 ... IOn) connect, to emulation chip 2 output multipath clock signals.Described clock source module 3 can use a plurality of active crystal oscillators to realize; Also can realize with a plurality of special clock generation chip that the clock signal frequency is set; No matter be active crystal oscillator or special clock generation chip, price all very cheap (several units to tens yuan).
Like this; Need not to re-use limited internal clocking resource in the emulation chip 2 that uses fpga chip to realize and produce the clock signal that satisfies each algorithm, interface module needs, only need do those clock signals that clock source module 3 is brought that some simple process (for example frequency division etc.) are given each algorithm respectively, interface module gets final product.
Even need to produce the clock signal on a lot of roads in the smart card product chip of a certain model, adopt the emulation chip 2 in the intelligent card chip emulator of the present invention also can use the less low side FPGA of clock resource to realize.Simultaneously, emulation chip 2 has no minimizing than product chips in the said emulator 1 on function, and is still consistent with product chips, and the function that is shown when carrying out user program also must be consistent, can satisfy the demand of user's debugged program.
More than through embodiment the present invention has been carried out detailed explanation, but these are not to be construed as limiting the invention.Under the situation that does not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be regarded as protection scope of the present invention.
Claims (2)
1. an intelligent card chip emulator is characterized in that, comprising:
The clock source module has a plurality of clock output pins, is used to produce the multipath clock signal;
Emulation chip adopts fpga chip to realize that the I/O interface of this fpga chip is connected with the clock output pin of said clock source module; Sending other module after said clock signal handled to uses.
2. intelligent card chip emulator as claimed in claim 1 is characterized in that: said clock source module adopts a plurality of active crystal oscillators to realize, also can realize with a plurality of special clock generation chip that the clock signal frequency is set.
Priority Applications (1)
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CN2010105392824A CN102467429A (en) | 2010-11-11 | 2010-11-11 | Smart card chip simulator |
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CN2010105392824A CN102467429A (en) | 2010-11-11 | 2010-11-11 | Smart card chip simulator |
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CN102467429A true CN102467429A (en) | 2012-05-23 |
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CN2010105392824A Pending CN102467429A (en) | 2010-11-11 | 2010-11-11 | Smart card chip simulator |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112506776A (en) * | 2020-12-08 | 2021-03-16 | 上海市信息网络有限公司 | Processor chip debugging system |
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CN1863105A (en) * | 2006-04-29 | 2006-11-15 | 中山大学 | Method of multichannel wireless communication sumulating and apparatus thereof |
US7478030B1 (en) * | 2003-06-19 | 2009-01-13 | Xilinx, Inc. | Clock stabilization detection for hardware simulation |
CN201374060Y (en) * | 2008-12-16 | 2009-12-30 | 康佳集团股份有限公司 | IIC bus expanded system structure |
US20110184717A1 (en) * | 2010-01-22 | 2011-07-28 | Robert Erickson | Method and System for Packet Switch Based Logic Replication |
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2010
- 2010-11-11 CN CN2010105392824A patent/CN102467429A/en active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7478030B1 (en) * | 2003-06-19 | 2009-01-13 | Xilinx, Inc. | Clock stabilization detection for hardware simulation |
CN1863105A (en) * | 2006-04-29 | 2006-11-15 | 中山大学 | Method of multichannel wireless communication sumulating and apparatus thereof |
CN201374060Y (en) * | 2008-12-16 | 2009-12-30 | 康佳集团股份有限公司 | IIC bus expanded system structure |
US20110184717A1 (en) * | 2010-01-22 | 2011-07-28 | Robert Erickson | Method and System for Packet Switch Based Logic Replication |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112506776A (en) * | 2020-12-08 | 2021-03-16 | 上海市信息网络有限公司 | Processor chip debugging system |
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Application publication date: 20120523 |