CN102456574B - Grooved semiconductor device of self-aligned metal silicide and manufacturing method thereof - Google Patents

Grooved semiconductor device of self-aligned metal silicide and manufacturing method thereof Download PDF

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Publication number
CN102456574B
CN102456574B CN201010523007.3A CN201010523007A CN102456574B CN 102456574 B CN102456574 B CN 102456574B CN 201010523007 A CN201010523007 A CN 201010523007A CN 102456574 B CN102456574 B CN 102456574B
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semiconductor device
contact hole
self
mask
metal
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CN102456574A (en
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梁安杰
苏冠创
张崇兴
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HONGKONG SHANGMOSIFEITE SEMICONDUCTOR CO Ltd
M Mos Semiconductor HK Ltd
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HONGKONG SHANGMOSIFEITE SEMICONDUCTOR CO Ltd
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Priority to PCT/CN2011/078878 priority patent/WO2012055288A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The invention provides a grooved semiconductor device of self-aligned metal silicide and a manufacturing method thereof. The method comprises the following steps of: forming a base region by using a source region mask; etching a groove by using a groove mask and depositing polycrystalline silicon; injecting phosphorus elements to form a source region; forming silicides on the surfaces of the polycrystalline silicon and the source region; and depositing an aluminum copper alloy to form a source metal cushion layer, a grid cushion layer and a metal connecting line. By using the manufacturing method provided by the invention, the manufacturing procedure and pollution of the grooved semiconductor device of the self-aligned metal silicide are reduced and the consistency of threshold voltage and other electric parameters of the semiconductor device is ensured because less mask plates are adopted. Because the manufacturing method provided by the invention has the advantages of simplicity, easiness and easiness for realizing the manufacturing process, the quality and reliability of the device are largely improved.

Description

A kind of grooved semiconductor device and manufacture method of self-aligned metal silicate
Technical field
The present invention relates to a kind of semiconductor device, relate in particular to a kind of grooved semiconductor device and manufacture method.
Background technology
In existing grooved semiconductor device manufacturing processes, conventionally adopt and form that self-aligned metal silicate is improved in source region, drain region and the film resistor of grid region silicon and the contact resistance of silicon and metal Zhi Inter, to reach conducting resistance and the resistance that device is lower, improve the efficiency of device.
American documentation literature (US20030168695A1) discloses a kind of manufacture method of mos field effect transistor groove silicide grids, as shown in figure 18, in the method, only there is one deck silicide (for example titanium silicide) at the surface deposition of the conductive polycrystalline silicon grid of semiconductor field effect transistor groove, then at the thick oxide layer of its surface deposition part.
American documentation literature (US20070023828A1) discloses a kind of semiconductor device and manufacture method thereof, as shown in figure 19, first the grid in groove in the vertical direction in two, middle using oxide as isolation, then part deposits one deck silicide to this semiconductor device thereon.
Adopting publication number is the semiconductor field effect transistor that US20030168695A1 american documentation literature is manufactured, the local thick oxide layer of its suicide surfaces can make air spots smooth, cause the inhomogeneous of source metal thickness, affect the conducting resistance consistency of device, be the semiconductor field effect transistor that US20070023828A1 american documentation literature is manufactured and adopt publication number, to high, the operation more complicated that requires of trench etch, make polysilicon width be difficult to control, affect the consistency of device.
Summary of the invention
The deficiency existing in order to solve prior art, the invention provides a kind of grooved semiconductor device and manufacture method of self-aligned metal silicate, with less processing step and mask, pollution and the conforming control of having avoided relevant operation to cause, reach the consistency of the electrical quantity such as threshold voltage and conducting resistance.
To achieve these goals, according to the manufacture method of the grooved semiconductor device of self-aligned metal silicate of the present invention, comprise the following steps:
1) utilize active region mask to form base;
2) utilize trench mask to etch groove, and deposit spathic silicon;
3) inject P elements, form source region;
4) form silicide at described polysilicon and surface, source region;
5) deposition of aluminum copper alloy, forms source metal bed course, gate metal bed course and metal connecting line.
Wherein, described step 1) is further comprising the steps:
A) on the epitaxial loayer of substrate, deposit thickness is the first oxide layer of 8000 left and right;
B) etching the first oxide layer forms active region mask, then in the epitaxial loayer part B Implanted element ， And propelling exposing is diffused into epitaxial loayer, forms base.
Wherein, described step 2) further comprising the steps:
A) generate the worn-out oxide layer of screen, deposition lithography coating, and it is carried out to etching formation trench mask;
B) utilize trench mask, expose epitaxial loayer partially-etched go out groove;
C) remove lithography coating, and the epitaxial loayer part, trenched side-wall and the lower surface that expose are sacrificed to oxidation, and then form the second oxide layer.
Wherein, described step 3) is further comprising the steps:
A) polysilicon of deposition to adulterate in groove, and polysilicon is eat-back;
B) inject P elements, and adopt annealing operation that its propelling is diffused into and in base, forms source region.
Wherein, further comprising the steps of between described step 3) and step 4): deposition lithography coating, and it is carried out to etching form the second base mask, the step of B Implanted element.
Wherein, further comprising the steps of between described step 3) and step 4):
A) deposition etching photolithograhic coating, forms the first contact hole mask;
B) etch contact hole groove by the first contact hole mask; To B Implanted element in contact hole groove, and its propelling is diffused into base.
Wherein, described step 4) also comprises:
A) remove after the lip-deep oxide in source region;
B) deposition transition metal, the operation of annealing is reacted metal and monocrystalline silicon and is formed silicide;
C) the unreacted transition metal of Xuan Ze Erosion Ke Duo I.
Wherein, described step 5) is further comprising the steps:
A) form contact hole groove by contact hole mask;
B) contact hole groove is filled and formed trench plug;
C) deposition of aluminum copper alloy, and anneal, then carry out metal etch by metal mask, form source metal bed course, gate metal bed course and metal connecting line.
Wherein, described step 5) is further comprising the steps:
A) in groove, deposit inter-level dielectric and eat-back;
B) deposition etching photolithograhic coating, forms the second contact hole mask;
C) utilize the second contact hole mask, the inter-level dielectric in etching contact hole;
D) contact hole groove is filled and formed trench plug;
E) deposition one deck aluminium copper, carries out metal etch by metal mask, makes to form source metal bed course, gate metal bed course and metal connecting line.
Wherein, described silicide is WSi2, TiSi2, MoSi2 or TaSi2.
The present invention has obvious advantage and good effect, adopt manufacture method of the present invention owing to having adopted mask plate, pollution and the conforming control of having avoided relevant operation to cause, reduce the manufacturing process of the grooved semiconductor device of self-aligned metal silicate, ensured the consistency of the electrical quantitys such as the threshold voltage of semiconductor device; Because manufacture method of the present invention is simple, easy, manufacturing process easily realizes, and the quality of device and reliability are greatly improved.
Brief description of the drawings
Accompanying drawing is used to provide a further understanding of the present invention, and forms a part for specification, together with embodiments of the present invention, for explaining the present invention, is not construed as limiting the invention.In the accompanying drawings:
Fig. 1 is grooved semiconductor device making method embodiment 1 flow chart according to self-aligned metal silicate of the present invention;
Fig. 2 position is according to depositing the first oxide layer in the grooved semiconductor device making method of self-aligned metal silicate of the present invention and form active region mask, B Implanted element schematic diagram;
Fig. 3 is according to the base forming in the grooved semiconductor device making method of self-aligned metal silicate of the present invention and trench mask schematic diagram;
Fig. 4 is according to etching groove in the grooved semiconductor device making method of self-aligned metal silicate of the present invention and generating the second oxide layer schematic diagram;
Fig. 5 is according to injecting P elements in the grooved semiconductor device making method of self-aligned metal silicate of the present invention, forming source region and grid (polysilicon) schematic diagram;
Fig. 6 is according to the silicide schematic diagram of source region in the grooved semiconductor device making method embodiment 1 of self-aligned metal silicate of the present invention and polysilicon surface generation;
Fig. 7 be according in the grooved semiconductor device making method embodiment 1 of self-aligned metal silicate of the present invention deposition and chemical mechanical polishing layer between medium schematic diagram;
Fig. 8 is according to the contact hole schematic diagram that utilizes contact hole mask to form in the grooved semiconductor device making method embodiment 1 of self-aligned metal silicate of the present invention;
Fig. 9 is according to expanding contact hole upper part in the grooved semiconductor device making method embodiment 1 of self-aligned metal silicate of the present invention and injecting the schematic diagram after P+;
Figure 10 is metal bed course and the metal connecting line schematic diagram forming according in the grooved semiconductor device making method embodiment 1 of self-aligned metal silicate of the present invention;
Figure 11 is grooved semiconductor device making method embodiment 2 flow charts according to self-aligned metal silicate of the present invention;
Figure 12 is according to utilizing the second base mask, the schematic diagram after B Implanted element in the grooved semiconductor device making method embodiment 2 of self-aligned metal silicate of the present invention;
Figure 13 is according to generating after silicide, along B-B ' cross section schematic diagram in Figure 12 in the second base and polysilicon surface in the grooved semiconductor device making method embodiment 2 of self-aligned metal silicate of the present invention;
Figure 14 be according in the grooved semiconductor device making method embodiment 2 of self-aligned metal silicate of the present invention at suicide surfaces Direct precipitation aluminium copper, after the metal bed course and metal connecting line of formation, along A-A ' cross section schematic diagram in Figure 12;
Figure 15 is grooved semiconductor device making method embodiment 3 flow charts according to self-aligned metal silicate of the present invention;
Figure 16 is according to the contact hole the B Implanted element schematic diagram that utilize contact hole mask to form in the grooved semiconductor device making method embodiment 3 of self-aligned metal silicate of the present invention;
Figure 17 is metal bed course and the metal connecting line schematic diagram forming by metal mask according in the grooved semiconductor device making method embodiment 3 of self-aligned metal silicate of the present invention;
Figure 18 is the disclosed semiconductor field effect transistor schematic diagram of american documentation literature in prior art (US20030168695A1);
Figure 19 is the disclosed semiconductor device schematic diagram of american documentation literature in prior art (US20070023828A1).
Embodiment
Below in conjunction with accompanying drawing, the preferred embodiments of the present invention are described, should be appreciated that preferred embodiment described herein, only for description and interpretation the present invention, is not intended to limit the present invention.
embodiment 1
Fig. 1 is grooved semiconductor device making method embodiment 1 flow chart according to self-aligned metal silicate of the present invention, below with reference to Fig. 1, the grooved semiconductor device making method embodiment 1 of self-aligned metal silicate of the present invention is described in detail:
First,, in step 101, utilize active region mask B Implanted element to form base.This step comprises: on the epitaxial loayer of substrate, adopt accumulation or hot growth pattern to generate the first oxide layer (oxide hard light shield), the thickness of the first oxide layer is about 8000; Etching the first oxide layer forms active region mask, then at the epitaxial loayer part B Implanted element exposing, as shown in Figure 2; Adopt annealing operation that boron element is advanced to be diffused in epitaxial loayer and form base, as shown in Figure 3;
In step 102, utilize trench mask to etch groove, and generate the second oxide layer.This step comprises: generate the worn-out oxide layer of screen in the epi-layer surface exposing, and deposition lithography coating, and it is carried out to etching formation trench mask, as shown in Figure 3; Utilize trench mask, expose epitaxial loayer partially-etched go out groove; Remove lithography coating, and the epitaxial loayer part, trenched side-wall and the lower surface that expose are sacrificed to oxidation, and then form the second oxide layer (grid oxic horizon), as shown in Figure 4;
In step 103, deposit spathic silicon, and inject P elements formation source region.In this step, the first polysilicon of deposition to adulterate in groove, and polysilicon is eat-back; Then, inject P elements, and adopt annealing operation that its propelling is diffused in base and forms source region, as shown in Figure 5;
In step 104, generate silicide in source region and polysilicon surface.This step comprises: the first, remove second oxide layer on surface, source region; The second, deposition transition metal, the operation of annealing is reacted metal and monocrystalline silicon and is formed silicide; The 3rd, the unreacted transition metal of Xuan Ze Erosion Ke Duo I, at polysilicon and source region Surface Creation silicide, as shown in Figure 6, the silicide of formation can be WSi2, TiSi2, MoSi2 or TaSi2.
In step 105, form contact hole groove by contact hole mask.First, at surface deposition one deck inter-level dielectric of device, and it is carried out to chemical mechanical polish process, make inter-level dielectric keep certain thickness, as shown in Figure 7; Secondly, at inter-level dielectric surface deposition one deck lithography coating, and it is carried out to etching, form contact hole mask; Finally, by contact hole mask, utilize dry method to etch in base and form contact hole groove by inter-level dielectric, as shown in Figure 8;
In step 106, in contact hole groove, inject p+(boron element), and its propelling is diffused into base.In this step, first utilize wet etching inter-level dielectric by contact hole mask, then remove lithography coating, in the most backward contact hole, inject P+, adopt quick high-temp annealing operation that its propelling is diffused in base, as shown in Figure 9;
In step 107, contact hole groove is filled and formed trench plug.In this step, successively use titanium/titanium nitride layer and tungsten layer to fill to form trench plug to contact hole groove, and etch is carried out in top layer, to remove titanium/titanium nitride and the tungsten of top layer;
In step 108, utilize metal mask to form metal bed course and line.First this device above deposit one deck aluminium copper, and anneal, then carry out metal etch by metal mask, form source metal bed course, gate metal bed course and metal connecting line, as shown in figure 10.
embodiment 2
Figure 11 is grooved semiconductor device making method embodiment 2 flow charts according to self-aligned metal silicate of the present invention, is described in detail below with reference to Figure 11:
At step 1101-1103, identical with the manufacture method of embodiment 1, refer step 101-103, repeats no more here;
In step 1104, in this step, first, deposition one deck lithography coating, and it is carried out to etching formation base mask, then B Implanted element, as shown in figure 12;
In step 1105, then adopt quick high-temp annealing operation, remove second oxide layer on lithography coating and surface, source region; Deposition transition metal, the operation of annealing is reacted metal and monocrystalline silicon and is formed silicide; The unreacted transition metal of Xuan Ze Erosion Ke Duo I, in the second base, source region and polysilicon surface generate silicide, as shown in Fig. 6 and Figure 13, the silicide of formation can be WSi2, TiSi2, MoSi2 or TaSi2;
In step 1106, in groove, deposit inter-level dielectric and eat-back;
In step 1107, at top layer deposition aluminium copper, make its directly contact silicide, form source metal bed course, gate metal bed course and metal connecting line, as shown in figure 14.
embodiment 3
Figure 15 is grooved semiconductor device making method embodiment 3 flow charts according to self-aligned metal silicate of the present invention, is described in detail below with reference to Figure 15:
At step 1501-1503, identical with the manufacture method of embodiment 1, refer step 101-103, repeats no more here;
In step 1504, deposition etching photolithograhic coating, form the first contact hole mask; Form contact hole groove by the first contact hole mask; To B Implanted element (P+) in contact hole groove, and its propelling is diffused into base, as shown in figure 16;
In step 1505, remove second oxide layer on lithography coating and surface, source region; Deposition transition metal, the operation of annealing is reacted metal and monocrystalline silicon and is formed silicide; The unreacted transition metal of Xuan Ze Erosion Ke Duo I, generates silicide in source region and polysilicon surface, and as shown in Figure 6, silicide is WSi2, TiSi2, MoSi2 or TaSi2;
In step 1506, the first step deposits inter-level dielectric and eat-backs in groove; Second step, deposition etching photolithograhic coating, form the second contact hole mask; The 3rd step, utilizes the second contact hole mask, the inter-level dielectric in etching contact hole;
In step 1507-1508, identical with the manufacture method of embodiment 1, refer step 107-108, repeats no more here.
Knot structure after metal bed course and the metal connecting line forming by metal mask in embodiment 3 as shown in figure 17.
Above-described embodiment is to describe with the manufacture process of the N-type channel groove type semiconductor power device of self-aligned metal silicate, for the manufacture of the P type passage semiconductor power device of self-aligned metal silicate, main difference is the type of alloy, adopt the method for above-described embodiment, change the type of alloy, equally can be for the manufacture of the P type passage semiconductor device of self-aligned metal silicate.
One of ordinary skill in the art will appreciate that, the foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, the present invention not exclusively relates to technique and the corresponding device of be used for producing the semiconductor devices (for example, device or bipolar diode or the Schottky diode of the device of MOS device or igbt (IGBT) type or bipolar junction transistor (BJT) type).
Although the present invention is had been described in detail with reference to previous embodiment, for a person skilled in the art, its technical scheme that still can record previous embodiment be modified, or part technical characterictic is wherein equal to replacement.Within the spirit and principles in the present invention all, any amendment of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.

Claims (12)

1. a manufacture method for the grooved semiconductor device of self-aligned metal silicate, the method comprises the following steps:
1) on the epitaxial loayer of substrate, deposit the first oxide layer, the first oxide layer forms active region mask described in etching, then in its propelling is diffused into epitaxial loayer by the epitaxial loayer part B Implanted element ， And exposing, forms base;
2) generate the worn-out oxide layer of screen in the epi-layer surface exposing, deposition lithography coating, and it is carried out to etching formation trench mask, utilize trench mask, expose epitaxial loayer partially-etched go out groove, remove lithography coating, and the epitaxial loayer part, trenched side-wall and the lower surface that expose are sacrificed to oxidation, and then form the second oxide layer;
3) in groove, deposition, with the polysilicon of doping, and is eat-back polysilicon, then injects P elements in the epitaxial loayer part exposing, and adopts annealing operation that its propelling is diffused into and in base, forms source region;
4) form silicide at described polysilicon and surface, source region;
5), at top layer deposition aluminium copper, form source metal bed course, gate metal bed course and metal connecting line.
2. the manufacture method of the grooved semiconductor device of self-aligned metal silicate according to claim 1, is characterized in that, further comprising the steps of between described step 3) and step 4): in groove, deposit inter-level dielectric and eat-back; At the epi-layer surface deposition lithography coating exposing, and it is carried out to etching form the second base mask; The epitaxial loayer part B Implanted element exposing.
3. the manufacture method of the grooved semiconductor device of self-aligned metal silicate according to claim 1, is characterized in that, further comprising the steps of between described step 3) and step 4):
A) in the epi-layer surface deposition the etching photolithograhic coating that expose, form the first contact hole mask;
B) etch contact hole groove by the first contact hole mask; To B Implanted element in contact hole groove, and its propelling is diffused into base.
4. the manufacture method of the grooved semiconductor device of self-aligned metal silicate according to claim 1, is characterized in that, described step 4) also comprises:
A) remove second oxide layer on surface, source region;
B) deposition transition metal, the operation of annealing is reacted metal and monocrystalline silicon and is formed silicide;
C) the unreacted transition metal of Xuan Ze Erosion Ke Duo I.
5. according to the manufacture method of the grooved semiconductor device of the self-aligned metal silicate described in claim 1 or 4, it is characterized in that, described silicide is WSi2, TiSi2, MoSi2 or TaSi2.
6. the manufacture method of the grooved semiconductor device of self-aligned metal silicate according to claim 1, is characterized in that, described step 5) is further comprising the steps:
A) form contact hole groove by contact hole mask;
B) contact hole groove is filled and formed trench plug;
C) on device, deposit deposition of aluminum copper alloy, and anneal, then carry out metal etch by metal mask, form source metal bed course, gate metal bed course and metal connecting line.
7. the manufacture method of the grooved semiconductor device of self-aligned metal silicate according to claim 6, is characterized in that, described step a) also comprises:
At surface deposition one deck inter-level dielectric of device, and it is carried out to chemical mechanical polish process; At inter-level dielectric surface deposition one deck lithography coating, and it is carried out to etching, form contact hole mask; By contact hole mask, utilize dry method to etch into and in base, form contact hole groove by inter-level dielectric; Utilize wet method, the contact hole in inter-level dielectric is expanded.
8. the manufacture method of the grooved semiconductor device of self-aligned metal silicate according to claim 6, is characterized in that, described step b) also comprises: to B Implanted element in contact hole groove, and its propelling is diffused into base; Successively use titanium/titanium nitride layer and tungsten layer to fill to form trench plug to contact hole groove, and etch is carried out in top layer, to remove titanium/titanium nitride and the tungsten of top layer.
9. the manufacture method of the grooved semiconductor device of self-aligned metal silicate according to claim 1, is characterized in that, is by direct described aluminium copper and silicide contacts in described step 5).
10. the manufacture method of the grooved semiconductor device of self-aligned metal silicate according to claim 1, is characterized in that, described step 5) is further comprising the steps:
A) in groove, deposit inter-level dielectric and eat-back;
B), in described inter-level dielectric surface deposition etching photolithograhic coating, form the second contact hole mask;
C) utilize the second contact hole mask, the inter-level dielectric in etching contact hole;
D) contact hole groove is filled and formed trench plug;
E) at surface deposition one deck aluminium copper of device, carry out metal etch by metal mask, make to form source metal bed course, gate metal bed course and metal connecting line.
The grooved semiconductor device of 11. 1 kinds of self-aligned metal silicate, is characterized in that, the N channel groove type semiconductor device that adopts the method manufacture described in claim 1-10 any one to form.
The grooved semiconductor device of 12. 1 kinds of self-aligned metal silicate, is characterized in that, the P channel groove type semiconductor device that adopts the method manufacture described in claim 1-10 any one to form.
CN201010523007.3A 2010-10-27 2010-10-27 Grooved semiconductor device of self-aligned metal silicide and manufacturing method thereof Active CN102456574B (en)

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CN106952957B (en) * 2017-02-09 2020-02-04 香港商莫斯飞特半导体有限公司 Longitudinal gallium nitride-based semiconductor device and manufacturing method thereof
CN108766965B (en) * 2018-08-03 2023-06-13 淄博汉林半导体有限公司 Groove type double MOS tube device shared by drain electrodes and manufacturing method
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