CN102157493B - Metal plug and manufacturing method thereof - Google Patents
Metal plug and manufacturing method thereof Download PDFInfo
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- CN102157493B CN102157493B CN201010108875.5A CN201010108875A CN102157493B CN 102157493 B CN102157493 B CN 102157493B CN 201010108875 A CN201010108875 A CN 201010108875A CN 102157493 B CN102157493 B CN 102157493B
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 169
- 239000002184 metal Substances 0.000 title claims abstract description 169
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 37
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 124
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 123
- 239000010703 silicon Substances 0.000 claims abstract description 123
- 239000000758 substrate Substances 0.000 claims abstract description 83
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 43
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 40
- 238000005516 engineering process Methods 0.000 claims abstract description 39
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims description 58
- 239000011248 coating agent Substances 0.000 claims description 24
- 238000000576 coating method Methods 0.000 claims description 24
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 19
- 229910000676 Si alloy Inorganic materials 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 18
- 238000000151 deposition Methods 0.000 claims description 17
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 16
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 16
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 15
- 239000010936 titanium Substances 0.000 claims description 15
- 229910052719 titanium Inorganic materials 0.000 claims description 15
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical group [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 claims description 13
- 239000010937 tungsten Substances 0.000 claims description 13
- 229910052721 tungsten Inorganic materials 0.000 claims description 13
- 238000001259 photo etching Methods 0.000 claims description 12
- 230000026267 regulation of growth Effects 0.000 claims description 11
- 239000012535 impurity Substances 0.000 claims description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims description 8
- 229910045601 alloy Inorganic materials 0.000 claims description 7
- 239000000956 alloy Substances 0.000 claims description 7
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 6
- AIOWANYIHSOXQY-UHFFFAOYSA-N cobalt silicon Chemical compound [Si].[Co] AIOWANYIHSOXQY-UHFFFAOYSA-N 0.000 claims description 6
- GALOTNBSUVEISR-UHFFFAOYSA-N molybdenum;silicon Chemical compound [Mo]#[Si] GALOTNBSUVEISR-UHFFFAOYSA-N 0.000 claims description 6
- 230000004224 protection Effects 0.000 claims description 6
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 239000004411 aluminium Substances 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000012528 membrane Substances 0.000 claims description 3
- LIZIAPBBPRPPLV-UHFFFAOYSA-N niobium silicon Chemical compound [Si].[Nb] LIZIAPBBPRPPLV-UHFFFAOYSA-N 0.000 claims description 3
- 238000006386 neutralization reaction Methods 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- 229920005591 polysilicon Polymers 0.000 abstract description 11
- 230000005611 electricity Effects 0.000 abstract description 7
- 238000009792 diffusion process Methods 0.000 abstract description 5
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 238000002955 isolation Methods 0.000 abstract description 3
- 229910044991 metal oxide Inorganic materials 0.000 abstract description 3
- 150000004706 metal oxides Chemical class 0.000 abstract description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 15
- 238000010586 diagram Methods 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 7
- NMJKIRUDPFBRHW-UHFFFAOYSA-N titanium Chemical compound [Ti].[Ti] NMJKIRUDPFBRHW-UHFFFAOYSA-N 0.000 description 7
- 229910001092 metal group alloy Inorganic materials 0.000 description 5
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 5
- 238000000137 annealing Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- MYHPJINPUDBKHX-UHFFFAOYSA-N [Si].[W].[Ti] Chemical compound [Si].[W].[Ti] MYHPJINPUDBKHX-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000002156 mixing Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000035755 proliferation Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical group [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- -1 silicon nitrides Chemical class 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
Abstract
The invention discloses a metal plug which is formed in a groove of a silicon substrate, and is used for the realization of electricity connection between a part which requires electricity connection in the silicon substrate and metal on the surface of the silicon substrate. The metal plug is composed of the combination of metallic silicides and doped polysilicon or doped amorphous silicon, or the combination of metal silicides and metal, or the combination of the metal and the doped polysilicon or the doped amorphous silicon, or the metal; and the isolation of the metal plug and the corresponding part of the silicon substrate at the direction of the side wall of the groove is realized through a medium, and the interconnection of the metal plug and the part which requires electricity connection in the silicon substrate in the bottom direction is realized. The invention also provides a manufacturing method of the metal plug. The metal plug provided by the invention can be used as a sinker layer of an RFLDMOS (radio frequency landscape diffusion metal oxide semi-conductor) device, the resistance and size of the device can be reduced, the frequency property of the device can be improved, and can be easily integrated with the existing technology.
Description
Technical field
The present invention relates to semiconductor integrated circuit and make the field, particularly relate to a kind of metal closures, the invention still further relates to the manufacture method of this metal closures.
Background technology
Radio frequency Laterally Diffused Metal Oxide Semiconductor (RFLDMOS) is a kind of device that good market is arranged.Particularly along with the extensive use of the communication technology, it will more and more be paid attention to as a kind of novel power device.
As shown in Figure 1, be the basic structure of existing RFLDMOS: adopting the substrate of mixing the high concentration p type impurity is the P+ substrate, and the scope of the resistivity of described P+ substrate is 0.01 ohmcm～0.02 ohmcm; On described P+ substrate according to the P type epitaxial loayer of different growth different-thickness of the requirement of device withstand voltage and doping content, for example for withstand voltage be 60 volts device, the thickness of described P type epitaxial loayer is 5 microns～8 microns; Utilize ion to inject and diffusion technology formation P+ sinking layer (P+SINKER); Form the P trap, grid oxide layer and grid; The N-drift region, N+ source region and N+ drain region, and the formation surface electrode is source electrode, drain and gate; Deposit back metal after described P+ substrate back is carried out attenuate at last, this back metal links to each other with source electrode by described P+ substrate, the P+ layer that sinks.
As from the foregoing, the structure of existing RFLDMOS is to adopt diffusion technology to form described P+ sinking layer, and the horizontal proliferation meeting in this diffusion technology makes the area of device be difficult to dwindle; And the described P+ sinking layer resistance that forms is higher, and this has also influenced the operating frequency of the performance of device, particularly device.For addressing the above problem, it is to adopt the P+ polysilicon to make described P+ lower floor that a kind of improvement way is arranged, though but adopt the P+ polysilicon improvement all to be arranged at above-mentioned two aspect characteristics, but it has the problem of two aspects: the one, and the P+ polysilicon process is not because the technology controlling and process problem has widespread usage, and the maturity of its technology still has problem; The 2nd, adopt that diffusion problem still exists after it, resistance is still higher.
Summary of the invention
Technical problem to be solved by this invention provides a kind of metal closures, can be as the sinking layer of RFLDMOS device, and reduce the resistance of device and size, and can improve the frequency characteristic of device and be easy to existing technology integrated; The present invention also provides the manufacture method of this metal closures for this reason.
For solving the problems of the technologies described above, metal closures provided by the invention is formed in the groove of silicon substrate, realizes that with the intermetallic on the described surface of silicon electricity is connected in order to the part that needs electricity to connect in described silicon substrate.
Described metal closures is combined by metal silicide and doped polycrystalline silicon or doping amorphous silicon, and described metal silicide is formed at described channel bottom, described doped polycrystalline silicon or doping amorphous silicon and is formed on the described metal silicide.
Perhaps, described metal closures is combined by metal silicide and metal, and described metal silicide is formed at described channel bottom, described metal is formed on the described metal silicide.
Perhaps, described metal closures is combined by metal and doped polycrystalline silicon or doping amorphous silicon, and described metal is formed at described channel bottom, described doped polycrystalline silicon or doping amorphous silicon and is formed on the described metal silicide.
Perhaps, described metal closures is made up of a kind of metal.
Further improvement is, described metal closures by the isolation of dielectric layer realization with the appropriate section of described silicon substrate, needs the interconnected of electricity coupling part in the trenched side-wall direction on bottom direction realization and described silicon substrate.
Further improving is that described metal silicide is titanium silicon or cobalt silicon alloy or niobium-silicon alloy or molybdenum-silicon alloy.Described metal is the combination of tungsten, tungsten silicon or titanium or titanium nitride or aluminium or copper or above-mentioned metal.The impurity of described doped polycrystalline silicon or doping amorphous silicon is P type or N type.
For solving the problems of the technologies described above, the manufacture method of a kind of metal closures provided by the invention comprises following steps:
Step 1, on silicon substrate growth regulation one deck medium one and second layer medium two successively, utilize photoetching, etching technics on described silicon substrate, to form groove figure;
Step 2, form the 3rd layer of medium one, form the 4th layer of medium two at described channel bottom and sidewall and described surface of silicon substrate at the bottom and the sidewall of described groove;
Step 3, the 4th layer of medium two of described channel bottom removed, keep the 4th layer of medium two existence of described trenched side-wall by anti-carving technology;
Step 4, the 3rd layer of medium one of described channel bottom removed;
Step 5, described the 4th layer of medium two and described second layer medium two are all removed, obtaining described channel bottom does not have dielectric layer, and described trenched side-wall remains with the structure that the 3rd layer of medium one and described substrate surface remain with ground floor medium one;
Step 6, at described channel bottom, sidewall and described surface of silicon depositing metal;
Step 7, form metal-silicide alloy at described channel bottom; And the described metal etch on the medium one of described trenched side-wall, described surface of silicon fallen;
Step 8, at described groove and described surface of silicon deposit doped polycrystalline silicon or doping amorphous silicon;
Step 9, utilize and to anti-carve or cmp removes the doped polycrystalline silicon or the doping amorphous silicon of described surface of silicon.
The manufacture method of second kind of metal closures provided by the invention comprises following steps:
Step 1, on silicon substrate growth regulation one deck medium one and second layer medium two successively, utilize photoetching, etching technics on described silicon substrate, to form groove figure;
Step 2, form the 3rd layer of medium one, form the 4th layer of medium two at described channel bottom and sidewall and described surface of silicon substrate at the bottom and the sidewall of described groove;
Step 3, the 4th layer of medium two of described channel bottom removed, keep the 4th layer of medium two existence of described trenched side-wall by anti-carving technology;
Step 4, the 3rd layer of medium one of described channel bottom removed;
Step 5, described the 4th layer of medium two and described second layer medium two are all removed, obtaining described channel bottom does not have dielectric layer, and described trenched side-wall remains with the structure that the 3rd layer of medium one and described substrate surface remain with ground floor medium one;
Step 6, at described channel bottom, sidewall and described surface of silicon depositing metal or metal silicide, described metal or metal silicide do not fill up described groove;
Step 7, form a coating on described groove and described silicon substrate, described coating is photoresist or antireflecting coating or organic membrane, and described coating is filled up described groove; Coating with described surface of silicon and groove top etches away again;
Step 8, described trenched side-wall top is not etched away by metal or metal silicide on the ground floor medium one of the metal of described coating covering protection or metal silicide and described surface of silicon;
Step 9, at described groove and described surface of silicon deposit doped polycrystalline silicon or doping amorphous silicon;
Step 10, utilize and to anti-carve or cmp removes the doped polycrystalline silicon or the doping amorphous silicon of described surface of silicon.
The manufacture method of the third metal closures provided by the invention comprises following steps:
Step 1, on silicon substrate growth regulation one deck medium one and second layer medium two successively, utilize photoetching, etching technics on described silicon substrate, to form groove figure;
Step 2, form the 3rd layer of medium one, form the 4th layer of medium two at described channel bottom and sidewall and described surface of silicon substrate at the bottom and the sidewall of described groove;
Step 3, the 4th layer of medium two of described channel bottom removed, keep the 4th layer of medium two existence of described trenched side-wall by anti-carving technology;
Step 4, the 3rd layer of medium one of described channel bottom removed;
Step 5, described the 4th layer of medium two and described second layer medium two are all removed, obtaining described channel bottom does not have dielectric layer, and described trenched side-wall remains with the structure that the 3rd layer of medium one and described substrate surface remain with ground floor medium one;
Step 6, at described channel bottom, sidewall and described surface of silicon depositing metal;
Step 7, form metal-silicide alloy at described channel bottom; And the described metal etch on the medium one of described trenched side-wall, described surface of silicon fallen;
Step 8, at groove and described surface of silicon depositing metal;
Step 9, utilize and to anti-carve or cmp removes the metal of described surface of silicon.
The manufacture method of the 4th kind of metal closures provided by the invention comprises following steps:
Step 1, on silicon substrate growth regulation one deck medium one and second layer medium two successively, utilize photoetching, etching technics on described silicon substrate, to form groove figure;
Step 2, form the 3rd layer of medium one, form the 4th layer of medium two at described channel bottom and sidewall and described surface of silicon substrate at the bottom and the sidewall of described groove;
Step 3, the 4th layer of medium two of described channel bottom removed, keep the 4th layer of medium two existence of described trenched side-wall by anti-carving technology;
Step 4, the 3rd layer of medium one of described channel bottom removed;
Step 5, described the 4th layer of medium two and described second layer medium two are all removed, obtaining described channel bottom does not have dielectric layer, and described trenched side-wall remains with the structure that the 3rd layer of medium one and described substrate surface remain with ground floor medium one;
Step 6, at described channel bottom, sidewall and described surface of silicon depositing metal or metal alloy, and described groove filled up;
Step 7, utilize wet method to anti-carve technology the metal or metal alloy on the ground floor medium one of described groove top and described surface of silicon is etched away;
Step 8, at surface of silicon deposit doped polycrystalline silicon or doping amorphous silicon shown in the neutralization of described groove;
Step 9, utilize anti-carve or cmp will shown in the described doped polycrystalline silicon or the doping amorphous silicon of surface of silicon remove.
The manufacture method of the 5th kind of metal closures provided by the invention comprises following steps:
Step 1, on silicon substrate growth regulation one deck medium one and second layer medium two successively, utilize photoetching, etching technics on described silicon substrate, to form groove figure;
Step 2, form the 3rd layer of medium one, form the 4th layer of medium two at described channel bottom and sidewall and described surface of silicon substrate at the bottom and the sidewall of described groove;
Step 3, the 4th layer of medium two of described channel bottom removed, keep the 4th layer of medium two existence of described trenched side-wall by anti-carving technology;
Step 4, the 3rd layer of medium one of described channel bottom removed;
Step 5, described the 4th layer of medium two and described second layer medium two are all removed, obtaining described channel bottom does not have dielectric layer, and described trenched side-wall remains with the structure that the 3rd layer of medium one and described substrate surface remain with ground floor medium one;
Step 6, at described channel bottom, sidewall and described surface of silicon depositing metal;
Step 7, utilization anti-carves or cmp falls the metal etch on the ground floor medium one of described surface of silicon.
Further be improved to, described metal silicide is titanium silicon or cobalt silicon alloy or niobium-silicon alloy or molybdenum-silicon alloy.Described metal is the combination of tungsten, tungsten silicon or titanium or titanium nitride or aluminium or copper or above-mentioned metal.The impurity of described doped polycrystalline silicon or doping amorphous silicon is P type or N type; The growth temperature of described doped polycrystalline silicon is 600 degree～680 degree; The growth temperature of described doping amorphous silicon is 500 degree～570 degree.Described medium one is a silica, and described medium two is a silicon nitride.
Metal closures of the present invention, the part that needs electricity to connect in the silicon substrate can be realized being connected with the metal on the surface of silicon, can be applied to the sinking layer in the radio frequency Laterally Diffused Metal Oxide Semiconductor (RFLDMOS), because the shortcoming that described metal closures has good electrical conductivity and do not have the P+ sinking layer horizontal proliferation in the existing RFLDMOS device, therefore can reduce the resistance and the size of described RFLDMOS device, thereby improve the frequency characteristic of device.The present invention also provides the manufacture method of described metal closures, is easy to existing technology integrated.
Description of drawings
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments:
Fig. 1 is the structural representation of existing RFLDMOS device;
Fig. 2 A is the structural representation of the embodiment of the invention one metal closures RFLDMOS device;
Fig. 2 B is the structural representation of the embodiment of the invention two metal closures RFLDMOS devices;
Fig. 2 C is the structural representation of the embodiment of the invention three metal closures RFLDMOS devices;
Fig. 2 D is the structural representation of the embodiment of the invention four metal closures RFLDMOS devices;
Fig. 3 A to Fig. 3 I is the device architecture schematic diagram in each step of first kind of manufacture method of the embodiment of the invention one metal closures RFLDMOS device;
Fig. 4 A to Fig. 4 C is the device architecture schematic diagram in each step of second kind of manufacture method of the embodiment of the invention one metal closures RFLDMOS device;
Fig. 5 A to Fig. 5 B is the device architecture schematic diagram in each step of the third manufacture method of the embodiment of the invention one metal closures RFLDMOS device;
Fig. 6 A to Fig. 6 B is the device architecture schematic diagram in each step of the 4th kind of manufacture method of the embodiment of the invention one metal closures RFLDMOS device;
Fig. 7 A to Fig. 7 D is the device architecture schematic diagram in each step of the 5th kind of manufacture method of the embodiment of the invention one metal closures RFLDMOS device.
Embodiment
Shown in Fig. 2 A, be the structural representation of the embodiment of the invention one metal closures RFLDMOS device.The silicon substrate that the high concentration p type impurity is mixed in employing is a P+ silicon substrate 11, and the scope of the resistivity of described P+ silicon substrate 11 is 0.01 ohmcm～0.02 ohmcm.On described P+ silicon substrate 11, form a P type epitaxial loayer 12.In described epitaxial loayer 12, form an embodiment of the invention one metal closures, described metal closures is to form in the groove of described epitaxial loayer 12, combined by metal or metal alloy such as titanium silicon 17 and doped polycrystalline silicon or amorphous silicon 18, described metal or metal alloy also can be titanium, titanium nitride, tungsten, tungsten silicon, titanium-tungsten double-decker, titanium-titanium nitride-tungsten three-decker, cobalt silicon alloy or molybdenum-silicon alloy.Described metal closures is interconnected by the titanium silicon 17 and 11 realizations of described P+ silicon substrate of bottom, and described metal closures is implemented in the isolation of the appropriate section of described epitaxial loayer 12 by silicon oxide film 15 in sidewall direction.Embodiment of the invention metal gate RFLDMOS device also is formed with P trap 111, grid oxide layer 19 and grid 110; N-drift region 112, N+ source region 114 and N+ drain region 114, and the formation surface electrode is source electrode 117, drain electrode 118 and grid.In described P trap 111, also be formed with P+ district 116, in order to the ohmic contact of 111 of the metal in the contact hole 115 of realizing described source electrode 117 and described P traps.Deposit back metal 119 after attenuate is carried out at described P+ silicon substrate 11 back sides at last, this back metal 119 links to each other with source electrode by described P+ substrate 11, described metal closures.
Shown in Fig. 2 B, be inventive embodiments two metal closures RFLDMOS device architecture figure, different with the embodiment one shown in Fig. 2 A is, contacting between described N+ source electrode 114 and the described P trap 111 is by injecting the modes that realize P+ injection region 216 at surface region to 111 of described P traps.
Shown in Fig. 2 C, be the embodiment of the invention three metal closures RFLDMOS device architecture figure, different with the embodiment one shown in Fig. 2 A is, when described P trap 111 concentration greater than 1E17CM
-3The time, described N+ source electrode 114 directly links to each other with described P trap 111 by contact hole 315 and forms ohmic contact.
Shown in Fig. 2 D, be the embodiment of the invention four metal closures RFLDMOS device architecture figure, different with the embodiment one shown in Fig. 2 A is, described N+ source electrode 114 is to realize and being connected of described P trap 111 by described metal closures, described P+ substrate 11 and described P type epitaxial loayer 12.
Shown in Fig. 3 A to Fig. 3 I, be the device architecture schematic diagram in each step of first kind of manufacture method of the embodiment of the invention one metal closures RFLDMOS device.Comprise the steps:
Step 1, as shown in Figure 3A, growth P type epitaxial loayer 12 on P+ silicon substrate 11.Described P+ silicon substrate 11 is mixed with boron impurity, and resistivity is 0.01 ohmcm～0.02 ohmcm; The doping content of described P type epitaxial loayer 12 and thickness can be different and adjust by the design of device withstand voltage, and when being 60 volts, the resistivity of employing is 10 ohmcms～20 ohmcms as withstand voltage, and thickness is 5 microns～8 microns.Silicon oxide deposition film 120 and silicon nitride film 121 successively from lower to upper on described P type epitaxial loayer 12 afterwards, described silicon oxide film 120 thickness are 150 dusts～1000 dusts, the thickness of described silicon nitride film 121 is 500 dusts～3000 dusts.Resist coating carries out the photoresist figure of photoetching, developing process definition place groove on described silicon nitride film 121 afterwards, forms the photoresist window in the place that will form groove.Utilize photoresist to do mask again and carry out etching formation groove 14, described groove 14 will be carved through the bottom that in the described P+ silicon substrate 11 is described groove 14 and will enter in the described P+ silicon substrate 11, afterwards photoresist is removed.
Step 2, shown in Fig. 3 B, silicon oxide deposition film 15 on the sidewall of described groove 14 and bottom, silicon oxide film 15 can adopt boiler tube technology to grow, the thickness of formation is 150 dusts～1000 dusts.Deposition silicon nitride film 131, described silicon nitride film 131 is formed on the surface of the sidewall of described raceway groove and bottom and described silicon nitride film 121, thickness is 100 dusts～500 dusts, the thickness of described silicon nitride film 131 should have enough process windows so that groove 14 bottom silicon nitrides afterwards return carving technology less than the thickness of described silicon nitride film 121.
Step 3, shown in Fig. 3 C, the silicon nitride film 131 of described groove 14 bottoms is etched away fully, adopt anisotropic etching technics during etching so that after the etching silicon nitride film 131 of described groove 14 sidewalls certain reservation thickness is arranged, this reservation thickness will be thicker than 150 dusts, and at the described silicon nitride film 121 and the silicon nitride film 131 of described P+ surface of silicon certain thickness greater than 150 dusts that remains with is arranged also.Utilize the silicon nitride film of the described P+ surface of silicon of included reservation and described groove 14 sidewalls to do the protection of the silicon oxide film 15 of the silicon oxide film 120 of described P+ surface of silicon and described groove 14 sidewalls afterwards, adopt wet method and dry etch process that the silicon oxide film 15 of described groove 14 bottoms is etched away.
Step 4, shown in Fig. 3 D, utilize wet method or dry etch process that silicon nitride film is finished removal, just obtain having only groove 14 bottoms not have the structure of silicon oxide film 15.
Step 5, shown in Fig. 3 E, at described P+ surface of silicon depositing metal such as titanium, thickness is 100 dusts～1000 dusts, institute's metals deposited titanium directly contacts with described P+ silicon substrate 11 in the bottom of described groove 14, contacts with described silicon oxide film 15 or 20 in other place of described groove 14 and substrate surface.
Step 6, shown in Fig. 3 F, carry out rta technique and make the direct contact position of titanium and silicon form titanium silicon; Described rta technique can be selected to carry out at twice, also can once finish; Primary annealing temperature is that 640 degree～750 degree, secondary annealing temperature are 790 degree～860 degree when carrying out at twice, wherein will carry out the etching of a residual titanium after the annealing for the first time.
Step 7, shown in Fig. 3 G, owing between the titanium of the sidewall of described groove 14 and substrate surface and silicon, silicon oxide film is arranged, the titanium of this part can not form alloy, therefore after the annealing in process, remain Titanium on the silicon oxide film of the sidewall of described groove 14 and substrate surface, utilize wet etching to get rid of this part metals titanium, described wet method liquid can not cause etching to titanium silicon, therefore after changing the titanium removal on the silicon fiml, form a structure that contains titanium silicon at described channel bottom.
Step 8, shown in Fig. 3 H, doped polycrystalline silicon or doping amorphous silicon 18 are deposited on described groove 14 and the surface of silicon.As to adopt polysilicon, the technological temperature of the described polysilicon of deposit be 600 degree～670 degree, and as adopting amorphous silicon, the technological temperature of the described amorphous silicon of deposit is 500 degree～550 degree.The doping of described polysilicon or amorphous silicon 18 can be for N type impurity liquid, also can be p type impurity, and impurity concentration is greater than 1E19CM
-3, described groove 14 to be filled up after described polysilicon or amorphous silicon 18 deposits are finished.
Step 9, shown in Fig. 3 I, utilize to anti-carve or cmp is removed surface of silicon polysilicon or amorphous silicon 18.Thereby formed the metal closures of the embodiment of the invention.
Step 10, as shown in Figure 2 forms P trap 111, grid oxide layer 19 and the grid 110 of the embodiment of the invention one metal closures RFLDMOS, forms N-drift region 112, N+ source region 114 and N+ drain region 114, and to form surface electrode be source electrode, drain and gate.In described P trap 111, also to form P+ district 116, in order to realize the ohmic contact of 111 of described source electrode and described P traps.Deposit back metal after attenuate is carried out at described P+ silicon substrate 11 back sides at last, this back metal links to each other with source electrode by described P+ substrate, described metal closures.
In the embodiment of the invention one metal closures RFLDMOS device, owing to adopted the P+ sinking layer in the existing RFLDMOS device of metal closures structure replacement, and this metal closures is made up of alloy and doped polycrystalline silicon or doping amorphous silicon, and sidewall direction and P type epitaxial loayer zone aerobic silicon fiml at described metal closures are isolated, therefore the impurity in doped polycrystalline silicon or the doping amorphous silicon can not be diffused into the outer Yanzhong of P type, thereby the sinking layer size that described metal closures is formed can be done very for a short time, as less than 1 micron.
Simultaneously, because described doped polycrystalline silicon or doping amorphous silicon realize that with contacting by titanium silicon of described P+ silicon substrate therefore mixing is not limited to the P type, can be that the P type can be the N type also, make employing general, ripe N+ doping process is called possibility.
Simultaneously, because described doped polycrystalline silicon or doping amorphous silicon are finished titanium silicon and are covered in the bottom, therefore the technology that forms described titanium silicon can be carried out before grid oxygen forms, and do not need to consider to having the pollution problem of technology now, and only need according in the requirement to the temperature of back of the electric property of the metal or alloy of bottom, the temperature of coming the design subsequent high-temperature technology.For example,, may cause that resistance becomes big, advise that therefore follow-up temperature is lower than 900 degree because too high-temperature may make the attitude that resembles of titanium silicon change for titanium silicon; The follow-up temperature of cobalt silicon alloy suggestion is lower than 900 degree; To molybdenum-silicon alloy,, just do not need to consider this problem because it can bear high temperature.
Shown in Fig. 4 A, Fig. 4 B, Fig. 4 C and Fig. 3 G, the device architecture schematic diagram for second kind of manufacture method of the embodiment of the invention one metal closures RFLDMOS device comprises the steps:
Adopt the step identical with first kind of manufacture method up to metal and metal silicide such as the titanizing silicon alloy 17 of formation shown in Fig. 3 F, described metal or metal alloy also can be titanium, titanium nitride, titanium-tungsten double-decker, titanium-titanium nitride-tungsten three-decker, cobalt silicon alloy or molybdenum-silicon alloy;
Shown in Fig. 4 A, coated 140, described coating 140 is photoresist or antireflecting coating;
Shown in Fig. 4 B, etch away by dry method or wet-etching technology coating 140 again surface of silicon and described groove 14 tops;
Shown in Fig. 4 C, will do not etched away by the metal and the metal silicide of described coating 140 protections by dry method or wet-etching technology;
Shown in Fig. 3 G, at last described coating 140 is all removed, formed the structure that only contains titanizing silicon alloy 17 in described groove 14 bottoms.Follow-up other step is the same with first kind of manufacture method.The metal of the embodiment of the invention one metal closures bottom or metal silicide such as titanium, titanium nitride, titanium-tungsten double-decker, titanium-titanium nitride-tungsten three-decker etc. all have good reliability, and be verified, and good heatproof characteristic can be arranged, the restriction of the thermal process after not needing to consider is easy to integrated.
The thickness of oxide-film silicon 15 as described in as shown in Fig. 2 A, if according to designs require with technology before in silicon oxide film variable thickness sample, corresponding method of manufacture can be adjusted, shown in Fig. 5 A to Fig. 5 B, the device architecture schematic diagram of the third manufacture method of the embodiment of the invention one metal closures RFLDMOS device, corresponding method of adjustment is:
Adopt the step identical after the structure that forms shown in Fig. 3 G, after described metal silicide such as titanizing silicon alloy 17 form,, obtain the structure shown in Fig. 5 A 15 removals of original sidewall oxidation silicon fiml with first kind of manufacture method;
Shown in Fig. 5 B, the silicon oxide film 55 of deposit desired thickness more afterwards, this silicon oxide film 55 can adopt the thermal oxidation technology growth; Subsequent step is identical to step 10 with first kind of manufacture method step 8.
Metal closures sinking layer also can be the simple layer metal closures as described in as shown in Fig. 2 A, shown in Fig. 6 A to 6B, the device architecture schematic diagram of the 4th kind of manufacture method of the embodiment of the invention one metal closures RFLDMOS device, realize that the manufacture method that contains the simple layer metal closures is:
After the step 4 shown in Fig. 3 D is finished, carry out metal film 68 deposits and just groove fill up, obtain structure as shown in Figure 6A;
Shown in Fig. 6 B, utilization anti-carves or cmp is removed the metal film 68 of surface of silicon; Form device according to first kind of step of manufacturing ten at last.
The technology of described the 4th kind of manufacture method will be considered the integration of technology, if described metal film 68 is tungsten or tungsten silicon, its formation step need be after grid form so; If can not resistant to elevated temperatures metal film, this metal film will carry out after all high-temperature technologies are finished so; If described metal film adopts titanium-tungsten double-decker, titanium-titanium nitride-tungsten three-decker, titanium-tungsten silicon double-decker, titanium-titanium nitride-tungsten silicon three-decker, because these structures have good heatproof characteristic, the restriction of the thermal process after not needing to consider is easy to integrated.
The composition structure of metal closures sinking layer also can be that lower metal layer adds top doped polycrystalline silicon or doping amorphous silicon as described in as shown in Fig. 2 A.Shown in Fig. 7 A to 7D, the device architecture schematic diagram of the 5th kind of manufacture method of the embodiment of the invention one metal closures RFLDMOS device, the manufacture method of described metal closures structure is:
Shown in Fig. 7 A, after the step 4 shown in Fig. 3 D is finished, advanced row metal film 76 deposits;
Shown in Fig. 7 B, afterwards with most of metal film 76 etchings on surface of silicon and groove top, the metal film 76 that stays described channel bottom forms with described silicon substrate and contacts;
Shown in Fig. 7 C, carry out deposit doped polycrystalline silicon or doping amorphous silicon 77 again;
Shown in Fig. 7 D, utilization at last anti-carves or cmp is removed the doped polycrystalline silicon or the doping amorphous silicon of surface of silicon, thereby forms described metal closures sinking layer; Subsequent step is identical with described first kind of step of manufacturing ten.In said structure, owing under described polysilicon or the amorphous silicon metal is arranged, therefore integrated the going up of technology will be considered to some extent: if described metal film 76 is tungsten or tungsten silicon, it need just can after grid form so, if can not resistant to elevated temperatures metal film, it will carry out after all high-temperature technologies are finished so; If described metal film adopts titanium-tungsten double-decker, titanium-titanium nitride-tungsten three-decker, titanium-tungsten silicon double-decker, titanium-titanium nitride-tungsten silicon three-decker, because these structures have good heatproof characteristic, the restriction of the thermal process after not needing to consider is easy to integrated.
More than by specific embodiment the present invention is had been described in detail, but these are not to be construed as limiting the invention.Under the situation that does not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (10)
1. the manufacture method of a metal closures is characterized in that, comprises following steps:
Step 1, on silicon substrate growth regulation one deck medium one and second layer medium two successively, utilize photoetching, etching technics on described silicon substrate, to form groove figure;
Step 2, form the 3rd layer of medium one, form the 4th layer of medium two at described channel bottom and sidewall and described surface of silicon substrate at the bottom and the sidewall of described groove;
Step 3, the 4th layer of medium two of described channel bottom removed, keep the 4th layer of medium two existence of described trenched side-wall by anti-carving technology;
Step 4, the 3rd layer of medium one of described channel bottom removed;
Step 5, described the 4th layer of medium two and described second layer medium two are all removed, obtaining described channel bottom does not have dielectric layer, and described trenched side-wall remains with the structure that the 3rd layer of medium one and described substrate surface remain with ground floor medium one;
Step 6, at described channel bottom, sidewall and described surface of silicon depositing metal;
Step 7, form metal-silicide alloy at described channel bottom; And the described metal etch on the medium one of described trenched side-wall, described surface of silicon fallen;
Step 8, at described groove and described surface of silicon deposit doped polycrystalline silicon or doping amorphous silicon;
Step 9, utilize and to anti-carve or cmp removes the doped polycrystalline silicon or the doping amorphous silicon of described surface of silicon.
2. the manufacture method of a metal closures is characterized in that, comprises following steps:
Step 1, on silicon substrate growth regulation one deck medium one and second layer medium two successively, utilize photoetching, etching technics on described silicon substrate, to form groove figure;
Step 2, form the 3rd layer of medium one, form the 4th layer of medium two at described channel bottom and sidewall and described surface of silicon substrate at the bottom and the sidewall of described groove;
Step 3, the 4th layer of medium two of described channel bottom removed, keep the 4th layer of medium two existence of described trenched side-wall by anti-carving technology;
Step 4, the 3rd layer of medium one of described channel bottom removed;
Step 5, described the 4th layer of medium two and described second layer medium two are all removed, obtaining described channel bottom does not have dielectric layer, and described trenched side-wall remains with the structure that the 3rd layer of medium one and described substrate surface remain with ground floor medium one;
Step 6, at described channel bottom, sidewall and described surface of silicon depositing metal silicide, described metal silicide does not fill up described groove;
Step 7, form a coating on described groove and described silicon substrate, described coating is photoresist or antireflecting coating or organic membrane, and described coating is filled up described groove; Coating with described surface of silicon and groove top etches away again;
Step 8, described trenched side-wall top is not etched away by the metal silicide on the ground floor medium one of the metal silicide of described coating covering protection and described surface of silicon;
Step 9, at described groove and described surface of silicon deposit doped polycrystalline silicon or doping amorphous silicon;
Step 10, utilize and to anti-carve or cmp removes the doped polycrystalline silicon or the doping amorphous silicon of described surface of silicon.
3. the manufacture method of a metal closures is characterized in that, comprises following steps:
Step 1, on silicon substrate growth regulation one deck medium one and second layer medium two successively, utilize photoetching, etching technics on described silicon substrate, to form groove figure;
Step 2, form the 3rd layer of medium one, form the 4th layer of medium two at described channel bottom and sidewall and described surface of silicon substrate at the bottom and the sidewall of described groove;
Step 3, the 4th layer of medium two of described channel bottom removed, keep the 4th layer of medium two existence of described trenched side-wall by anti-carving technology;
Step 4, the 3rd layer of medium one of described channel bottom removed;
Step 5, described the 4th layer of medium two and described second layer medium two are all removed, obtaining described channel bottom does not have dielectric layer, and described trenched side-wall remains with the structure that the 3rd layer of medium one and described substrate surface remain with ground floor medium one;
Step 6, at described channel bottom, sidewall and described surface of silicon depositing metal, described metal does not fill up described groove;
Step 7, form a coating on described groove and described silicon substrate, described coating is photoresist or antireflecting coating or organic membrane, and described coating is filled up described groove; Coating with described surface of silicon and groove top etches away again;
Step 8, described trenched side-wall top is not fallen by the metal etch on the ground floor medium one of the metal of described coating covering protection and described surface of silicon;
Step 9, at described groove and described surface of silicon deposit doped polycrystalline silicon or doping amorphous silicon;
Step 10, utilize and to anti-carve or cmp removes the doped polycrystalline silicon or the doping amorphous silicon of described surface of silicon.
4. the manufacture method of a metal closures is characterized in that, comprises following steps:
Step 1, on silicon substrate growth regulation one deck medium one and second layer medium two successively, utilize photoetching, etching technics on described silicon substrate, to form groove figure;
Step 2, form the 3rd layer of medium one, form the 4th layer of medium two at described channel bottom and sidewall and described surface of silicon substrate at the bottom and the sidewall of described groove;
Step 3, the 4th layer of medium two of described channel bottom removed, keep the 4th layer of medium two existence of described trenched side-wall by anti-carving technology;
Step 4, the 3rd layer of medium one of described channel bottom removed;
Step 5, described the 4th layer of medium two and described second layer medium two are all removed, obtaining described channel bottom does not have dielectric layer, and described trenched side-wall remains with the structure that the 3rd layer of medium one and described substrate surface remain with ground floor medium one;
Step 6, at described channel bottom, sidewall and described surface of silicon depositing metal;
Step 7, form metal-silicide alloy at described channel bottom; And the described metal etch on the medium one of described trenched side-wall, described surface of silicon fallen;
Step 8, at groove and described surface of silicon depositing metal;
Step 9, utilize and to anti-carve or cmp removes the metal of described surface of silicon.
5. the manufacture method of a metal closures is characterized in that, comprises following steps:
Step 1, on silicon substrate growth regulation one deck medium one and second layer medium two successively, utilize photoetching, etching technics on described silicon substrate, to form groove figure;
Step 2, form the 3rd layer of medium one, form the 4th layer of medium two at described channel bottom and sidewall and described surface of silicon substrate at the bottom and the sidewall of described groove;
Step 3, the 4th layer of medium two of described channel bottom removed, keep the 4th layer of medium two existence of described trenched side-wall by anti-carving technology;
Step 4, the 3rd layer of medium one of described channel bottom removed;
Step 5, described the 4th layer of medium two and described second layer medium two are all removed, obtaining described channel bottom does not have dielectric layer, and described trenched side-wall remains with the structure that the 3rd layer of medium one and described substrate surface remain with ground floor medium one;
Step 6, at described channel bottom, sidewall and described surface of silicon depositing metal, and described groove filled up;
Step 7, utilize wet method to anti-carve technology the metal etch on the ground floor medium one of described groove top and described surface of silicon is fallen;
Step 8, at surface of silicon deposit doped polycrystalline silicon or doping amorphous silicon shown in the neutralization of described groove;
Step 9, utilize anti-carve or cmp will shown in the described doped polycrystalline silicon or the doping amorphous silicon of surface of silicon remove.
6. the manufacture method of a metal closures is characterized in that, comprises following steps:
Step 1, on silicon substrate growth regulation one deck medium one and second layer medium two successively, utilize photoetching, etching technics on described silicon substrate, to form groove figure;
Step 2, form the 3rd layer of medium one, form the 4th layer of medium two at described channel bottom and sidewall and described surface of silicon substrate at the bottom and the sidewall of described groove;
Step 3, the 4th layer of medium two of described channel bottom removed, keep the 4th layer of medium two existence of described trenched side-wall by anti-carving technology;
Step 4, the 3rd layer of medium one of described channel bottom removed;
Step 5, described the 4th layer of medium two and described second layer medium two are all removed, obtaining described channel bottom does not have dielectric layer, and described trenched side-wall remains with the structure that the 3rd layer of medium one and described substrate surface remain with ground floor medium one;
Step 6, at described channel bottom, sidewall and described surface of silicon depositing metal;
Step 7, utilization anti-carves or cmp falls the metal etch on the ground floor medium one of described surface of silicon.
7. as claim 1 or 2 or 4 described methods, it is characterized in that: described metal silicide is titanium silicon or cobalt silicon alloy or niobium-silicon alloy or molybdenum-silicon alloy.
8. as claim 1 or 3 or 4 or 5 or 6 described methods, it is characterized in that: described metal is the combination of tungsten or tungsten silicon or titanium or titanium nitride or aluminium or copper or above-mentioned metal.
9. as claim 1 or 2 or 3 or 5 described methods, it is characterized in that: the impurity of described doped polycrystalline silicon or doping amorphous silicon is P type or N type; The growth temperature of described doped polycrystalline silicon is 600 degree～680 degree; The growth temperature of described doping amorphous silicon is 500 degree～570 degree.
10. as claim 1 or 2 or 3 or 4 or 5 or 6 described methods, it is characterized in that: described medium one is silica, and described medium two is a silicon nitride.
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| CN102412133B (en) * | 2011-11-07 | 2013-10-23 | 上海华虹Nec电子有限公司 | Technological method for forming radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) |
| CN103050424B (en) * | 2012-08-17 | 2016-01-20 | 上海华虹宏力半导体制造有限公司 | The guard ring of semiconductor device |
| CN103779230B (en) * | 2012-10-26 | 2016-10-26 | 上海华虹宏力半导体制造有限公司 | A kind of process of preparing of LDMOS |
| WO2014086479A1 (en) * | 2012-12-03 | 2014-06-12 | Infineon Technologies Ag | Semiconductor device, integrated circuit and method of forming a semiconductor device |
| US9735243B2 (en) | 2013-11-18 | 2017-08-15 | Infineon Technologies Ag | Semiconductor device, integrated circuit and method of forming a semiconductor device |
| US9799762B2 (en) | 2012-12-03 | 2017-10-24 | Infineon Technologies Ag | Semiconductor device and method of manufacturing a semiconductor device |
| CN103904020B (en) * | 2012-12-24 | 2016-08-17 | 上海华虹宏力半导体制造有限公司 | The method optimizing self-aligned contact hole bottom metal silicide pattern |
| CN104425589B (en) * | 2013-08-20 | 2017-08-08 | 上海华虹宏力半导体制造有限公司 | Radio frequency LDMOS device and its manufacture method |
| CN104425588B (en) * | 2013-08-20 | 2017-06-06 | 上海华虹宏力半导体制造有限公司 | RFLDMOS devices and its manufacture method |
| US9306058B2 (en) | 2013-10-02 | 2016-04-05 | Infineon Technologies Ag | Integrated circuit and method of manufacturing an integrated circuit |
| US9287404B2 (en) | 2013-10-02 | 2016-03-15 | Infineon Technologies Austria Ag | Semiconductor device and method of manufacturing a semiconductor device with lateral FET cells and field plates |
| US9401399B2 (en) | 2013-10-15 | 2016-07-26 | Infineon Technologies Ag | Semiconductor device |
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