CN103779230B - A kind of process of preparing of LDMOS - Google Patents
A kind of process of preparing of LDMOS Download PDFInfo
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- CN103779230B CN103779230B CN201210417414.5A CN201210417414A CN103779230B CN 103779230 B CN103779230 B CN 103779230B CN 201210417414 A CN201210417414 A CN 201210417414A CN 103779230 B CN103779230 B CN 103779230B
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- hard mask
- ldmos
- mask layer
- polysilicon
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- 238000000034 method Methods 0.000 title claims abstract description 50
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 32
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical group [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 16
- 239000010937 tungsten Substances 0.000 claims abstract description 16
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 12
- 229920005591 polysilicon Polymers 0.000 claims description 28
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 18
- 229910052710 silicon Inorganic materials 0.000 claims description 18
- 239000010703 silicon Substances 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 17
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 238000001259 photo etching Methods 0.000 claims description 8
- 238000001312 dry etching Methods 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 7
- 229910021332 silicide Inorganic materials 0.000 claims description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 4
- 230000004888 barrier function Effects 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 230000007547 defect Effects 0.000 abstract description 5
- 238000002360 preparation method Methods 0.000 description 6
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1068—Formation and after-treatment of conductors
Abstract
The invention discloses the process of preparing of a kind of LDMOS, by completing after deep plough groove etched and filling step move to device formation again, divide two parts by deep trench inner stuffing simultaneously, DOPOS doped polycrystalline silicon is presented herein below, the above is tungsten.The LDMOS prepared by the method for the present invention can reduce the conducting resistance of device, and Simplified flowsheet controls difficulty, improves product yield, makes manufacturing process be suitable for producing in enormous quantities.Completing additionally due to groove is placed on after transistor is formed by the present invention, subsequent thermal process greatly reduces, it is to avoid the thermal process impact on groove, reduces the formation of defect, the particularly appearance of dislocation, and finally reduces the electric leakage of components and parts.
Description
Technical field
The invention belongs to semiconductor technology method in semiconductor integrated circuit, particularly to a kind of LDMOS(Laterally
Diffused Metal Oxide Semiconductor, LDMOS) process of preparing.
Background technology
LDMOS(Laterally Diffused Metal Oxide Semiconductor, LDMOS)
It is mainly used in switch, conducting resistance and electric leakage are had the highest requirement.The structure of existing LDMOS is as shown in Figure 1.At present
In popular LDMOS preparation process, etching groove and trench fill completed before transistor device is formed, and due to
Manufacturing condition limits, and groove generally utilizes polysilicon to be filled with, and then utilizes metal silicide by polysilicon with adjacent
Transistor source connects.But owing to metal silicide is in the trench top more difficult control of end sidewall forming processes, can break time serious
Split, thus cause transistor conduct resistance to increase, and affect product yield.
Summary of the invention
Present invention solves the technical problem that the process of preparing being to provide a kind of LDMOS, optimize existing production technology, reduction is led
Energising resistance, can reduce technique controlling difficulty simultaneously, improves product yield, makes manufacturing process be suitable for producing in enormous quantities.In addition by
Completing after groove is placed on transistor formation by new technology, subsequent thermal process greatly reduces, it is to avoid the thermal process impact on groove,
Reduce the appearance a kind of staggered arrangement of the line defect in crystal, i.e. atomic arrangement (dislocation be exactly) of the formation of defect, particularly dislocation,
And finally reduce the electric leakage of components and parts.
For solving above-mentioned technical problem, the present invention provides the process of preparing of a kind of LDMOS, mainly comprises following processing step:
Step 1, is initially formed transistor arrangement, specifically includes: first growth one layer and silicon substrate doping type
Identical epitaxial monocrystalline silicon, then utilizes photoetching and ion implantation technology to form the low pressure trap contrary with silicon substrate doping type, with
The doping of silicon substrate same type forms channel region and source electrode, grows gate oxide, polysilicon gate, gate metal silicide the most successively
Thing, and utilize photoetching and dry etching to form grid；
Step 2, in transistor arrangement surface one layer of oxide of deposition that step 1 is formed as hard mask layer, utilizes lithographic definition
Go out region the etch hard mask layer of deep trench；
Step 3, forms deep trench according to hard mask layer as barrier etch；
Step 4, fills in deep trench and the polysilicon of silicon substrate same type doping, and utilizes dry etching to return polysilicon at quarter；
Step 5, in deep trench remainder and on fill tungsten in hard mask layer, and utilize the method for cmp will
The tungsten on hard mask layer surface is removed；
Step 6, finally uses the rear end semiconductor preparing process of standard to form contact hole and metal connects.
Further, in step 1, the formation of described transistor arrangement is to complete before deep trench is formed, and described extension
The thickness of monocrystal silicon is 1-3 micron, and resistivity is 0.2-1.5ohm.cm.
Further, in step 1, described silicon substrate is N-type or p-type；If silicon substrate is N-type, then epitaxial monocrystalline silicon is N
Type, low pressure trap is p-type, and channel region is that n-type doping is formed, and the polysilicon filled in deep trench in step 4 is n-type doping；
If silicon substrate is p-type, then epitaxial monocrystalline silicon is p-type, and low pressure trap is N-type, and channel region is that p-type doping is formed, step 4
The polysilicon filled in middle deep trench is p-type doping.
Further, in step 2, the thickness of described hard mask layer is greater than gate, and the thickness of described hard mask layer is
0.3-0.7 micron；This hard mask layer uses the mode of aumospheric pressure cvd to grow or the growth of other thin film-forming method.
Further, in step 3, the degree of depth of described deep trench is about 1.2-3.2 micron, and width is about 0.5-1.5 micron.
Further, in step 4, filling DOPOS doped polycrystalline silicon in described deep trench, doping content is 1E19-5E20/cm3, profit
Return polysilicon at quarter with dry etching, need to make polysilicon surface be less than source bottom, and make the trap that polysilicon is identical with doping type
District is formed and is fully contacted.
Further, in step 5, described in deep trench remainder and on fill tungsten in hard mask layer, filling temp is
400-450 DEG C, and utilize chemical mechanical milling tech to be removed by the tungsten on hard mask layer surface, but the tungsten filled in hard mask layer
Need not remove.
Compared to the prior art, the method have the advantages that the present invention proposes the process of preparing of a kind of LDMOS,
Can reduce conducting resistance, Simplified flowsheet controls difficulty, improves product yield, makes manufacturing process be suitable for producing in enormous quantities.Meanwhile,
Completing after groove being placed on transistor formation due to present invention process method, subsequent thermal process greatly reduces, it is to avoid thermal process pair
The impact of groove, this technique can reduce the appearance of the formation of defect, particularly dislocation, and finally reduce the electric leakage of components and parts.
Accompanying drawing explanation
Fig. 1 is the structural representation of existing LDMOS device；
Fig. 2-Fig. 6 is the device profile structural representation after each step of the inventive method completes；Wherein, Fig. 2 is the present invention
The step 1 of method complete after device profile structural representation；Fig. 3 is the device profile after the step 2 of the inventive method completes
Structural representation；Fig. 4 is the device profile structural representation after the step 3 of the inventive method completes；Fig. 5 is the inventive method
Step 4 complete after device profile structural representation；Fig. 6 is the device profile structure after the step 5 of the inventive method completes
Schematic diagram.
In figure, description of reference numerals is as follows:
1 is N-type silicon substrate
2 is N-type epitaxial monocrystalline silicon
3 is deep trench
4 is low pressure p-type trap
5 is channel region
6 is gate oxide
7 is polysilicon gate
8 is gate metal silicide
9 is source electrode
10 is hard mask layer
11 is polysilicon
12 is tungsten
Detailed description of the invention
The present invention is further detailed explanation with embodiment below in conjunction with the accompanying drawings.
The preparation technology of embodiment one p-type LDMOS
Below as a example by the preparation technology of p-type LDMOS, it is specifically described preparation technology involved in the present invention.Need explanation a bit,
It is suitable for preparation N-type LDMOS.
1., as in figure 2 it is shown, first form LDMOS transistor structure according to the standard technology that this area is conventional, specifically include as follows
Step: first grow one layer of N-type epitaxial monocrystalline silicon 2 in N-type silicon substrate 1, the thickness of N-type epitaxial monocrystalline silicon 2 is that 1-3 is micro-
Rice, resistivity is about 0.2-1.5ohm.cm, then utilizes the photoetching of this area routine and ion implantation technology to form low pressure p-type
Trap 4, n-type doping forms channel region 5 and source electrode 9, the most successively growth gate oxide 6, polysilicon gate 7, gate metal silicon
Compound 8, and utilize the photoetching of this area routine and dry etch process to form grid.
2. as it is shown on figure 3, deposit one layer of oxide on the ldmos transistor shown in Fig. 2 as hard mask layer 10, hard mask
The thickness of layer 10 is greater than gate, concrete about 0.3-0.7 micron.Hard mask layer 10 can utilize atmospheric chemical vapor
The mode of deposition grows, it is also possible to utilize other thin film-forming method to grow.Photoetching process is utilized to define the region of deep trench and etch
Hard mask layer 10.
The most as shown in Figure 4, forming deep trench 3 according to hard mask layer 10 as barrier etch, the degree of depth of deep trench 3 is about
1.2-3.2 micron, width is about 0.5-1.5 micron.
4., as it is shown in figure 5, fill the polysilicon 11 of n-type doping in deep trench 3, doping content is about 1E19-5E20/cm3,
And utilize dry etching to return polysilicon 11 at quarter, make polysilicon 11 surface be less than bottom source electrode 9, and make polysilicon 11 and N well region
(i.e. channel region 5) is formed and is fully contacted.
The most as shown in Figure 6, in deep trench 3 remainder and on fill tungsten 12 in hard mask layer 10, filling temp is
400-450 DEG C, and utilize the method for cmp to be removed by the tungsten on hard mask layer 10 surface, but fill out in hard mask layer 10
The tungsten filled need not remove.
6. the rear end semiconductor preparing process of the last standard using this area routine forms contact hole and metal connection etc..
In the inventive method, the formation of transistor arrangement is to complete before deep trench is formed, by by deep plough groove etched and filling
Move to be formed again after transistor device is formed, divide two parts by deep trench inner stuffing simultaneously, DOPOS doped polycrystalline silicon is presented herein below, on
Face is tungsten.Processing LDMOS by the new technology of the present invention and can reduce the conducting resistance of device, Simplified flowsheet controls difficulty, carries
High product yield, makes manufacturing process be suitable for producing in enormous quantities.Formed additionally due to groove is placed on transistor by present invention process method
Completing afterwards, subsequent thermal process greatly reduces, it is to avoid the thermal process impact on groove, reduces the formation of defect, particularly dislocation
Appearance, and finally reduce the electric leakage of components and parts.
The preparation technology of embodiment two N-type LDMOS
Embodiment two is with the difference of embodiment one:
In step 1, P-type silicon substrate grows one layer of p-type epitaxial monocrystalline silicon, then utilize the conventional photoetching in this area and from
Sub-injection technology forms low pressure N-type trap, and p-type doping forms channel region and source electrode；
In step 4, in deep trench, fill the polysilicon of p-type doping.
Claims (7)
1. the process of preparing of a LDMOS, it is characterised in that mainly comprise following processing step:
Step 1, is initially formed transistor arrangement, specifically includes: first growth one layer and silicon substrate doping type
Identical epitaxial monocrystalline silicon, then utilizes photoetching and ion implantation technology to form the low pressure trap contrary with silicon substrate doping type, with
The doping of silicon substrate same type forms channel region and source electrode, grows gate oxide, polysilicon gate, gate metal silicide the most successively
Thing, and utilize photoetching and dry etching to form grid；
Step 2, in transistor arrangement surface one layer of oxide of deposition that step 1 is formed as hard mask layer, utilizes lithographic definition
Go out region the etch hard mask layer of deep trench；
Step 3, forms deep trench according to hard mask layer as barrier etch；
Step 4, fills in deep trench and the polysilicon of silicon substrate same type doping, and utilizes dry etching to return polysilicon at quarter,
Make polysilicon surface be less than source bottom, and make polysilicon be fully contacted with channel region formation；
Step 5, in deep trench remainder and on fill tungsten in hard mask layer, and utilize the method for cmp will
The tungsten on hard mask layer surface is removed；
Step 6, finally uses the rear end semiconductor preparing process of standard to form contact hole and metal connects.
The process of preparing of LDMOS the most according to claim 1, it is characterised in that: in step 1, described transistor
The formation of structure is to complete before deep trench is formed, and the thickness of described epitaxial monocrystalline silicon is 1-3 micron, and resistivity is
0.2-1.5ohm.cm。
The process of preparing of LDMOS the most according to claim 1, it is characterised in that: in step 1, described silicon substrate
It is N-type or p-type；If silicon substrate is N-type, then epitaxial monocrystalline silicon is N-type, and low pressure trap is p-type, and channel region is n-type doping
Being formed, the polysilicon filled in deep trench in step 4 is n-type doping；If silicon substrate is p-type, then epitaxial monocrystalline silicon is P
Type, low pressure trap is N-type, and channel region is that p-type doping is formed, and the polysilicon filled in deep trench in step 4 is p-type doping.
The process of preparing of LDMOS the most according to claim 1, it is characterised in that: in step 2, described hard mask
The thickness of layer is greater than gate, and the thickness of described hard mask layer is 0.3-0.7 micron；This hard mask layer uses normal pressure chemical
The mode of vapour deposition grows or the growth of other thin film-forming method.
The process of preparing of LDMOS the most according to claim 1, it is characterised in that: in step 3, described deep trench
The degree of depth be 1.2-3.2 micron, width is 0.5-1.5 micron.
The process of preparing of LDMOS the most according to claim 1, it is characterised in that: in step 4, described deep trench
Interior filling DOPOS doped polycrystalline silicon, doping content is 1E19-5E20/cm3, utilize dry etching to return polysilicon at quarter, need to make polysilicon
Surface is less than source bottom, and the well region formation making polysilicon identical with doping type is fully contacted.
The process of preparing of LDMOS the most according to claim 1, it is characterised in that: in step 5, described at zanjon
Filling tungsten in remainder and upper hard mask layer thereof in groove, filling temp is 400-450 DEG C, and utilizes cmp work
The tungsten on hard mask layer surface is removed by skill, but the tungsten filled in hard mask layer need not remove.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210417414.5A CN103779230B (en) | 2012-10-26 | 2012-10-26 | A kind of process of preparing of LDMOS |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210417414.5A CN103779230B (en) | 2012-10-26 | 2012-10-26 | A kind of process of preparing of LDMOS |
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| Publication Number | Publication Date |
|---|---|
| CN103779230A CN103779230A (en) | 2014-05-07 |
| CN103779230B true CN103779230B (en) | 2016-10-26 |
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Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050280085A1 (en) * | 2004-06-16 | 2005-12-22 | Cree Microwave, Inc. | LDMOS transistor having gate shield and trench source capacitor |
| CN102157493B (en) * | 2010-02-11 | 2013-07-24 | 上海华虹Nec电子有限公司 | Metal plug and manufacturing method thereof |
| CN102237406A (en) * | 2010-04-22 | 2011-11-09 | 上海华虹Nec电子有限公司 | Radio frequency lateral double-diffusion metal oxide semiconductor (LDMOS) device and manufacturing method thereof |
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