CN102456396A - Bit line structure of phase change memory array - Google Patents
Bit line structure of phase change memory array Download PDFInfo
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- CN102456396A CN102456396A CN2010105223258A CN201010522325A CN102456396A CN 102456396 A CN102456396 A CN 102456396A CN 2010105223258 A CN2010105223258 A CN 2010105223258A CN 201010522325 A CN201010522325 A CN 201010522325A CN 102456396 A CN102456396 A CN 102456396A
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Abstract
The invention provides a bit line structure of a phase change memory array. All bit lines in the structure are positioned in different wiring layers. For example, one of two adjacent bit lines is positioned in a first wiring layer, and the other of the two adjacent bit lines is positioned in a second wiring layer; or part of one of the two adjacent bit lines is positioned in the first wiring layer, while the other part of one of the two adjacent bit lines is positioned in the second wiring layer, and part of the other of the two adjacent bit lines is positioned in the second wiring layer, while the other part of the other of the two adjacent bit lines is positioned in the first wiring layer; and the like. Therefore, an interval between the adjacent bit lines can be increased, and interference between the bit lines further can be decreased.
Description
Technical field
The present invention relates to a kind of phase change memory array, particularly a kind of bit line structure of phase change memory array.
Background technology
Phase-changing memory unit is based on that conception that the phase-change thin film that proposes beginning of the seventies late 1960s can be applied to the phase change memory medium sets up, and is the memory device of a kind of low price, stable performance.Phase-changing memory unit can be made on the silicon wafer substrate, and its critical material is recordable phase-change thin film, heating electrode material, thermal insulation material and extraction electrode material, and its research focus also just launches around device technology.The physical mechanism research of device comprises how reducing device material etc.The ultimate principle of phase-changing memory unit is to act on the device cell with electric impulse signal; Make phase-change material between amorphous state and polycrystalline attitude, reversible transition take place, the low-resistance when high resistant during through the resolution amorphous state and polycrystalline attitude realizes writing, wipe and read operation of information.
Phase transition storage owing to have reads at a high speed, high erasable number of times, non-volatile, advantages such as component size is little, strong motion low in energy consumption, anti-and radioresistance, is thought flash memories that most possible replacement is present and becomes following storer main product and become the device of commercial product at first by international semiconductor TIA.
The reading and writing of phase transition storage, wiping operation apply the voltage or the current pulse signal of different in width and height exactly on device cell: wipe operation (RESET); After phase-change material temperature in adding a weak point and strong pulse enable signal device cell is elevated to more than the temperature of fusion; Through thereby cooling realization phase-change material polycrystalline attitude is to amorphous conversion fast, promptly one state is to the conversion of " 0 " attitude again; Write operation (SET); When apply one long and pulse enable signal phase-change material temperature medium tenacity is raised under the temperature of fusion, on the Tc after; And keep a period of time to impel nucleus growth, thus realize the conversion of amorphous state to the polycrystalline attitude, promptly " 0 " attitude is to the conversion of one state; Read operation after adding the very weak pulse signal that a state to phase-change material can not exert an influence, is read its state through the resistance value of measuring element unit.
All bit lines in the existing phase change memory array all are to be in same wiring layer, and are as shown in Figure 1, thus; Along with the raising of phase transition storage density, the spacing between the bit line can be more and more littler, and then the capacity effect between bit line can be more and more obvious; And this capacity effect between bit line can cause the signal on the selected bit line to disturb adjacent bit lines, thereby the signal on the adjacent not selected bit line is overturn; And then generation read-write mistake; So, be necessary under the prerequisite that does not influence storage density, to reduce this capacity effect, improve the performance of storer.
Summary of the invention
The object of the present invention is to provide the bit line structure of the big phase change memory array of a kind of adjacent bit lines spacing.
Reach other purposes in order to achieve the above object, the bit line structure of phase change memory array provided by the invention is characterized in that all bit line branches of phase change memory array are in different wiring layers.
As a kind of optimal way, each bit line all is in same wiring layer, and wherein, the part bit line is in first wiring layer, and the part bit line is in second wiring layer.Preferable, be in the bit line and the adjacent arrangement of bit line that is in second wiring layer of first wiring layer; Preferable; In all bit lines; At least one bit line comprises the first sub-portion and the second sub-portion, and wherein, the said first sub-portion and the second sub-portion be not on same straight line; For example, the said first sub-portion or second sub-portion projection and the adjacent bit lines on the plane that is parallel to this bit line place on this plane to be projected in same straight line first-class.
As another kind of optimal way, part bit line at least in all bit lines, each self-contained at least two sub-portions, and have at least both not to be in same wiring layer at least in two sub-portions.Preferable, each each leisure of sub-portion that is not in same wiring layer is parallel to being projected on the same straight line on this plane, bit line place.
As another optimal way; At least part bit line in all bit lines; Each self-contained at least three sub-portions, wherein, both are not in same wiring layer at least at least three sub-portions; But this at least both each leisures be parallel to being projected on the same straight line on plane, this bit line place, and said each leisure of at least three sub-portions is parallel in the projection on this plane, bit line place and has the part projection overlapping
In sum, in the bit line structure of phase change memory array of the present invention, all bit line branches are in the various wirings layer, so can increase the spacing between bit line, effectively reduce the interference between the bit line.
Description of drawings
Fig. 1 is the bit line structure synoptic diagram of existing phase change memory array.
Fig. 2 is embodiment one synoptic diagram of the bit line structure of phase change memory array of the present invention.
Fig. 3 is embodiment two synoptic diagram of the bit line structure of phase change memory array of the present invention.
Fig. 4 is embodiment three synoptic diagram of the bit line structure of phase change memory array of the present invention.
Fig. 5 is embodiment four synoptic diagram of the bit line structure of phase change memory array of the present invention.
Embodiment
Below will combine accompanying drawing that the bit line structure of phase change memory array of the present invention is described in detail.
Embodiment one:
See also Fig. 2, be simplicity of illustration, phase change memory array in the present embodiment only illustrates 6 bit lines; Be bit line L1 to L6; And bit line L1 to L6 branch is in different wiring layers, promptly divide to be in the first wiring layer Mp and the second wiring layer Mp+1, and same bit line is in same wiring layer.More specifically, bit line L1, L3, L5 are in the first wiring layer Mp, and bit line L2, L4, L6 are in the second wiring layer Mp+1.
As shown in the figure; If the level interval that is in the bit line L1 of the first wiring layer Mp and is between the bit line L2 of wiring layer the 2nd Mp+1 is λ; Layer distance between the first wiring layer Mp and the second wiring layer Mp+1 is d; Then the actual pitch between bit line L1 and the bit line L2 is
obviously; This spacing λ '＞λ this shows, because the adjacent bit lines branch of phase transition storage is in different wiring layers; Can increase the spacing between the adjacent bit lines, the signal that reduces between the adjacent bit lines disturbs.
But, it should be appreciated by those skilled in the art that above-mentioned illustration only just for better explanation technical scheme of the present invention, but not be used to limit the present invention that in fact, the quantity of wiring layer is not to exceed with two-layer, can also be for more than two-layer; Have, the distribution of bit line is not to exceed with above-mentioned instance yet again, for example, can bit line L1 and L2 be in the first wiring layer Mp, bit line L3 and L4 are in the second wiring layer Mp+1, bit line L5 and L6 are in the first wiring layer Mp etc.
Embodiment two:
Seeing also Fig. 3, in the present embodiment, is that example describes with the phase change memory array that 6 bit lines are shown still.
As shown in the figure, each bit line all is in same wiring layer, and promptly bit line L1, L3, L5 are in the first wiring layer Mp, and bit line L2, L4, L6 are in the second wiring layer Mp+1.Wherein, each bit line all comprises the first sub-portion and the second sub-portion separately, and each first sub-portion and the second sub-portion be not on same straight line.
Say it more in detail, bit line L1 comprises the first sub-L11 of portion and the second sub-L12 of portion, and its first sub-L11 of portion and the second sub-L12 of portion be not on same straight line; Bit line L2 comprises the first sub-L21 of portion and the second sub-L22 of portion; Second sub-each leisure of the L12 of portion of its first sub-L21 of portion and bit line L1 is parallel to being projected on the same straight line on the plane at bit line place, and first sub-each leisure of the L11 of portion of its second sub-L22 of portion and bit line L1 is parallel to being projected on the same straight line on the plane that bit line belongs to; Bit line L3 comprises the first sub-L31 of portion and the second sub-L32 of portion, and its first sub-L31 of portion and the second sub-L32 of portion be not on same straight line; Bit line L4 comprises the first sub-L41 of portion and the second sub-L42 of portion; Second sub-each leisure of the L32 of portion of the first sub-L41 of portion of bit line L4 and bit line L3 is parallel to being projected on the same straight line on the plane at bit line place, and the second sub-L42 of portion of bit line L4 and the first sub-L31 of portion of bit line L3 are being parallel to being projected on the same straight line on the plane that bit line belongs to; Bit line L5 comprises the first sub-L51 of portion and the second sub-L52 of portion, and its first sub-L51 of portion and the second sub-L52 of portion be not on same straight line; Bit line L6 comprises the first sub-L61 of portion and the second sub-L62 of portion; The first sub-L61 of portion of bit line L6 and the second sub-L52 of portion of bit line L5 being projected on the same straight line on the plane that is parallel to the bit line place, the second sub-L62 of portion of bit line L6 and the first sub-L51 of portion of bit line L5 being projected on the same straight line on the plane that is parallel to the bit line place.
Visible by figure, bit line L1 and bit line L2 are cross-shaped; Bit line L3 and bit line L4 are cross-shaped; Bit line L5 and bit line L6 are cross-shaped.Yet; Spacing between adjacent bit lines still is
obviously, and this spacing λ '＞λ is also greater than level interval.
Equally, art technology should be appreciated that in this kind mode, the quantity of wiring layer is not to exceed with two-layer yet, can also be for more than two-layer; Have, the interleaved mode of bit line is not to exceed with above-mentioned instance yet again, for example, can also be following various situations:
A) bit line and non-adjacent bit lines are cross-shaped, and for example: bit line L1 and bit line L3 are cross-shaped, bit line L2 and bit line L5 are cross-shaped, and bit line L4 and bit line L6 are cross-shaped or the like.
B) bit line is cross-shaped with other two or more bit line respectively, and for example the part of L1 and bit line L2 are cross-shaped, and another part and bit line L3 are cross-shaped etc.
Embodiment three:
Seeing also Fig. 4, in the present embodiment, is that example describes with the phase change memory array that 6 bit lines are shown still.As shown in the figure, each self-contained at least two sub-portions of bit line, and have at least both not to be in same wiring layer at least in two sub-portions, and each each leisure of sub-portion that is not in same wiring layer is parallel to being projected on the same straight line on this plane, bit line place.
Say it more in detail, bit line L1 comprises first sub-L11 of portion that is in the first wiring layer Mp and the second sub-L12 of portion that is in the second wiring layer Mp+1, wherein, and the first sub-L11 of portion and the second sub-L12 of portion being projected on the same straight line on the plane that is parallel to the bit line place; Bit line L2 comprises first sub-L21 of portion that is in the second wiring layer Mp+1 and the second sub-L22 of portion that is in the first wiring layer Mp, wherein, and the first sub-L21 of portion and the second sub-L22 of portion being projected on the same straight line on the plane that is parallel to the bit line place; Bit line L3 comprises first sub-L31 of portion that is in the first wiring layer Mp and the second sub-L32 of portion that is in the second wiring layer Mp+1, wherein, and the first sub-L31 of portion and the second sub-L32 of portion being projected on the same straight line on the plane that is parallel to the bit line place; Bit line L4 comprises first sub-L41 of portion that is in the second wiring layer Mp+1 and the second sub-L42 of portion that is in the first wiring layer Mp, wherein, and the first sub-L41 of portion and the second sub-L42 of portion being projected on the same straight line on the plane that is parallel to the bit line place; Bit line L5 comprises first sub-L51 of portion that is in the first wiring layer Mp and the second sub-L52 of portion that is in the second wiring layer Mp+1, wherein, and the first sub-L51 of portion and the second sub-L52 of portion being projected on the same straight line on the plane that is parallel to the bit line place; Bit line L6 comprises first sub-L61 of portion that is in the second wiring layer Mp+1 and the second sub-L62 of portion that is in the first wiring layer Mp, wherein, and the first sub-L61 of portion and the second sub-L62 of portion being projected on the same straight line on the plane that is parallel to the bit line place.
This shows; Spacing between adjacent bit lines also is
obviously, and this spacing λ '＞λ is also greater than level interval.
Equally, art technology should be appreciated that in this kind mode, the quantity of wiring layer is not to exceed with two-layer yet, can also be for more than two-layer; Have, the sub-portion that bit line comprised not is with the above-mentioned limit that is depicted as again, and for example, bit line can comprise sub-portion more than 3 or 3, and wherein a part of sub-portion is in first wiring layer, and the sub-portion of another part is in second wiring layer or the like.More intuitively say it, for example, the center section of bit line L1 is in first wiring layer, and the part at two ends is in second wiring layer etc.
Embodiment four:
Seeing also Fig. 5, in the present embodiment, is that example describes with the phase change memory array that 6 bit lines are shown still.As shown in the figure; Each self-contained at least three sub-portions of bit line; Wherein, Both are not in same wiring layer at least at least three sub-portions, but this at least both each leisures be parallel to being projected on the same straight line on plane, this bit line place, and said each leisure of at least three sub-portions is parallel in the projection on this plane, bit line place and has the part projection overlapping.
Say it more in detail; Bit line L1 comprises the first sub-L11 of portion and the second sub-L12 of portion that is in the first wiring layer Mp and the 3rd sub-portion that is in the second wiring layer Mp+1, and (itself and the second sub-L12 of portion are range upon range of; So figure is not shown); Wherein, the first sub-L11 of portion and the second sub-L12 of portion are being parallel to projection on the plane, bit line place not on same straight line, and the second sub-L12 of portion and the 3rd sub-portion are overlapping in the projection that is parallel on the plane, bit line place.Bit line L2 comprises the first sub-L21 of portion and the second sub-L22 of portion that is in the second wiring layer Mp+1 and the 3rd sub-portion that is in the first wiring layer Mp, and (itself and the second sub-L22 of portion are range upon range of; So figure is not shown); Wherein, The first sub-L21 of portion and the second sub-L22 of portion are being parallel to projection on the plane, bit line place not on same straight line, and the second sub-L22 of portion and the 3rd sub-portion are overlapping in the projection that is parallel on the plane, bit line place.Bit line L3 comprises the first sub-L31 of portion and the second sub-L32 of portion that is in the first wiring layer Mp and the 3rd sub-portion that is in the second wiring layer Mp+1, and (itself and the second sub-L32 of portion are range upon range of; So figure is not shown); Wherein, The first sub-L31 of portion and the second sub-L32 of portion are being parallel to projection on the plane, bit line place not on same straight line, and the second sub-L32 of portion and the 3rd sub-portion are overlapping in the projection that is parallel on the plane, bit line place.Bit line L4 comprise the first sub-L41 of portion that is in the second wiring layer Mp+1 and the second sub-L42 of portion; And (itself and the second sub-L42 of portion are range upon range of to be in the 3rd sub-portion of the first wiring layer Mp; So figure is not shown); Wherein, the first sub-L41 of portion and the second sub-L42 of portion are being parallel to projection on the plane, bit line place not on same straight line, and the second sub-L42 of portion and the 3rd sub-portion are overlapping in the projection that is parallel on the plane, bit line place.Bit line L5 comprises the first sub-L51 of portion and the second sub-L52 of portion that is in the first wiring layer Mp and the 3rd sub-portion that is in the second wiring layer Mp+1, and (itself and the second sub-L52 of portion are range upon range of; So figure is not shown); Wherein, The first sub-L51 of portion and the second sub-L52 of portion are being parallel to projection on the plane, bit line place not on same straight line, and the second sub-L52 of portion and the 3rd sub-portion are overlapping in the projection that is parallel on the plane, bit line place.Bit line L6 comprises the first sub-L61 of portion and the second sub-L62 of portion that is in the second wiring layer Mp+1 and the 3rd sub-portion that is in the first wiring layer Mp, and (itself and the second sub-L62 of portion are range upon range of; So figure is not shown); Wherein, The first sub-L61 of portion and the second sub-L62 of portion are being parallel to projection on the plane, bit line place not on same straight line, and the second sub-L62 of portion and the 3rd sub-portion are overlapping in the projection that is parallel on the plane, bit line place.
Visible by figure, bit line L1 and bit line L2 are cross-shaped; Bit line L3 and bit line L4 are cross-shaped; Bit line L5 and bit line L6 are cross-shaped.Yet; Spacing between adjacent bit lines still is
obviously, and this spacing λ '＞λ is also greater than level interval.
Equally, art technology should be appreciated that in this kind mode, the quantity of wiring layer is not to exceed with two-layer yet, can also be for more than two-layer; Have, the interleaved mode of bit line is not to exceed with above-mentioned instance yet again, for example, can also be following various situations:
A) bit line and non-adjacent bit lines are cross-shaped, and for example: bit line L1 and bit line L3 are cross-shaped, bit line L2 and bit line L5 are cross-shaped, and bit line L4 and bit line L6 are cross-shaped or the like.
B) bit line is cross-shaped with other two or more bit line respectively, and for example the part of L1 and bit line L2 are cross-shaped, and another part and bit line L3 are cross-shaped etc.
In addition; It should be appreciated by those skilled in the art that the bit line structure shown in above-mentioned each embodiment can be combined to form unitized construction, for example; With making up more than both or both arbitrarily among embodiment one, embodiment two, embodiment three and the embodiment four, detail no longer one by one at this.
In sum; The bit line structure of phase change memory array of the present invention adopts multiple wiring layer; With respect to the existing bit line structure that adopts single wiring layer, under the identical situation of phase-change memory cell distribution density, the spacing between bit line of the present invention is greater than the spacing between existing bit line; Therefore, can effectively reduce crosstalking between bit line.
The foregoing description is just listed expressivity principle of the present invention and effect is described, but not is used to limit the present invention.Any personnel that are familiar with this technology all can make amendment to the foregoing description under spirit of the present invention and scope.Therefore, rights protection scope of the present invention should be listed like claims.
Claims (8)
1. the bit line structure of a phase change memory array is characterized in that:
All bit line branches of phase change memory array are in different wiring layers.
2. the bit line structure of phase change memory array as claimed in claim 1, it is characterized in that: each bit line all is in same wiring layer, and wherein, the part bit line is in first wiring layer, and the part bit line is in second wiring layer.
3. the bit line structure of phase change memory array as claimed in claim 2 is characterized in that: the bit line and the adjacent arrangement of bit line that is in second wiring layer that are in first wiring layer.
4. the bit line structure of phase change memory array as claimed in claim 2, it is characterized in that: in all bit lines, at least one bit line comprises the first sub-portion and the second sub-portion, and wherein, the said first sub-portion and the second sub-portion be not on same straight line.
5. the bit line structure of phase change memory array as claimed in claim 4 is characterized in that: the said first sub-portion or second sub-portion projection and the adjacent bit lines on the plane that is parallel to this bit line place is being projected on the same straight line on this plane.
6. the bit line structure of phase change memory array as claimed in claim 1 is characterized in that: part bit line at least in all bit lines, and each self-contained at least two sub-portions, and have at least both not to be in same wiring layer at least in two sub-portions.
7. the bit line structure of phase change memory array as claimed in claim 6 is characterized in that: each each leisure of sub-portion that is not in same wiring layer is parallel to being projected on the same straight line on this plane, bit line place.
8. the bit line structure of phase change memory array as claimed in claim 1; It is characterized in that: part bit line at least in all bit lines; Each self-contained at least three sub-portions, wherein, both are not in same wiring layer at least at least three sub-portions; But this at least both each leisures be parallel to being projected on the same straight line on plane, this bit line place, and said each leisure of at least three sub-portions is parallel in the projection on this plane, bit line place and has the part projection overlapping.
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| CN2010105223258A CN102456396A (en) | 2010-10-26 | 2010-10-26 | Bit line structure of phase change memory array |
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| CN2010105223258A CN102456396A (en) | 2010-10-26 | 2010-10-26 | Bit line structure of phase change memory array |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1572002A (en) * | 2000-10-17 | 2005-01-26 | 英特尔公司 | Noise suppression for open bit line DRAM architectures |
| CN1759482A (en) * | 2003-04-03 | 2006-04-12 | 株式会社东芝 | Phase change memory device |
| CN101055871A (en) * | 2006-04-13 | 2007-10-17 | 尔必达存储器股份有限公司 | Semiconductor storage device |
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- 2010-10-26 CN CN2010105223258A patent/CN102456396A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1572002A (en) * | 2000-10-17 | 2005-01-26 | 英特尔公司 | Noise suppression for open bit line DRAM architectures |
| CN1759482A (en) * | 2003-04-03 | 2006-04-12 | 株式会社东芝 | Phase change memory device |
| CN101055871A (en) * | 2006-04-13 | 2007-10-17 | 尔必达存储器股份有限公司 | Semiconductor storage device |
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Application publication date: 20120516 |