CN102064276B - Asymmetric phase-change memory unit and element - Google Patents
Asymmetric phase-change memory unit and element Download PDFInfo
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- CN102064276B CN102064276B CN201010528582.2A CN201010528582A CN102064276B CN 102064276 B CN102064276 B CN 102064276B CN 201010528582 A CN201010528582 A CN 201010528582A CN 102064276 B CN102064276 B CN 102064276B
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Abstract
The invention belongs to an asymmetric phase-change memory unit and an element. The asymmetric phase-change memory unit comprises a lower electrode layer, a first insulation layer, a phase change layer, a second insulation layer and an upper electrode layer, which are overlapped from top down, wherein the first insulation layer has a small hole which is 10 nanometers to 4 micrometers wide; the phase change layer is contacted with the lower electrode layer through the small hole in the first insulation layer; the second insulation layer also has a small hole which is 10 nanometers to 5 micrometers wide; and an upper electrode is contacted with the phase change layer through the small hole in the second insulation layer. The core structural characteristic of the asymmetric phase-change memory unit lies in that any two of the axis of the small hole in the first insulation layer, the axis of the small hole in the second insulation layer and the axis of the lower electrode layer are not coincide. When the asymmetric phase-change memory unit and the element, which are provided by the invention, are used, a memory has a higher thermal property, and consequently, power consumption can be reduced while the original properties of the element are kept.
Description
Technical field
The invention belongs to phase change memory technology, particularly relate to a kind of asymmetric phase-change memory unit and device.
Background technology
Phase transition storage technology is to grow up in the quick reversible transition of the chalcogenide compound of late 1960s discovery based on Ovshinsky.Phase transition storage is due to the significant advantage at reading and writing data speed, erasable number of times, device power consumption, component size and the aspect such as non-volatile, thought most possibly to replace current flash memories and become following memory main product and become at first the device of commercial product by international semiconductor TIA.
The operation principle of phase transition storage is to utilize electric pulse to act on device cell, makes phase-change material, between amorphous state and polycrystal, reversible transition occur, and realizes writing, wipe and read operation of information by differentiating the low-resistance of amorphous high resistant and crystalline state.For example, ablation process (reset): if apply a short and strong potential pulse, electric energy is transformed into heat energy, make more than chalcogenide compound temperature is elevated to fusion temperature, through cooling (being about several nanoseconds) fast, can make the long-range order of crystalline state be destroyed, and this state is remained, thereby realization is by crystalline state to amorphous conversion, and so far the resistance of chalcogenide compound increases, and enters high-impedance state; Erase process (set): if apply a potential pulse long and intensity is medium, more than the temperature of chalcogenide compound is elevated to crystallization temperature, below fusion temperature, and keep the regular hour, make chalcogenide compound be converted into crystalline state by amorphous state, enter low resistive state; Data read process: reading of data is to realize by measuring the resistance value of chalcogenide compound, the intensity that now adds pulse voltage is very weak, the heat energy producing can only make the temperature of chalcogenide compound be elevated to below crystallization temperature, does not cause that material undergoes phase transition.
Traditional T-shaped symmetrical phase-change memory unit element core texture as shown in Figure 1, mainly comprise: lower electrode layer 5, the first insulating barrier 4, phase change layer 3, the second insulating barrier 2 and upper electrode layer 1, its design feature be the central axis of aperture in the first insulating barrier 4 and the second insulating barrier 2 overlap and with the central axes of whole cellular construction.In the time that described T-shaped symmetrical phase transformation memory device unit is passed to reset pulse, the phase-change material on lower electrode layer 5 can undergo phase transition, and is changed to amorphous state by crystalline state.In the time that described T-shaped symmetrical phase-change memory unit element is passed to set pulse subsequently, the phase-change material on lower electrode layer 5 will change to crystalline state from amorphous state.These variations cause that the resistance value of described T-shaped symmetrical phase-change memory unit element changes, and can realize the storage of information thus.
But in the above-mentioned course of work, only account for the about 15% of total amount of heat for the heat reality of phase-change material generation reversible transition, this means in the heat that pulse current provides that 85% has all been dissipated.The reduction that this has seriously hindered phase-change memory unit element power consumption on the one hand, also affects the integrated of high-density device cell array simultaneously because unit component caloric value is excessive.Therefore, how to design phase-change memory unit element structure that a kind of heat utilization ratio is high to reduce the power consumption of device, become those skilled in the art's problem demanding prompt solution.For now, the method for reduction device power consumption generally has: the contact area that reduces electrode and phase-change material; Improve the resistance of phase-change material; Between electrode and phase-change material or the inner hot merit ergosphere etc. that adds of phase-change material.And the innovative point of this invention is from device architecture to start with, by the improvement of T-shaped symmetrical phase-change memory unit element structure being improved to the heating efficiency of device.
Summary of the invention
The object of the invention is to provide a kind of asymmetric phase-change memory unit and device, and the storage component part being made up of this memory cell has good thermal property, and then can in the original performance of retainer member, reduce power consumption.
A kind of asymmetric phase-change memory unit provided by the invention, is characterized in that: its film layer structure comprises:
The lower electrode layer of electric conducting material;
In first insulating barrier on described lower electrode layer surface, the first insulating barrier has aperture;
In the phase change layer of described the first surface of insulating layer;
In second insulating barrier on described phase change layer surface, the second insulating barrier has aperture;
In described the second surface of insulating layer and be the upper electrode layer of electric conducting material;
The section axis a3 of the section axis a1 of the first insulating barrier aperture, the section axis a2 of the second insulating barrier aperture and lower electrode layer, any two of these three section axis overlap when different.
The memory device that described asymmetric phase-change memory cell forms, is characterized in that: this memory device is made up of the multiple asymmetric phase-change memory cell that becomes array distribution, its total memory capacity is greater than 210.
Asymmetric phase-change memory unit of the present invention and device can be under identical electric current, potential pulses for traditional T-shaped symmetrical phase-changing memory unit and device, reach higher maximum temperature values, and lower surface temperature value, and then improve the thermal property of memory cell device, and effectively reduce device power consumption.
Brief description of the drawings
Fig. 1 is the T-shaped symmetrical phase-changing memory unit of tradition longitudinal cross-section axially symmetric structure schematic diagram.
Fig. 2 is the asymmetric phase-change memory unit longitudinal cross-section structural representation that the present invention proposes.
Fig. 3 is the eight asymmetric phase-change memory device schematic diagrames in unit of preparing in instantiation 1.
Fig. 4 is the asymmetric phase-change memory unit longitudinal cross-section structural representation of preparing in instantiation 1.
Fig. 5 is the asymmetric phase-change memory unit longitudinal cross-section structural representation of preparing in instantiation 2.
Fig. 6 is the asymmetric phase-change memory unit longitudinal cross-section structural representation of preparing in instantiation 3.
Fig. 7 is the asymmetric phase-change memory unit longitudinal cross-section structural representation of preparing in instantiation 4.
Fig. 8 is the I-V curve that the asymmetric phase-change memory unit prepared in instantiation obtains under the effect of 0-50uA direct current sweep current.
Embodiment
Below in conjunction with accompanying drawing and example, the structure of invention is described in further detail.
As shown in Figure 2, asymmetric phase-change memory unit provided by the invention comprises from the bottom to top stacked successively lower electrode layer 5, the first insulating barrier 4, phase change layer 3, the second insulating barrier 2 and upper electrode layer 1.
Described lower electrode layer 5 can adopt the electric conducting materials such as TiW, W, TiN, Ta, Pt, Ag, Cu or CuN, and its width L7 scope is 60nm～40um, and thickness h 6 scopes are 2nm～500nm.
Described the first insulating barrier 4 is in described lower electrode layer 5 surfaces, and the first insulating barrier 4 can adopt SiO2, ZrO2, TiO2, Y2O3, Hf2O, Ta2O5, amorphous Si, or the material such as C.The first insulating barrier 4 width L8 scopes are 60nm～40um, and thickness h 7 scopes are 2nm～500nm.The first insulating barrier 4 has aperture, and aperture width L11 is 10nm～4um.
Described phase change layer 3 is in the first insulating barrier 4 surfaces, and phase change layer 3 can adopt the combination of IVA in the periodic table of elements, VA and VIA family element.Phase change layer 3 width L9 scopes are 60nm～40um, and thickness h 8 scopes are 2nm～500nm, and phase change layer 3 contacts with lower electrode layer 5 by the aperture on the first insulating barrier 4.
Described the second insulating barrier 2 is in described phase change layer 3 surfaces, and the second insulating barrier can adopt SiO2, ZrO2, TiO2, Y2O3, Hf2O, Ta2O5, amorphous Si, or the material such as C.The second insulating barrier 2 width L10 scopes are 60nm～40um, and thickness h 9 scopes are 2nm～500nm.The second insulating barrier 2 has aperture, and aperture width L12 scope is 10nm～5um.
Described upper electrode layer 1 is in described the second insulating barrier 2 surfaces, and top electrode 1 contacts with phase change layer 3 by the aperture on the second insulating barrier 2.Top electrode 1 can adopt the electric conducting materials such as TiW, W, TiN, Ta, Pt, Ag, Cu or CuN.Its width L7 scope is 60nm～40um, and thickness h 10 scopes are 2nm～500nm.
The present invention does not have special requirement to the particular location of aperture on upper and lower insulating barrier, as long as ensure that any two of axis a3 on axis a2 and the lower electrode layer 5 of aperture on the axis a1, the second insulating barrier 2 of aperture on the first insulating barrier 4 does not overlap mutually.
The width that it should be noted that the width of described lower electrode layer, the first insulating barrier, phase change layer, the second insulating barrier, upper electrode layer and thickness and the first insulating barrier aperture, the second insulating barrier aperture can carry out equal proportion convergent-divergent according to actual needs.
Below provide a kind of method of using asymmetric phase-change memory unit to prepare phase transition storage:
First, (comprise the impurity diffusion zone of MOS at SiO2 substrate or Semiconductor substrate, drain-source district, contact conductor, through hole, or PN diode, bipolar transistor etc.) prepare the lower electrode layer 5 conducting electricity, described lower electrode layer 5 can adopt the electric conducting materials such as TiW, W, TiN, Ta, Pt, Ag, Cu or CuN.
Then, prepare the first insulating barrier 4 on the surface of established lower electrode layer 5, described the first insulating barrier 4 can adopt SiO2, ZrO2, TiO2, Y2O3, Hf2O, Ta2O5, amorphous Si, or the material such as C.
Then,, at the surface sputtering sediment phase change layer 3 of established the first insulating barrier 4, described phase change layer 3 can adopt the combination of IVA in the periodic table of elements, VA and VIA family element.
Then, prepare the second insulating barrier 2 on the surface of established phase change layer 3, described the second insulating barrier 2 can adopt SiO2, ZrO2, TiO2, Y2O3, Hf2O, Ta2O5, amorphous Si, or the material such as C.
Finally, at the upper electrode layer 1 of the surface sputtering depositing electrically conductive of established the second insulating barrier 2, described upper electrode layer 1 can adopt the electric conducting materials such as TiW, W, TiN, Ta, Pt, Ag, Cu or CuN.
Embodiment 1:
In the present embodiment, the eight asymmetric phase-change memory devices in unit of manufacturing as shown in Figure 3: a, b, c, d, e, f, g, h represent respectively eight unit, and TE represents top electrode, and BE represents bottom electrode.Each unit all can be realized and the function such as write, reads and wipe.This asymmetric phase-change memory device unit construction is as shown in Figure 4: described lower electrode layer 5 adopts TiW, its width L7=12um, thickness h 6=150nm.
What the first insulating barrier 4 adopted is SiO2 material, its width L8=20um, thickness h 7=200um.The first insulating barrier 4 has aperture, and width is L11=2um, and the axis a1 of this aperture is with respect to the axis a3 horizontal left d1=1.5um on bottom electrode 5.
The material that phase change layer 3 adopts is Ge2Sb2Te5, its width L9=10um, thickness h 8=150nm.
What the second insulating barrier 2 adopted is SiO2 material, its width L10=30um, thickness h 9=200nm.The second insulating barrier 2 has aperture, width L12=4um, and the axis a2 of this aperture is with respect to the axis a3 horizontal left d2=2um on bottom electrode 5.
In the time having the phase-changing memory unit of above-mentioned asymmetry structure and passed to 0 to 50uA direct current sweep current, its I-V curve as shown in Figure 8.Above-mentioned curve shows, described asymmetric phase-change memory unit can encourage and undergo phase transition by response current, and this asymmetric phase-change memory unit meets the characteristic performance requirement of phase transition storage.Be that 7v, rising time are that 10ns, pulsewidth are that the reset pulse that is 10ns of 50ns, trailing edge time and amplitude are that 6v, rising time are that 10ns, pulsewidth are the set pulse that is 100ns of 200ns, trailing edge time when described asymmetric phase-change memory unit is applied in amplitude, also can there is reversible transition in the resistance value of device cell accordingly between high-impedance state and low resistance state.Be embodied in: when passing to after above-mentioned reset effect pulse, device cell resistance value becomes the 100K Ω of high-impedance state, and the phase-change material on corresponding lower electrode layer 5 is in amorphous state; When passing to after above-mentioned set effect pulse, device cell resistance value becomes the 7K Ω of low resistance state, and the phase-change material on corresponding lower electrode layer 5 is in crystalline state.
Embodiment 2:
In the present embodiment, manufacturing be the eight asymmetric phase transition storages in unit, its asymmetric phase-change memory unit structure as shown in Figure 5: described lower electrode layer 5 adopts Cu, its width L7=10um, thickness h 6=100nm.
What the first insulating barrier 4 adopted is TiO2 material, its width L8=15um, thickness h 7=150um.The first insulating barrier 4 has aperture, and width is L11=1um, and the axis a1 of this aperture is with respect to the d1=1.5um that moves to right of the axis a3 level on bottom electrode 5.
The material that phase change layer 3 adopts is Ge1Sb4Te7, its width L9=10um, thickness h 8=100nm.
What the second insulating barrier 2 adopted is TiO2 material, its width L10=20um, thickness h 9=150nm.The second insulating barrier 2 has aperture, width L12=2um, and the axis a2 of this aperture is with respect to the axis a3 horizontal left d2=1um on bottom electrode 5.
Embodiment 3:
In the present embodiment, the asymmetric phase-change memory device of manufacturing, its asymmetric phase-change memory unit structure as shown in Figure 6: described lower electrode layer 5 adopts Ag, its width L7=30um, thickness h 6=500nm.
What the first insulating barrier 4 adopted is amorphous Si material, its width L8=40um, thickness h 7=500um.The first insulating barrier 4 has aperture, and width is L11=4um, and the axis a1 of this aperture is with respect to the d1=4um that moves to right of the axis a3 level on bottom electrode 5.
The material that phase change layer 3 adopts is GeTe.Its width L9=30um, thickness h 8=500nm.
What the second insulating barrier 2 adopted is amorphous Si material, its width L10=40um, thickness h 9=500nm.The second insulating barrier 2 has aperture, width L12=6um, and the axis a2 of this aperture is with respect to the axis a3 horizontal left d2=6um on bottom electrode 5.
Embodiment 4:
In the present embodiment, the asymmetric phase-change memory device of manufacturing, its asymmetric phase-change memory unit structure as shown in Figure 7: described lower electrode layer 5 adopts TiN, its width L7=60nm, thickness h 6=2nm.
What the first insulating barrier 4 adopted is ZrO2 material, its width L8=90nm, thickness h 7=2nm.The first insulating barrier 4 has aperture, and width is L11=10nm, and the axis a1 of this aperture is with respect to the axis a3 horizontal left d1=10nm on bottom electrode 5.
The material that phase change layer 3 adopts is AgInSbTe.Its width L9=60nm, thickness h 8=2nm.
What the second insulating barrier 2 adopted is ZrO2 material, its width L10=90nm, thickness h 9=2nm.The second insulating barrier 2 has aperture, width L12=10nm, and the axis a2 of this aperture is with respect to the d2=10nm that moves to right of the axis a3 level on bottom electrode 5.
It should be noted that, the size of each layer of structure in above embodiment is only example, not for limiting the present invention, these those of skill in the art can be adjusted according to actual conditions, for example, can design needs according to side circuit, the design size of this unit component is carried out to convergent-divergent, also can between bottom electrode 5 and the first insulating barrier 4, add hot merit ergosphere, contact layer etc., can also between upper electrode layer 1 and the second insulating barrier 2, add the situation of hot merit ergosphere, contact layer etc.
Only exemplary explanation principle of the present invention and basic structure of above-described embodiment, not for limiting the present invention.Any person skilled in the art person all can without departing from the spirit and scope of the present invention, modify to above-described embodiment.Therefore, the scope of the present invention, should be as listed in claims.
Claims (5)
1. an asymmetric phase-change memory unit, is characterized in that: its film layer structure comprises:
The lower electrode layer of electric conducting material;
In first insulating barrier on described lower electrode layer surface, the first insulating barrier has aperture;
In the phase change layer of described the first surface of insulating layer;
In second insulating barrier on described phase change layer surface, the second insulating barrier has aperture;
In described the second surface of insulating layer and be the upper electrode layer of electric conducting material;
The section axis a3 of the section axis a1 of the first insulating barrier aperture, the section axis a2 of the second insulating barrier aperture and lower electrode layer, any two of these three section axis do not overlap mutually; Phase change layer contacts with lower electrode layer by the aperture on the first insulating barrier; Upper electrode layer contacts with phase change layer by the aperture on the second insulating barrier; Make described asymmetric phase-change memory unit be issued to higher maximum temperature values at identical power supply, potential pulse, and lower surface temperature value;
The width of the thickness of described lower electrode layer, the first insulating barrier, phase change layer, the second insulating barrier and upper electrode layer and width and the first insulating barrier aperture and the second insulating barrier aperture equal proportion convergent-divergent according to actual needs;
The thickness of described lower electrode layer, the first insulating barrier, phase change layer, the second insulating barrier and upper electrode layer is all within the scope of 2nm～500nm; The first insulating barrier has aperture, and aperture width is 10nm～4um, and the second insulating barrier also has aperture, and aperture width is 10nm～5um; Between bottom electrode and the first insulating barrier, add hot merit ergosphere and/or contact layer; Between upper electrode layer and the second insulating barrier, add hot merit ergosphere and/or contact layer.
2. asymmetric phase-change memory unit as claimed in claim 1, is characterized in that: the material of described phase change layer is the combination of IVA, VA and VIA family element in the periodic table of elements.
3. asymmetric phase-change memory unit as claimed in claim 1 or 2, is characterized in that: the material of described the first insulating barrier and the second insulating barrier is SiO2, ZrO2, TiO2, Y2O3, Hf2O, Ta2O5, amorphous Si, or one in C.
4. asymmetric phase-change memory unit as claimed in claim 1, is characterized in that: the material of described lower electrode layer and upper electrode layer is the one of TiW, W, TiN, Ta, Pt, Ag, Cu or CuN.
5. the memory device being made up of asymmetric phase-change memory cell claimed in claim 1, is characterized in that: this memory device is made up of the multiple asymmetric phase-change memory cell that becomes array distribution, and its total memory capacity is greater than 2
10.
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| CN102447061B (en) * | 2011-12-12 | 2014-08-27 | 华中科技大学 | Preparation method of high-speed low-power-consumption phase change memory |
| CN103050623B (en) * | 2012-12-25 | 2015-01-28 | 华中科技大学 | Second-order memristor with multi-resistance state characteristic and modulation method thereof |
| WO2015196412A1 (en) * | 2014-06-26 | 2015-12-30 | 华为技术有限公司 | Metal doped ge-sb-te-based multivalue storage phase-change material and phase-change memory |
| CN107017341B (en) * | 2017-03-28 | 2020-09-25 | 华中科技大学 | Asymmetric annular microelectrode phase change memory unit and device |
| CN110767801B (en) * | 2019-09-24 | 2021-09-14 | 华中科技大学 | Processing method of vertical electrode configuration structure of nanoscale phase change memory unit |
| CN110635030B (en) * | 2019-09-24 | 2021-10-01 | 华中科技大学 | Vertical electrode configuration structure for nanoscale phase-change memory cells |
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| EP1484799A2 (en) * | 2003-06-03 | 2004-12-08 | Samsung Electronics Co., Ltd. | Nonvolatile memory device comprising a switching device and a resistant material and method of manufacturing the same |
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