CN110767801B - Processing method of vertical electrode configuration structure of nanoscale phase change memory unit - Google Patents
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- 230000008859 change Effects 0.000 title claims abstract description 19
- 238000003672 processing method Methods 0.000 title abstract description 7
- 239000007772 electrode material Substances 0.000 claims abstract description 119
- 239000012782 phase change material Substances 0.000 claims abstract description 86
- 238000000034 method Methods 0.000 claims abstract description 56
- 230000008569 process Effects 0.000 claims abstract description 49
- 229920002120 photoresistant polymer Polymers 0.000 claims description 35
- 238000001259 photo etching Methods 0.000 claims description 25
- 239000002184 metal Substances 0.000 claims description 21
- 229910052751 metal Inorganic materials 0.000 claims description 21
- 238000004519 manufacturing process Methods 0.000 claims description 15
- 238000000151 deposition Methods 0.000 claims description 11
- 150000004770 chalcogenides Chemical class 0.000 claims description 6
- 238000002360 preparation method Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 4
- 229910005936 Ge—Sb Inorganic materials 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- -1 chalcogenide compounds Chemical class 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 239000013078 crystal Substances 0.000 abstract description 7
- 230000005641 tunneling Effects 0.000 abstract description 5
- 238000009792 diffusion process Methods 0.000 abstract description 4
- 230000002035 prolonged effect Effects 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 173
- 238000000206 photolithography Methods 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052681 coesite Inorganic materials 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 238000002425 crystallisation Methods 0.000 description 3
- 230000008025 crystallization Effects 0.000 description 3
- 229910052697 platinum Inorganic materials 0.000 description 3
- 239000011241 protective layer Substances 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- 238000005280 amorphization Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 241001391944 Commicarpus scandens Species 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000002346 layers by function Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
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Abstract
The invention discloses a processing method of a vertical electrode configuration structure for a nanoscale phase change memory unit, which comprises the following steps of growing a lower electrode material layer, a middle phase change material layer and an upper electrode material layer in sequence according to procedures; when the electrode is processed, the upper electrode material layer and the lower electrode material layer are processed into a partially overlapped upper electrode structure and a partially overlapped lower electrode structure, and source-drain end exchange can be carried out. For the low-resistance crystalline state, by constructing an asymmetric upper electrode structure and an asymmetric lower electrode structure, compared with a structure which is opposite to a vertical electrode, the equivalent resistance R is increased, the working current is reduced, the tunneling of large current is avoided, and the service life of the device is prolonged. Meanwhile, the non-right opposite surface integral quantity shunts the current of a series passage, the current diffusion in the series connection process is increased, the working current is reduced, and the smaller the working current is, the more difficultly the metastable crystal phase structure is broken down.
Description
Technical Field
The invention belongs to the field of microelectronics, relates to a processing method of a vertical electrode configuration structure for a nano-scale phase change memory unit, and particularly relates to a design and processing method of a phase change memory element taking a chalcogenide phase change material as a substrate and application thereof.
Background
The phase change memory using the chalcogenide phase change material as the substrate stores information data through huge resistance difference between a crystalline phase and an amorphous phase, and even can realize multi-stage phase change storage. Such a phase change process has a cost advantage of low power consumption and high density as the size is reduced, and thus, the development of a nanoscale phase change memory is of great interest in the industry.
At present, a T-shaped structure, a side wall contact structure and the like are more mature in the structural design of a phase change unit, and the purpose is to reduce the current in the non-crystallization process so as to reduce the power consumption. The structure treats a phase change memory cell as a constant two-terminal element, increases the current density in the amorphization process by limiting the cross-sectional area of one terminal, and reduces the current in the amorphization process, thereby reducing power consumption.
In fact, in the process of continuously shrinking the phase change unit, the nanometer effect of the phase change material gradually becomes non-negligible. Particularly, the resistance of the crystal phase is very small when the dimension of the crystal phase is less than 10nm, and the crystal phase is easy to tunnel through and shows the characteristic of a short circuit.
Therefore, it is necessary to provide a method for processing a novel electrode configuration structure suitable for a nanoscale phase change unit to solve the problem of tunneling short circuit in the crystallization process of low resistance at a nanoscale level.
Disclosure of Invention
Aiming at least one of the defects or the improvement requirements in the prior art, particularly, how to avoid tunneling short circuit in the low-resistance crystallization process under the condition that the nano effect is prominent due to the fact that the phase change unit is reduced to a nano level, the invention provides a processing method of a vertical electrode configuration structure for a nano-scale phase change memory unit. Meanwhile, the non-right opposite surface integral quantity shunts the current of a series passage, the current diffusion in the series connection process is increased, the working current is reduced, and the smaller the working current is, the more difficultly the metastable crystal phase structure is broken down.
To achieve the above object, according to one aspect of the present invention, there is provided a method for manufacturing a vertical electrode configuration structure for a nanoscale phase-change memory cell, wherein the vertical electrode configuration structure comprises an upper electrode material layer, a middle phase-change material layer, and a lower electrode material layer, and the method for manufacturing and using the vertical electrode configuration structure comprises the following steps:
s1, firstly, forming a photoresist mask pattern of a lower electrode material layer and a calibration pattern for aligning the intermediate phase change material layer and the upper electrode material layer on the silicon substrate through a first photoetching exposure process;
s2, growing a lower electrode material layer, removing the photoresist in the first photoetching exposure process through a photoresist removing process, and depositing an insulating dielectric protective layer to fill a side gap formed after photoetching of the lower electrode material layer;
s3, before the preparation of the intermediate phase-change material layer is started, utilizing the calibration graph in the step S1 and using the second photoetching exposure process to form a photoresist mask graph of the intermediate phase-change material layer on the upper surface of the lower electrode material layer;
s4, growing an intermediate phase change material layer on the lower electrode material layer and the insulating medium protection layer, and removing the photoresist of the second photoetching exposure process through a photoresist removing process;
s5, before preparing the upper electrode material layer, forming a photoresist mask pattern of the upper electrode material layer on the upper surface of the intermediate phase change material layer by using the third photoetching exposure process by using the calibration pattern in the step S1;
s6, growing an upper electrode material layer in a mode of forming an asymmetric upper and lower electrode structure with a lower electrode material layer, wherein the upper and lower electrode structure has positive and opposite integral quantities with overlapped horizontal projection areas and non-positive and opposite integral quantities with non-overlapped projection areas, all the positive and opposite integral quantities are correspondingly provided with the intermediate phase-change material layer, and part or all the non-positive and opposite integral quantities are correspondingly provided with the intermediate phase-change material layer; removing the photoresist in the third photoetching exposure process through a photoetching photoresist removing process; the upper electrode material layer and the lower electrode material layer can be exchanged at the source and drain ends.
Preferably, the growth of any one of the lower electrode material layer, the intermediate phase change material layer and the upper electrode material layer in the steps S2, S4 and S6 is performed by magnetron sputtering.
Preferably, in any one of the photoresist removing processes in steps S2, S4 and S6, a stripping or etching method is adopted.
Preferably, if the lower electrode material layer is an inert electrode matched with the intermediate phase-change material, the intermediate phase-change material layer is directly deposited on the lower electrode material layer and the insulating medium protective layer;
and/or the presence of a gas in the gas,
if the upper electrode material layer adopts an inert electrode matched with the intermediate phase-change material, the deposition of the upper electrode material layer is directly carried out on the intermediate phase-change material layer.
Preferably, if the lower electrode material layer is an active electrode, a metal adhesion layer or an electrode matching layer is grown on the electrode contact surface between the lower electrode material layer and the intermediate phase-change material layer; forming a photoresist mask pattern of the intermediate phase-change material layer on the upper surface of the metal adhesion layer or the electrode matching layer by using the calibration pattern in the step S1 and a second photoetching exposure process, and depositing the intermediate phase-change material layer on the metal adhesion layer or the electrode matching layer;
and/or the presence of a gas in the gas,
if the upper electrode material layer is an active electrode, a metal adhesion layer or an electrode matching layer is grown on the electrode contact surface between the intermediate phase change material layer and the upper electrode material layer, a photoresist mask pattern of the upper electrode material layer is formed on the upper surface of the metal adhesion layer or the electrode matching layer by using the scaling pattern in the step S1 and a third photoetching exposure process, and then the upper electrode material layer is deposited on the metal adhesion layer or the electrode matching layer.
Preferably, between step S4 and step S5, there is also the step of:
an insulating dielectric protection layer is required between the intermediate phase change material layers of different phase change memory cells to isolate the phase change material layers of the cells.
Preferably, the upper electrode material layer and the lower electrode material layer are made of different electrode materials respectively.
Preferably, the intermediate phase-change material layer is made of chalcogenide compound or non-chalcogenide Ge-Sb series phase-change material.
Preferably, after step S6, growing an insulating dielectric protection layer on the upper electrode material layer;
alternatively, after step S6, an insulating dielectric protection layer need not be grown over the upper electrode material layer.
Preferably, after step S6, an insulating dielectric protection layer is grown on the side of the upper electrode material layer and above the intermediate phase-change material layer;
alternatively, after step S6, there is no need to grow an insulating dielectric protection layer on the side of the upper electrode material layer and above the middle phase-change material layer.
The above-described preferred features may be combined with each other as long as they do not conflict with each other.
Generally, compared with the prior art, the above technical solution conceived by the present invention has the following beneficial effects:
1. for the low-resistance crystalline state, the unit is connected into a circuit by constructing an asymmetric upper electrode structure and an asymmetric lower electrode structure, current flows vertically between an upper potential surface and a lower potential surface, the equivalent surface distance L is increased, the overlapped opposite surface integral quantity is small, and the equivalent sectional area S is reduced compared with the opposite vertical electrode structure, so that the equivalent resistance R is increased, the working current is reduced, the tunneling of large current is avoided, and the service life of a device is prolonged.
2. According to the vertical electrode configuration structure for the nanoscale phase-change memory unit and the processing method thereof, due to the fact that the asymmetric upper and lower electrode structures are constructed, when the positive and opposite integral quantity plays a role, the non-positive and opposite integral quantity shunts the current of a series channel, current diffusion in the series process is increased, the working current is reduced, the smaller the working current is, and the more difficultly the metastable crystal phase structure is broken down.
Drawings
FIG. 1 is an expanded schematic diagram of a vertical electrode configuration for nanoscale phase-change memory cells in accordance with an embodiment of the present invention, with a cross-section corresponding to a top view.
FIG. 2 is a process flow diagram of a method of fabricating a vertical electrode configuration for a nanoscale phase-change memory cell in accordance with an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other. The present invention will be described in further detail with reference to specific embodiments.
As a preferred embodiment of the present invention, as shown in FIG. 1, the present invention provides a vertical electrode configuration for nanoscale phase-change memory cells, wherein: the vertical electrode arrangement 100 includes an upper electrode material layer 120, an intermediate phase change material layer 130, and a lower electrode material layer 140.
The upper electrode material layer 120 and the lower electrode material layer 140 are asymmetric upper and lower electrode structures, and have front-to-face integral quantities with overlapped horizontal projection areas (the upper and lower electrodes and the intermediate phase change material are in an intersecting relationship), and also have non-front-to-face integral quantities with non-overlapped projection areas, and the front-to-face integral quantities are all correspondingly provided with the intermediate phase change material layer 130, and some or all of the non-front-to-face integral quantities are also correspondingly provided with the intermediate phase change material layer 130, as shown in fig. 1. An insulating dielectric protection layer 150 is disposed on a side of the lower electrode material layer 140 and below the intermediate phase change material layer 130, and preferably, the insulating dielectric protection layer 150 fills a non-right-to-face integral amount below the upper electrode material layer 120.
In this application, the upper electrode material layer 120 and the lower electrode material layer 140 may be regarded as common two-terminal devices for source-drain terminal exchange.
The upper electrode material layer 120 and the lower electrode material layer 140 are not formed based on the same photolithography and exposure process in the manufacturing process, and may use different electrode materials for life protection.
An insulating dielectric protection layer, such as SiO2, may be present on the upper electrode material layer 120 depending on the application, and is not shown here, or may not be provided.
The upper and lower electrodes are close to the middle phase-change material layer 130, and are the upper electrode contact surface 120A and the lower electrode contact surface 140A, and also there may be a metal adhesion layer or an electrode matching layer, respectively, as the case may be, or the metal adhesion layer or the electrode matching layer may be directly contacted with or not provided.
For inert electrodes (e.g. Ti3W7) and well-configured chemical potentials phase change materials (e.g. Ge2Sb2Te5), no additional layers are needed, and the upper electrode material layer 120 and the lower electrode material layer 140 are in direct contact with the intermediate phase change material layer 130.
For active electrode materials such as Pt, Ag, etc., a metal adhesion layer or electrode matching layer (e.g., Ti) is required.
The intermediate phase-change material layer 130 uses chalcogenide (chalcogenes) materials as functional layers, adopts Ge-Sb-Te series or AIST series phase-change materials, or uses non-chalcogenide Ge-Sb series phase-change materials; the processes involving the change of physical properties during the device operation mainly occur at the position of the middle phase change material layer 130 near the upper electrode contact surface 120A and the lower electrode contact surface 140A.
The insulating dielectric protection layer 150 on the side of the lower electrode material layer 140 is necessary, however, depending on the application, there may be an insulating dielectric protection layer 150 on the side of the upper electrode material layer 120 and above the intermediate phase change material layer 130, and preferably, the insulating dielectric protection layer 150 fills up the non-direct-to-surface integral quantity on the lower electrode material layer 140; the insulating dielectric protection layer 150 may not be provided depending on the application.
As shown in FIG. 2, the method for fabricating a vertical electrode configuration structure for nanoscale phase-change memory cells according to the present invention comprises the following steps:
s1, first, a photoresist mask pattern of the lower electrode material layer 140 and a calibration pattern for aligning the intermediate phase-change material layer 130 and the upper electrode material layer 120 are formed on the silicon substrate through a first photolithography exposure process.
S2, growing the lower electrode material layer 140 by magnetron sputtering, removing the photoresist in the first photolithography exposure step by a photoresist stripping step (stripping or etching), and depositing an insulating protective layer 150 (e.g. SiO2) to fill the lateral gap (e.g. the left blank of the lower electrode material layer in the cross-sectional view of fig. 2) formed by photolithography of the lower electrode material layer 140; and then the surface is flattened through Chemical Mechanical Polishing (CMP) to finish the preparation of the lower electrode material layer.
S3, before the preparation of the intermediate phase-change material layer 130 is started, a photoresist mask pattern of the intermediate phase-change material layer 130 is formed on the upper surface of the planarized lower electrode material layer 140 using the second photolithography exposure process using the calibration pattern of step S1.
S4, growing the intermediate phase change material layer 130 on the lower electrode material layer 140 and the insulating medium protection layer 150 by magnetron sputtering, and removing the photoresist of the second photoetching exposure process by a photoetching photoresist removing process (stripping or etching mode). The intermediate phase-change material layer 130 is made of chalcogenide compounds including but not limited to Ge-Sb-Te series phase-change materials and AIST series phase-change materials, and the growth thickness varies from tens of nanometers to tens of nanometers as required. At this time, an insulating dielectric protection layer is required between the intermediate phase change material layers 130 of different phase change memory cells to isolate the phase change material layers of the cells. And then, flattening the surface through Chemical Mechanical Polishing (CMP) to finish the preparation of the intermediate phase-change material layer.
S5, before the preparation of the upper electrode material layer 120 is started, a third photolithography exposure process is used to form a photoresist mask pattern of the upper electrode material layer 120 on the upper surface of the planarized intermediate phase change material layer 130 by using the calibration pattern in step S1.
S6, growing an upper electrode material layer 120 by magnetron sputtering in a mode of forming an asymmetric upper and lower electrode structure with the lower electrode material layer 140, and removing photoresist of a third photoetching exposure process through a photoetching photoresist removing process (a stripping or etching mode); the upper electrode material layer 120 and the lower electrode material layer 140 may perform source-drain exchange.
Preferably, if the lower electrode material layer 140 is selected to be an inert electrode well matched with the intermediate phase-change material to form a combination (e.g., the inert electrode is selected to be Ti3W7, and the lower phase-change material is selected to be Ge2Sb2Te5), the deposition of the intermediate phase-change material layer 130 is directly performed on the lower electrode material layer 140 and the insulating dielectric protection layer 150;
and/or the presence of a gas in the gas,
if the upper electrode material layer 120 is selected to be an inert electrode well matched with the intermediate phase-change material to form a combination (e.g., the inert electrode is selected to be Ti3W7, and the lower phase-change material is selected to be Ge2Sb2Te5), the deposition of the upper electrode material layer 120 is directly performed on the intermediate phase-change material layer 130.
Preferably, if the lower electrode material layer 140 is selected from active electrodes such as Pt, Ag, etc., a metal adhesion layer or an electrode matching layer (e.g., Ti) is grown on the electrode contact surface 140A between the lower electrode material layer 140 and the intermediate phase-change material layer 130; forming a photoresist mask pattern of the intermediate phase-change material layer 130 on the upper surface of the metal adhesion layer or the electrode matching layer by using the calibration pattern in the step S1 and using a second photolithography exposure process, and then depositing the intermediate phase-change material layer 130 on the metal adhesion layer or the electrode matching layer;
and/or the presence of a gas in the gas,
if the upper electrode material layer 120 is selected from active electrodes such as Pt, Ag, etc., a metal adhesion layer or an electrode matching layer (e.g., Ti) is grown on the electrode contact surface 120A between the middle phase change material layer 130 and the upper electrode material layer 120, a photoresist mask pattern of the upper electrode material layer 120 is formed on the upper surface of the metal adhesion layer or the electrode matching layer by using the calibration pattern in step S1 and the third photolithography exposure process, and then the upper electrode material layer 120 is deposited on the metal adhesion layer or the electrode matching layer.
Preferably, the upper electrode material layer 120 and the lower electrode material layer 140 are respectively made of different electrode materials for life protection.
Preferably, after step S6, an insulating dielectric protection layer, such as SiO2, may be grown on the upper electrode material layer 120 according to different applications, or the insulating dielectric protection layer may not be grown.
Preferably, after step S6, an insulating dielectric protection layer 150 may be grown on the side of the upper electrode material layer 120 and above the middle phase change material layer 130, or the insulating dielectric protection layer 150 may not be grown depending on the application.
As shown in FIG. 1, the unit is connected into the circuit, the current flows vertically between the upper potential surface and the lower potential surface, and the qualitative estimation value is based on the general resistance calculation formula
The resistivity constant rho is kept unchanged, compared with a structure of the asymmetric upper electrode and the asymmetric lower electrode, the equivalent plane distance L is increased, the equivalent sectional area S is reduced, and therefore the equivalent resistance R is increased. The thickness of the phase change material layer prepared in the process is generally below 20 nanometers, and the plane process size is usually about two orders of magnitude larger, so that the contribution of non-right-to-face integral quantity to the resistance value is far smaller than the right-to-face area, when the right-to-face area is reduced to 1/x of the original area, the equivalent surface distance L can be regarded as unchanged, and the equivalent sectional area S is reduced to 1/x of the original area, the resistance value is increased by x times, the working current can be effectively reduced, the tunneling of large current is avoided, and the service life of the device is prolonged.
By constructing an asymmetric upper electrode structure and an asymmetric lower electrode structure, when the positive and opposite integral quantities play the roles, the non-positive and opposite integral quantities shunt the current of a series passage, the current diffusion in the series process is increased, the working current is reduced, and the smaller the working current is, the less the metastable crystal phase structure is easy to break down.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. A method of fabricating a vertical electrode arrangement for a nanoscale phase-change memory cell, wherein the vertical electrode arrangement (100) comprises an upper electrode material layer (120), a middle phase-change material layer (130), and a lower electrode material layer (140), and wherein the method of fabrication and use comprises the steps of:
s1, firstly, forming a photoresist mask pattern of a lower electrode material layer (140) and a calibration pattern for aligning the intermediate phase change material layer (130) and the upper electrode material layer (120) on the silicon substrate through a first photoetching exposure process;
s2, growing a lower electrode material layer (140), removing the photoresist in the first photoetching exposure process through a photoresist removing process, and depositing an insulating dielectric protection layer (150) to fill a lateral gap formed after photoetching of the lower electrode material layer (140);
s3, before the preparation of the intermediate phase-change material layer (130) is started, utilizing the calibration graph in the step S1, and forming a photoresist mask graph of the intermediate phase-change material layer (130) on the upper surface of the lower electrode material layer (140) by using a second photoetching exposure process;
s4, growing an intermediate phase change material layer (130) on the lower electrode material layer (140) and the insulating medium protection layer (150), and removing the photoresist of the second photoetching exposure process through a photoetching photoresist removing process;
s5, before preparing the upper electrode material layer (120), forming a photoresist mask pattern of the upper electrode material layer (120) on the upper surface of the intermediate phase-change material layer (130) by using the third photoetching exposure process by using the calibration pattern in the step S1;
s6, growing an upper electrode material layer (120) in a mode of forming a partially overlapped upper and lower electrode structure with a lower electrode material layer (140), wherein one of the upper electrode material layer (120) and the lower electrode material layer (140) has an orthogonal-to-surface integral quantity with overlapped horizontal projection areas relative to the other, and also has a non-orthogonal-to-surface integral quantity with non-overlapped horizontal projection areas, the orthogonal-to-surface integral quantity is provided with the intermediate phase change material layer (130) in a corresponding mode, and part or all of the non-orthogonal-to-surface integral quantity is provided with the intermediate phase change material layer (130) in a corresponding mode; removing the photoresist in the third photoetching exposure process through a photoetching photoresist removing process; the upper electrode material layer (120) and the lower electrode material layer (140) may be exchanged for source and drain.
2. The method of fabricating a vertical electrode arrangement for nanoscale phase-change memory cells as claimed in claim 1, characterized in that:
in the steps S2, S4 and S6, the growth of the lower electrode material layer (140), the intermediate phase change material layer (130) and the upper electrode material layer (120) is performed by magnetron sputtering.
3. The method of fabricating a vertical electrode arrangement for nanoscale phase-change memory cells as claimed in claim 1, characterized in that:
in the photoresist stripping process in step S2, step S4 and/or step S6, a stripping or etching method is used.
4. The method of fabricating a vertical electrode arrangement for nanoscale phase-change memory cells as claimed in claim 1, characterized in that:
if the lower electrode material layer (140) adopts an inert electrode matched with the intermediate phase-change material, directly depositing the intermediate phase-change material layer (130) on the lower electrode material layer (140) and the insulating medium protection layer (150);
and/or the presence of a gas in the gas,
if the upper electrode material layer (120) is selected to be an inert electrode compatible with the intermediate phase change material, the deposition of the upper electrode material layer (120) is performed directly on the intermediate phase change material layer (130).
5. The method of fabricating a vertical electrode arrangement for nanoscale phase-change memory cells as claimed in claim 1, characterized in that:
if the lower electrode material layer (140) is an active electrode, a metal adhesion layer or an electrode matching layer is grown on an electrode contact surface (140A) between the lower electrode material layer (140) and the middle phase-change material layer (130); forming a photoresist mask pattern of the intermediate phase-change material layer (130) on the upper surface of the metal adhesion layer or the electrode matching layer by using the calibration pattern in the step S1 and a second photoetching exposure process, and then depositing the intermediate phase-change material layer (130) on the metal adhesion layer or the electrode matching layer;
and/or the presence of a gas in the gas,
if the upper electrode material layer (120) is selected as an active electrode, a metal adhesion layer or an electrode matching layer is grown on an electrode contact surface (120A) between the intermediate phase change material layer (130) and the upper electrode material layer (120), a photoresist mask pattern of the upper electrode material layer (120) is formed on the upper surface of the metal adhesion layer or the electrode matching layer by using the scaling pattern in the step S1 and a third photoetching exposure process, and then the upper electrode material layer (120) is deposited on the metal adhesion layer or the electrode matching layer.
6. The method of fabricating a vertical electrode arrangement for nanoscale phase-change memory cells as claimed in claim 1, characterized in that:
between step S4 and step S5, there are also the steps of:
an insulating dielectric protection layer is required between the respective intermediate phase change material layers (130) of the different phase change memory cells to isolate the phase change material layers of the respective cells.
7. The method of fabricating a vertical electrode arrangement for nanoscale phase-change memory cells as claimed in claim 1, characterized in that:
the upper electrode material layer (120) and the lower electrode material layer (140) are made of different electrode materials respectively.
8. The method of fabricating a vertical electrode arrangement for nanoscale phase-change memory cells as claimed in claim 1, characterized in that:
the intermediate phase-change material layer (130) is made of chalcogenide compounds or non-chalcogenide Ge-Sb series phase-change materials.
9. The method of fabricating a vertical electrode arrangement for nanoscale phase-change memory cells as claimed in claim 1, characterized in that:
after step S6, growing an insulating dielectric protection layer on the upper electrode material layer (120);
alternatively, after step S6, an insulating dielectric protection layer need not be grown over the upper electrode material layer (120).
10. The method of fabricating a vertical electrode arrangement for nanoscale phase-change memory cells as claimed in claim 1, characterized in that:
after the step S6, growing an insulating medium protection layer (150) on the side of the upper electrode material layer (120) and above the intermediate phase-change material layer (130);
alternatively, after step S6, the insulating dielectric protection layer (150) need not be grown on the side of the upper electrode material layer (120) and above the intermediate phase change material layer (130).
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| CN1983617A (en) * | 2005-11-28 | 2007-06-20 | 尔必达存储器株式会社 | Electrically rewritable non-volatile memory element and method of manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1983617A (en) * | 2005-11-28 | 2007-06-20 | 尔必达存储器株式会社 | Electrically rewritable non-volatile memory element and method of manufacturing the same |
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| Title |
|---|
| 非对称相变存储器单元制备工艺及性能研究;温学鑫;《CNKI 中国优秀硕士学位论文全文数据库（电子期刊） 信息科技辑》;20130731;"3 非对称相变存储器单元结构设计及制备工艺研究"部分 * |
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