CN102446956A

CN102446956A - Semiconductor high-power device and manufacturing method thereof

Info

Publication number: CN102446956A
Application number: CN2011102593544A
Authority: CN
Inventors: 万小敏
Original assignee: Individual
Current assignee: Individual
Priority date: 2011-09-05
Filing date: 2011-09-05
Publication date: 2012-05-09
Anticipated expiration: 2031-09-05
Also published as: CN102446956B

Abstract

The invention relates to the technical field of a semiconductor device and a manufacturing method thereof, and particularly relates to a semiconductor high-power device with a Super-Junction structure and a simple and effective implementation method thereof. The structure comprises a central region used for finishing positive operation and a terminal region used for assisting to finish reverse operation, wherein both the regions are provided with P/N pillars, which are successively arranged; an N type device is taken as a example: the width and the depth of P regions in both the regions are same, and the gaps of the P regions in both the regions are also same; and polysilicon or/and metal connected with the P pillars is/are increased on the surface so as to serve as a field plate, when the structure undergoes high voltage, the surface electric field is lower than the critical electric field, finally the P/N pillar regions comprising the central area and a periphery region are all effectively exhausted, and breakdown is firstly generated in the central area. The semiconductor device and the manufacturing method thereof provided by the invention have the advantages that the design is simple, devices with different breakdown potential standards are obtained only by properly adjusting the spacing and quantity of the field plate; the manufacture is simple, all P/N pillars are composed of standard P/N pillar units, and meanwhile, and the semiconductor device is suitable for a deep groove process and a multiple ion implantation process; and the structure is reliable, reverse voltage resistance can be effectively realized, and the yield of a product is effectively improved.

Description

A kind of semiconductor high power device and manufacturing approach thereof

Technical field

Designing semiconductor device of the present invention and preparation method thereof technical field is refered in particular to high-power body device of partly leading of a kind of Super-Junction of having structure and simple and effective implementation method thereof.

Background technology

Metal-oxide layer-semiconductor-field-effect transistor; (Metal-Oxide-Semiconductor Field-Effect Transistor MOSFET) is a kind of field-effect transistor (field-effect transistor) that can be widely used in analog circuit and digital circuit to be called for short metal-oxide half field effect transistor.MOSFET is different according to the polarity of its " passage ", can be divided into the MOSFET of N type and P type, is called NMOSFET and PMOSFET usually again.Common N type MOSFET adopts a P type silicon semiconductor material as substrate, diffuses to form N type zone above that, covers insulating barrier at end face, on N type zone, the hole is set at last, as electrode.In order to improve the characteristic of some parameter, as improving operating current, raising operating voltage, the conducting resistance that reduces, raising switching characteristic etc. various structure and technology are arranged, constitute structures such as so-called VMOS, DMOS, TMOS.

For common VDMOSEFT (vertical bilateral diffusion metallic oxide field effect pipe), when puncture voltage requires when increasingly high, conducting resistance is also increasingly high, common " the silicon limit " for common VDMOSEFT said that Here it is.The structure of breaking " silicon limit " is the Super-Junction structure, and it replaces to the 3D structure of P/N post to being arranged in order with drift region replacement or the part of common VDMOSEFT usually, and PN junction is arranged in this inside configuration according to certain rules.

For high voltage power device, it can be divided into the zone (being active area) of conducting electricity under the conducting state and turn-off and bear under the high pressure conditions as the zone (be termination environment) of active area to the transition of chip edge.The termination environment is most important, concerns that not only can device reach specified puncture voltage, more is related to the integrity problem of devices switch process and non-normal working situation.

For the device of a Super-Junction structure, epitaxial layer concentration is about 10～20 times of VDMOSEFT of same breakdown voltage grade, and this confirms according to process conditions.Poisson's equation through classics is known: the width of a certain side depletion layer of PN junction is to follow the square root of this side impurity concentration to be inversely proportional to; So about 1/3. before depletion width can be compressed to and increase when concentration is increased to 10 times must increase depletion width to satisfy specified breakdown voltage value effectively under the constant basically situation of critical electric field.In the active area of Super-Junction, the depletion layer through adjacent longitudinal P N knot is together with each other and sets up an enough wide and depletion layer completely.If there is not terminal structure, in the outside of the PN junction of Super-Junction device outermost do not have other longitudinally PN junction come to combine with it to accomplish an effectively depletion layer fully; In case can not effectively form depletion layer, electric field is inevitable so concentrates at this, realize that breakdown voltage rating is with impossible.The present invention introduces additional charge on the surface through at terminal end surface increase field plate when bearing high voltage, and its surface field is distributed to whole terminal, and the electric field that suppresses the part is concentrated, thereby realizes the puncture voltage of requirement.

About the terminal structure of Super-Junction device popular have two kinds: a kind of is that the mode that adopt to change P/N post width and/or spacing satisfies the charge balance at terminal; This mode designs difficulty very, because the change of one of them width or spacing can influence the whole charge balance state in terminal; And also relatively more difficult at deep trouth about middle realization, because changed the depth ratio of groove; Another kind is to adopt dark and wide groove to isolate, the general dielectric material of filling in the groove, and this is a great challenge on technology.

Summary of the invention

Technical problem to be solved by this invention just is to provide a kind of and is easy to design, can not extra increase technology difficulty, the cost a kind of semiconductor high power device and the manufacturing approach thereof that more have superiority; The high power device of making through the present invention does not increase extra processing step and guarantees sufficiently high yields, can solve the terminal problem of Super-Junction device through the present invention.

In order to solve the problems of the technologies described above; The present invention has adopted following technical scheme; The present invention is through the PN post in the peripheral introducing of active area ring-type; The active area at next-door neighbour center, several wide equally spaced P/N posts are closely arranged from inside to outside successively, and the width of P/N post is fully the same with active area P/N post with spacing; The field plate that is made up of the metal and/or the polycrystalline of certain width also is arranged in order by certain spacing from inside to outside, and is connected with corresponding P or N post through contact hole.Through suitable increase or reduce the quantity of terminal P/N post, increase or reduce simultaneously corresponding field plate quantity accordingly, promptly can under the situation that field plate length and spacing are adjusted slightly, satisfy the device of different breakdown voltage ratings.This theory is fully based on charge balance concept, so be not only applicable to the Super-Junction device, even Semi Super-Junction device, this structure is also suitable fully.

Furthermore, in the technique scheme, the surfaces of active regions structure is the DMOSFET structure that comprises planar gate and grooved grid in the structure of high power device, and P/N posts all in the entire device scope all have identical width, spacing and the degree of depth.

First kind of technical scheme that manufacture method of the present invention adopted is: its making step comprises: the first step, the growth epitaxial loayer identical with the substrate conduction type on the substrate of first kind conduction type; Second step, adopt the ion etching mode in epitaxial loayer, to slot, the cell body degree of depth is no more than the thickness of epitaxial loayer; The 3rd step, the silicon epitaxy layer of second type of conduction type of growth in groove; In the 4th step, flattening surface obtains having the semi-finished product of alternate P/N post; The 5th step, on above-mentioned semi-finished product, process according to the metal oxide layer semiconductor field effect transistor structure, obtain the device finished product; Offer several wide equally spaced grooves in the above-mentioned epitaxial loayer, and groove is arranged in order.

Second kind of technical scheme that manufacture method of the present invention adopted is: its making step comprises: the first step, the epitaxial loayer identical with the substrate conduction type of on the substrate of first kind conduction type, repeatedly growing; And after outer layer growth each time, second type of electric conducting material of implanting impurity ion formation in specific zone; Second step, to anneal and knot, the ions diffusion that order is injected also joins together, and forms alternate P/N post semi-finished product; The 3rd step, on above-mentioned semi-finished product, process according to the metal oxide layer semiconductor field effect transistor structure, obtain the device finished product; The zone of above-mentioned repeatedly implanting impurity ion is wide, equidistant each other, and is arranged in order.

Furthermore; In the technical scheme of above-mentioned two kinds of manufacture methods; Described high power device comprises N type semiconductor device and P type semiconductor device; Wherein making the first kind conductivity type material that the N type semiconductor device adopted is: other semi-conducting materials of doped type N impurity silicon or doped type N impurity, and described second type of conductivity type material is: mix p type impurity silicon or mix other semi-conducting materials of p type impurity; First kind conductivity type material, second types of material that making P type semiconductor device is adopted are opposite with above-mentioned N type semiconductor equipment.

The present invention is a kind of in the structure that is not changing adding field plate under groove depth, groove width and the separation prerequisite, and than traditional terminal structure, it is all having more advantage aspect design cost and the manufacturing cost two.At the state that turn-offs, when device bears big voltage, field plate is stored charge under effect of electric field, has suppressed concentrating of electric field, has accomplished the work of charge balance, thereby in the terminal, has formed depletion layer effectively, realizes the puncture voltage that requires; In opening, the PN junction depletion layer is very thin, and electric current arrives another electrode through first kind conductive region and raceway groove from an electrode.

Description of drawings

Fig. 1 is first kind of common Super-Junction semiconductor device structure sketch map;

Fig. 2 is second kind of common Super-Junction semiconductor device structure sketch map;

Fig. 3 is a structural representation of the present invention;

Fig. 4 a-4b is a domain sketch map of the present invention;

Fig. 5 is simulation result figure of the present invention.

Description of reference numerals:

1 substrate, 2 epitaxial loayer 3P columnar region 4Body districts

5 source area 6 grids, 7 termination environments second type of electric conducting material, 8 grid BUS

9 field plates, 10 insulating material

I representes first kind conductive type semiconductor material;

II representes second type of conductive type semiconductor material.

Embodiment

High power device of the present invention can be N type semiconductor device or P type semiconductor device; Wherein making the first kind conductivity type material that the N type semiconductor device adopted is: other semi-conducting materials of doped type N impurity silicon or doped type N impurity, and described second type of conductivity type material is: mix p type impurity silicon or mix other semi-conducting materials of p type impurity; First kind conductivity type material, second types of material that making P type semiconductor device is adopted are opposite with above-mentioned N type semiconductor equipment.Below in the explanation, suppose that I is the n type single crystal silicon material, II is the p type single crystal silicon material.

See Fig. 1, shown in 2; This is present common Super-Junction semiconductor device structure sketch map; It comprises: substrate 1 and epitaxial loayer 2, the P/N post that is arranged in epitaxial loayer 2, source area 5 and P-Body district 4, and 6 grids,

screen BUS

8 and 10 insulating material.Wherein, I is the n type single crystal silicon material, and II is the p type single crystal silicon material.

See Fig. 3; Device of the present invention adopts MOSFET (metal oxide layer semiconductor field-effect transistor) structure; It comprises: substrate 1 and epitaxial loayer 2, the P/N post that is arranged in epitaxial loayer 2, source area 5 and P-Body district 4, wherein, introduce the P/N post of ring-type in the termination environment; The active area at next-door neighbour center, several wide equally spaced P/N posts are arranged in order from inside to outside; The field plate that is made up of metal and/or polysilicon is spaced from inside to outside, and is connected with corresponding P post through contact hole.

Wherein active area comprises: P columnar region 3, P-Body zone 4, source area 5 and grid 6; The termination environment comprises: P columnar region 7, grid BUS 8 and field plate 9.Grid BUS 8 also adopts metal and/or polycrystalline to constitute.

Embodiment is that main body is divided into two kinds with the Super-Junction structure.Here be example with N type silicon device.This method may further comprise the steps:

The first step, the growth epitaxial loayer identical on the N+ substrate with the substrate conduction type;

Second step, adopt the ion etching mode in epitaxial loayer, to slot, the cell body degree of depth is no more than the thickness of epitaxial loayer;

The 3rd step, growing P-type silicon epitaxy layer in groove;

In the 4th step, flattening surface obtains having the semi-finished product of alternate P/N post;

The 5th step, on above-mentioned semi-finished product, process according to the metal oxide layer semiconductor field effect transistor structure, obtain the device finished product;

Offer several wide equally spaced grooves on the above-mentioned epitaxial loayer, and groove is arranged in order.

What this method adopted is deep trouth technology; This method is an extension N type silicon on the N+ of low-resistance substrate 1 at first in brief; Then the etching deep trouth and in groove growing P-type silicon, accomplish the common DMOSFET structure on surface after the flattening surface, the field plate at terminal belongs to the part of common DMOSFET structure.

The present invention also can adopt another kind of method, specifically comprises the steps:

The first step, the epitaxial loayer identical of on the N+ substrate, repeatedly growing with the substrate conduction type; And after outer layer growth each time, implanting impurity ion forms second type of electric conducting material in the specific region;

Second step, to anneal and knot, the ions diffusion that order is injected also joins together, and forms alternate P/N post semi-finished product;

The 3rd step, on above-mentioned semi-finished product, process according to the metal oxide layer semiconductor field effect transistor structure, obtain the device finished product;

The zone of repeatedly prolonging layer and implanting impurity ion on the above-mentioned substrate is wide, equidistant each other, and is arranged in order.

Said method is repeatedly a repeatedly injection technology of extension; In brief; Be that whole Super-Junction structure sheaf is divided into extension completion several times, injecting p type impurity in the zone of needs after the extension each time, all extensions are accomplished afterwards through annealing and knot with injection; Making the p type impurity of each time injection be connected as a single entity and form the P post, is to accomplish common DMOSFET structure at last equally.

The present invention makes the Super-Junction device that adopts the field plate terminal structure can be based on silica-based and reach in silica-based identical performance or any material of superior function more.

In making process of the present invention; Charge balance is most important in the Super-Junction structure; Doping content can directly have influence on maximum voltage and the conducting resistance that device can bear, thus need ten minutes careful to doping content assurance, must be within the controlled scope of technology.

(1) the present invention increases the field plate of some certain-lengths through the device terminal area; Introduce extra electric charge so that entire device can reach desirable charge balance in terminal end surface when bearing voltage; Can set up complete depletion layer, reach specified breakdown voltage value.The present invention is simply distinct except thinking in design; Entire device has no harsh requirement to the Super-Junction structure sheaf: P/N post width or P/N intercolumniation must be adjusted in the terminal of traditional Super-Junction device, and this deep trouth technological requirement for main flow is harsh unusually; On all four groove width and on all four spacing guaranteed to technology require minimumly, improved tolerance, thereby can guarantee high stability, yields and reliability technology.

(2) the present invention is applicable to different manufacture crafts: in deep trouth technology, remarkable advantages is arranged; The present invention simultaneously also is applicable to and the technology injected of ion repeatedly of extension repeatedly, and design can become simpler, more easily the charge balance problem at four angles of processing apparatus.

(3) the present invention is applicable to the device of different puncture voltages, and the following needs of economizing most at area of prerequisite suitably increase or reduce the terminal P/N band of column and field plate quantity.

(4) quantity of P/N post, concrete width and spacing are decided according to the technological ability and the design requirement of reality in the structure of the present invention, and the doping content of P/N post is determined by width, spacing and the technology accuracy of P/N post jointly, at present generally at 1～4e15/cm ³Magnitude.The developing direction of Super-Junction is that the width and the spacing of P/N post is littler, and doping content is higher, thereby resistance is littler under the prerequisite that does not influence puncture voltage.When technological ability improved, for example the depth-to-width ratio of groove can do more in the deep trouth technology, and perhaps the precision of ion implantation dosage is higher, just can be littler for the width and the spacing of the device P/N post of certain puncture voltage, and doping content just can be higher.And only need make simple change for the terminal of structure of the present invention: the firstth, the width of scaled field plate and spacing; The secondth, the quantity that increases terminal P/N post and field plate remains unchanged to satisfy the terminal integral width, keeps Electric Field Distribution constant basically.

This terminal structure is equally applicable to Semi Super-Junction device and the IGBT device that has adopted the Super-Junction structure.

See shown in Fig. 4 a, the 4b that this is the domain sketch map of structure of the present invention: Fig. 4 a wherein: be applicable to the domain structure of bar shaped cellular, what color was darker among Fig. 4 a is P type doped region, light areas represent polycrystalline perhaps/with the metal field plate.Fig. 4 b is a kind of distortion of Fig. 4 a, and it is applicable to the domain structure of square/circle/hexagon cellular.

See shown in Figure 5ly, this is a structure simulation design sketch of the present invention.

Claims

1. semiconductor high power device; It is characterized in that: this device adopts the metal oxide layer semiconductor field effect transistor structure; It comprises: the cellular structure and the terminal field plate structure of substrate and epitaxial loayer, the P/N post that is arranged in epitaxial loayer and P/N column top; Wherein, the peripheral P/N post of introducing ring-type of active area, several wide equally spaced P/N posts are arranged in order from inside to outside; The field plate that is made up of metal and/or polysilicon also is spaced with the PN post from inside to outside, and is connected with corresponding P or N post through contact hole.

2. the manufacturing approach of a semiconductor high power device, it is characterized in that: this manufacturing approach may further comprise the steps:

The first step, the growth epitaxial loayer identical on the substrate of first kind conduction type with the substrate conduction type;

The 3rd step, the silicon epitaxy layer of second type of conduction type of generation in groove;

Have a plurality of wide equally spaced grooves in the above-mentioned epitaxial loayer, and groove is arranged in order.

3. the manufacturing approach of a kind of semiconductor high power device according to claim 2; It is characterized in that: described high power device comprises N type semiconductor device and P type semiconductor device; Wherein making the first kind conductivity type material that the N type semiconductor device adopted is: other semi-conducting materials of doped type N impurity silicon or doped type N impurity, and described second type of conductivity type material is: mix p type impurity silicon or mix other semi-conducting materials of p type impurity; First kind conductivity type material, second types of material that making P type semiconductor device is adopted are opposite with above-mentioned N type semiconductor equipment.

4. the manufacturing approach of a semiconductor high power device, it is characterized in that: this manufacturing approach may further comprise the steps:

The first step, the extension epitaxial loayer identical repeatedly on the substrate of first kind conduction type with the substrate conduction type; And after outer layer growth each time, second type of electric conducting material of implanting impurity ion formation in specific zone;

The zone of above-mentioned implanting impurity ion is wide, equidistant each other, and is arranged in order.

5. the manufacturing approach of a kind of semiconductor high power device according to claim 4; It is characterized in that: described high power device comprises N type semiconductor device and P type semiconductor device; Wherein making the first kind conductivity type material that the N type semiconductor device adopted is: doped type N impurity silicon or other semi-conducting materials of doped type N impurity, and described second type of conductivity type material is: mix p type impurity silicon or mix other semi-conducting materials of p type impurity; First kind conductivity type material, second types of material that making P type semiconductor device is adopted are opposite with above-mentioned N type semiconductor equipment.